CN110825653B - Memory management method and memory controller - Google Patents
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- CN110825653B CN110825653B CN201810902566.1A CN201810902566A CN110825653B CN 110825653 B CN110825653 B CN 110825653B CN 201810902566 A CN201810902566 A CN 201810902566A CN 110825653 B CN110825653 B CN 110825653B
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- 238000007726 management method Methods 0.000 title claims abstract description 88
- 230000004044 response Effects 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 12
- 238000004064 recycling Methods 0.000 claims description 122
- 238000011084 recovery Methods 0.000 claims description 70
- 230000000717 retained effect Effects 0.000 claims 1
- 230000005540 biological transmission Effects 0.000 description 11
- 238000013523 data management Methods 0.000 description 9
- 238000013507 mapping Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000005055 memory storage Effects 0.000 description 6
- 238000012937 correction Methods 0.000 description 5
- 238000004891 communication Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000008672 reprogramming Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0253—Garbage collection, i.e. reclamation of unreferenced memory
- G06F12/0261—Garbage collection, i.e. reclamation of unreferenced memory using reference counting
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Abstract
The invention provides a memory management method and a memory controller. The method comprises the following steps: identifying one or more reclamation block strings of a plurality of block strings of a rewritable non-volatile memory module on which the garbage reclamation operation is performed in response to completing the garbage reclamation operation; updating a garbage collection information table in a buffer memory according to the one or more collection block strings; and writing the garbage collection information table into the rewritable nonvolatile memory module.
Description
Technical Field
The present invention relates to a memory management method, and more particularly, to a memory management method and a memory controller suitable for a memory device configured with a rewritable nonvolatile memory module.
Background
In general, a memory controller of a memory device configured with a rewritable nonvolatile memory module performs garbage collection operation to move effective data in a plurality of source physical blocks to a plurality of new physical blocks, and erases the plurality of source physical blocks to release space occupied by invalid data of the plurality of source physical blocks.
Conventionally, in the process of performing garbage collection operations on a plurality of physical blocks, when any information of the plurality of physical blocks changes, a Snapshot (snap shot) operation is used to save the information of the plurality of physical blocks originally maintained in a buffer memory and corresponding to the performed garbage collection operation to a rewritable nonvolatile memory module. In this way, during the execution of the garbage collection operation, a lot of time is consumed because the snapshot operation is frequently executed, which results in a lot of delay of the storage device.
Therefore, how to more efficiently save the information of the garbage collection operation to reduce the delay caused by performing the garbage collection operation, thereby improving the working efficiency of the storage device is one of the subjects of the study of the person skilled in the art.
Disclosure of Invention
The present invention provides a memory management method capable of recording a reclamation physical block, on which a garbage reclamation operation is performed, to a garbage reclamation information table and writing the garbage reclamation information table to a rewritable nonvolatile memory module only when the garbage reclamation operation is completed, and updating the garbage reclamation information table according to whether a plurality of reclamation physical blocks recorded in the garbage reclamation information table are used. In addition, the memory management method may also perform a restore operation to restore the garbage collection information table when a power-off event occurs.
An embodiment of the present invention provides a memory management method, which is suitable for a memory device configured with a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of physical blocks, and the plurality of physical blocks are grouped into a plurality of block strings. The method comprises the following steps: identifying one or more recycling block strings of the plurality of block strings on which the garbage recycling operation is performed in response to completing the garbage recycling operation; updating a garbage collection information table in a buffer memory according to the one or more collection block strings; and writing the garbage collection information table into the rewritable nonvolatile memory module.
An embodiment of the present invention provides a memory controller for controlling a memory device configured with a rewritable nonvolatile memory module. The memory controller includes: the garbage collection device comprises a connection interface circuit, a memory interface control circuit, a garbage collection management circuit unit and a processor. The connection interface circuit is used for being coupled to the host system. The memory interface control circuit is used for being coupled to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module is provided with a plurality of physical blocks, and the physical blocks are grouped into a plurality of block strings. The processor is coupled to the connection interface circuit, the memory interface control circuit, and the garbage collection management circuit unit. The garbage collection management circuit unit is used for identifying one or more recycling block strings which are used for executing the garbage collection operation in the plurality of block strings in response to completing the garbage collection operation, wherein the garbage collection management circuit unit is also used for updating a garbage collection information table in the buffer memory according to the one or more recycling block strings. The processor is configured to instruct the memory interface control circuit to write the garbage collection information table into the rewritable non-volatile memory module.
Based on the above, the memory management method and the memory controller provided by the embodiments of the present invention can record the recycling physical block executed with the garbage recycling operation to the garbage recycling information table and write the garbage recycling information table to the rewritable nonvolatile memory module only when the garbage recycling operation is completed. Thus, the working efficiency of the memory device can be improved.
In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a block diagram of a host system and a storage device according to an embodiment of the invention.
FIG. 2A is a flow chart of a memory management method according to an embodiment of the invention.
FIG. 2B is a flow chart of a memory management method according to an embodiment of the invention.
FIG. 3 is a schematic diagram of a plurality of block strings of a rewritable nonvolatile memory module according to an embodiment of the present invention.
Fig. 4 is a schematic diagram illustrating a data structure of a garbage collection information table according to an embodiment of the present invention.
Fig. 5 is a flowchart illustrating a recovery operation according to an embodiment of the present invention.
Description of the reference numerals
10: host system
20: storage device
110. 211: processor and method for controlling the same
120: host memory
130: data transmission interface circuit
210: memory controller
212: data management circuit
213: memory interface control circuit
214: error checking and correcting circuit
215: garbage collection management circuit unit
2151: garbage recycling execution circuit
2152: recovery block string recording circuit
216: buffer memory
217: power management circuit
220: rewritable nonvolatile memory module
230: connection interface circuit
S211, S212, S213: flow steps of memory management method
S221, S222, S223: flow steps of memory management method
D1: packaging
LUN1: logical number
P1 (1) to P1 (6), P1 (M-1), P1 (M), P2 (1) to P2 (6), P2 (M-1), P2 (M), P3 (1) to P3 (6), P3 (M-1), P3 (M), P4 (1) to P4 (6), P4 (M-1), P4 (M): physical block
P1 to P4: plane surface
BS (1) to BS (6), BS (M-1), BS (M): block string
400: garbage collection information table
DT: data label
TS: time stamp
TRBN: number of recovery block strings
RBI [1] -RBI [ X ]: reclaiming block string index values
PD: filling data
S51, S52, S53, S54, S55, S56, S57, S58, S59: flow step of recovery operation
Detailed Description
In this embodiment, the storage device includes a rewritable non-volatile memory module (re-writable non-volatile memory module) and a storage device controller (also referred to as a storage controller or a storage control circuit). In addition, the storage device is used with a host system so that the host system can write data to or read data from the storage device.
FIG. 1 is a block diagram of a host system and a storage device according to an embodiment of the invention.
Referring to fig. 1, a host system (HostSystem) 10 includes a Processor (Processor) 110, a host memory (HostMemory) 120, and a data transfer interface circuit (datatransfer interface circuit) 130. In the present embodiment, the data transmission interface circuit 130 is coupled (also referred to as electrically connected) to the processor 110 and the host memory 120. In another embodiment, the processor 110, the host memory 120, and the data transmission interface circuit 130 are coupled to each other using a system bus (SystemBus).
The storage device 20 includes a storage controller (storage controller) 210, a rewritable nonvolatile memory module (RewritableNon-volatile memory module) 220, and a connection interface circuit (connectionsterface) 230. The memory controller 210 includes a processor 211, a data management circuit (datamanagement circuit) 212, and a memory interface control circuit (MemoryInterface ControlCircuit) 213.
In the present embodiment, the host system 10 is coupled to the storage device 20 through the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform the data access operation. For example, the host system 10 may store data to the storage device 20 or read data from the storage device 20 via the data transfer interface circuit 130.
In the present embodiment, the processor 110, the host memory 120 and the data transmission interface circuit 130 may be disposed on a motherboard of the host system 10. The number of data transmission interface circuits 130 may be one or more. The motherboard may be coupled to the memory device 20 via a wired or wireless connection via the data transmission interface circuit 130. The storage device 20 may be, for example, a USB flash drive, a memory card, a solid state disk (SolidStateDrive, SSD), or a wireless memory storage device. The wireless memory storage device may be, for example, a near field communication (NearField Communication, NFC) memory storage device, a wireless facsimile (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a Bluetooth low energy memory storage device (e.g., iBeacon) or the like based on a variety of wireless communication technologies. In addition, the motherboard may also be coupled to various I/O devices such as a global positioning system (GlobalPositioningSystem, GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a speaker, etc. through a system bus.
In the present embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the high-speed peripheral component connection interface (PeripheralComponentInterconnectExpress, PCIExpress) standard. The data transmission interface circuit 130 and the connection interface circuit 230 use the rapid nonvolatile memory interface standard (Non-VolatileMemoryexpress, NVMe) protocol to transmit data.
However, it should be understood that the present invention is not limited thereto, and the data transmission interface circuit 130 and the connection interface circuit 230 may also be a Memory Stick (MS) interface standard, a Multi-chip package (Multi-chip package) interface standard, a multimedia memory card (MultiMediaCard, MMC) interface standard, an eMMC interface standard, a universal flash memory (UniversalFlashStorage, UFS) interface standard, an eMCP interface standard, a CF interface standard, an integrated drive electronics interface (IntegratedDevice Electronics, IDE) or other suitable standards, which conform to the parallel advanced technology attachment (ParallelAdvancedTechnology Attachment, PATA) standard, the institute of electrical and electronics engineers (institute of electrical and electronics) ElectronicEngineers, IEEE) 1394 standard, the serial advanced technology attachment (serial advanced TechnologyAttachment, SATA) standard, the universal serial bus (UniversalSerialBus, USB) standard, the SD interface standard, the ultra high speed-I (UHS-I) interface standard, the ultra high speed-II (UHS-I) interface standard, the memory stick (memory stick) interface standard, the Multi-chip package (Multi-chip package) interface standard, the mmc interface standard, the eMCP interface standard, or other suitable standards. In addition, in another embodiment, the connection interface circuit 230 may be packaged with the memory controller 210 in a chip, or the connection interface circuit 230 may be disposed outside a chip including the memory controller 210.
In the present embodiment, the host memory 120 is used for temporarily storing instructions or data executed by the processor 110. For example, in the present exemplary embodiment, the host memory 120 may be a Dynamic random access memory (Dynamic RandomAccessMemory, DRAM), a static random access memory (StaticRandomAccess Memory, SRAM), or the like. However, it should be understood that the present invention is not limited thereto and that host memory 120 may be other suitable memory.
The memory controller 210 is configured to execute a plurality of logic gates or control instructions implemented in hardware or firmware and perform operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 220 according to the instructions of the host system 10.
In more detail, the processor 211 in the memory controller 210 is hardware with operation capability, which is used to control the overall operation of the memory controller 210. Specifically, the processor 211 has a plurality of control instructions, and when the memory device 20 is operated, the control instructions are executed to perform operations such as writing, reading and erasing data.
It should be noted that, in the present embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CentralProcessingUnit, CPU), a Microprocessor (micro-processor), or other programmable processing units (micro processor), a digital signal processor (DigitalSignalProcessor, DSP), a programmable controller, an application specific integrated circuit (ApplicationSpecificIntegratedCircuits, ASIC), a programmable logic device (ProgrammableLogicDevice, PLD), or other similar circuit elements, which are not limited to this embodiment.
In one embodiment, the memory controller 210 also has read-only memory (not shown) and random access memory (not shown). In particular, the rom has a boot code (boot code), and when the memory controller 210 is enabled, the processor 211 executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 220 into the ram of the memory controller 210. The processor 211 then runs the control commands to perform data writing, reading and erasing operations. In another embodiment, the control instructions of the processor 211 may also be stored in a program code format in a specific area of the rewritable nonvolatile memory module 220, for example, in a physical memory unit dedicated to storing system data in the rewritable nonvolatile memory module 220.
In the present embodiment, as described above, the memory controller 210 further includes the data management circuit 212 and the memory interface control circuit 213. It should be noted that the operations performed by the various components of the memory controller 210 may also be considered operations performed by the memory controller 210.
The data management circuit 212 is coupled to the processor 211, the memory interface control circuit 213 and the connection interface circuit 230. The data management circuit 212 is configured to receive the instruction from the processor 211 to transmit data. For example, data is read from the host system 10 (e.g., host memory 120) via the connection interface circuit 230, and the read data is written into the rewritable nonvolatile memory module 220 via the memory interface control circuit 213 (e.g., write operations are performed according to write instructions from the host system 10). For another example, data is read from one or more physical units of the rewritable nonvolatile memory module 220 via the memory interface control circuit 213 (data may be read from one or more memory units in the one or more physical units) and the read data is written into the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 (e.g., a read operation is performed according to a read instruction from the host system 10). In another embodiment, the data management circuit 212 may also be integrated into the processor 211.
The memory interface control circuit 213 is used for receiving the instruction of the processor 211, and performs a write (also called Programming) operation, a read operation or an erase operation on the rewritable nonvolatile memory module 220 in cooperation with the data management circuit 212.
For example, the processor 211 may execute a sequence of write instructions to instruct the memory interface control circuit 213 to write data into the rewritable non-volatile memory module 220; the processor 211 may execute a sequence of read instructions to instruct the memory interface control circuit 213 to read data from one or more physical units (also referred to as target physical units) of the rewritable nonvolatile memory module 220 that correspond to the read instructions; the processor 211 may execute an erase command sequence to instruct the memory interface control circuit 213 to perform an erase operation on the rewritable nonvolatile memory module 220. The write command sequence, the read command sequence, and the erase command sequence may each include one or more program codes or command codes and are used to instruct the rewritable nonvolatile memory module 220 to perform corresponding writing, reading, and erasing operations. In one embodiment, the processor 211 may also issue other types of instruction sequences to the memory interface control circuit 213 to perform corresponding operations on the rewritable nonvolatile memory module 220.
In addition, the data to be written into the rewritable nonvolatile memory module 220 is converted into a format acceptable to the rewritable nonvolatile memory module 220 by the memory interface control circuit 213. Specifically, if the processor 211 is to access the rewritable nonvolatile memory module 220, the processor 211 transmits a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform a corresponding operation. For example, the instruction sequences may include a write instruction sequence indicating write data, a read instruction sequence indicating read data, an erase instruction sequence indicating erase data, and corresponding instruction sequences for indicating various memory operations (e.g., changing a plurality of preset read voltage values of a preset read voltage set for a read operation, or performing a garbage collection procedure, etc.). These instruction sequences may include one or more signals, or data, on a bus. Such signals or data may include instruction code or program code. For example, the read instruction sequence may include information such as a read identification code and a memory address.
The rewritable nonvolatile memory module 220 is coupled to the memory controller 210 (memory interface control circuit 213) and is used for storing data written by the host system 10. The rewritable nonvolatile memory module 220 may be a single-level memory cell (SingleLevelCell, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a Multi-level memory cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a three-level memory cell (TripleLevelCell, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a four-level memory cell (QuadrupleLevelCell, QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), a three-dimensional NAND type flash memory module (3 DNAND flashmemorymodule) or a vertical NAND type flash memory module (VerticalNANDflash memorymodule) or other flash memory modules having the same characteristics. The memory cells in the rewritable nonvolatile memory module 220 are arranged in an array.
In this embodiment, the rewritable nonvolatile memory module 220 has a plurality of word lines, wherein each of the plurality of word lines includes a plurality of memory cells. Multiple memory cells on the same word line may constitute one or more physical programming units (physical pages). In addition, a plurality of physical program units can form a physical unit (physical block or physical erase unit).
In this embodiment, one physical page is used as the minimum unit of writing (programming) data. The physical units (physical blocks) are the minimum unit of erase, i.e., each physical unit contains one of the minimum number of erased memory cells. Further, the address of each physical page may also be referred to as a physical address.
It should be noted that, in the present embodiment, the system data for recording the information of a physical block or a block string may be recorded by using one or more memory units in the physical block, or one or more memory units of a specific physical block (also referred to as a system physical block) for recording all the system data in a system area.
Furthermore, it must be understood that when the processor 211 groups memory elements (or physical elements) in the rewritable nonvolatile memory module 220 to perform corresponding management operations, such memory elements (or physical elements) are logically grouped without their actual locations being altered.
The memory controller 210 may configure a plurality of logic units for the rewritable nonvolatile memory module 220. The host system 10 accesses user data stored in a plurality of physical units through a configured logical unit. Here, each logical unit may be composed of one or more logical addresses. For example, the Logical unit may be a Logical block (LogicalBlock), a Logical page (LogicalPage), or a Logical Sector (Logical Sector). A logical unit may be mapped to one or more physical units, where a physical unit may be one or more physical addresses, one or more physical sectors, one or more physical program units, or one or more physical erase units. In this embodiment, the logic unit is a logic block, and the logic subunit is a logic page. Each logic unit has a plurality of logic subunits. In this embodiment, the address of the logical subunit is also referred to as a logical address.
In addition, the memory controller 210 establishes a logical-to-physical address mapping table (LogicalTo Physicaladdressmappingtable) and a physical-to-logical address mapping table (PhysicalToLogical addressmappingtable) to record the mapping relationship between the logical address and the physical address allocated to the rewritable nonvolatile memory module 220. In other words, the storage controller 210 may look up a physical address mapped by a logical address through the logical-to-physical address mapping table, and the storage controller 210 may look up a logical address mapped by a physical address through the physical-to-logical address mapping table. However, the above technical concept related to the mapping relationship between the logical address and the physical address is a conventional technical means for those skilled in the art, and will not be described herein. In general operation of the memory controller, the logical-to-physical address mapping table and the physical-to-logical address mapping table may be maintained in the buffer memory 216.
In the present embodiment, the error checking and correcting circuit 214 is coupled to the processor 211 and is used for performing an error checking and correcting procedure to ensure the correctness of the data. Specifically, when the processor 211 receives a write command from the host system 10, the error checking and correcting circuit 214 generates a corresponding Error Correction Code (ECC) and/or error checking code (error detectingcode, EDC) for the data corresponding to the write command, and the processor 211 writes the data corresponding to the write command and the corresponding ECC and/or error checking code into the rewritable nonvolatile memory module 220. Then, when the processor 211 reads data from the rewritable nonvolatile memory module 220, the error correction code and/or the error check code corresponding to the data are read at the same time, and the error check and correction circuit 214 performs an error check and correction procedure on the read data according to the error correction code and/or the error check code.
In one embodiment, the memory controller 210 further includes a buffer memory 216 and a power management circuit 217. The buffer memory 216 is coupled to the processor 211 and is used for temporarily storing data and instructions from the host system 10, data from the rewritable nonvolatile memory module 220 or other system data for managing the memory device 20, so that the processor 211 can quickly access the data, instructions or system data from the buffer memory 216. The power management circuit 217 is coupled to the processor 211 and is used to control the power of the memory device 20.
In the present embodiment, the garbage collection management circuit unit 215 includes a garbage collection execution circuit 2151 and a collection block string recording circuit 2152. The garbage collection management circuit 215 is configured to receive instructions from the processor 211 to perform writing instructions or reprogramming operations. It should be noted that, in an embodiment, the garbage collection management circuit 215 may also be integrated into the processor 211, so that the processor 211 may implement the data writing method provided in this embodiment. In addition, in another embodiment, the garbage collection management circuit 215 may be implemented as a garbage collection management program code module in firmware or software, accessed and executed by the processor 211 to implement the memory management method according to the present invention
It should be noted that in this embodiment, the garbage collection operation is performed for one block string. Details of the block string will be described below with reference to fig. 3.
FIG. 3 is a schematic diagram of a plurality of block strings of a rewritable nonvolatile memory module according to an embodiment of the present invention. Referring to fig. 3, in the present embodiment, the rewritable nonvolatile memory module 220 may have a plurality of packages (pages), each package may have a plurality of physical blocks, the plurality of physical blocks may be divided into N planes, and part or all of the planes may be logically divided into one logical number (Logical unitnumber, LUN). For simplicity of explanation, it is assumed that the rewritable nonvolatile memory module 220 has one package D1, and the package D1 has a plurality of physical blocks. The plurality of physical blocks are divided (grouped) into 4 planes (planes) P1 to P4 (N is equal to 4), wherein the 4 planes are divided into one logical number LUN1. In addition, each plane has M physical units arranged according to a first order, for example, the plane P1 has M physical blocks P1 (1) to P1 (M); the plane P2 is provided with M physical blocks P2 (1) to P2 (M); the plane P3 has M physical blocks P3 (1) to P3 (M); the plane P4 has M physical blocks P4 (1) to P4 (M). In this embodiment, physical blocks with the same arrangement order in each plane are formed into a block string (BlockStripe). For example, the block string BS (1) includes a physical block P1 (1), a physical block P2 (1), a physical block P3 (1), and a physical block P4 (1). That is, all the physical blocks in the 4 planes may constitute M block strings BS (1) to BS (M) arranged according to the first order.
In the present embodiment, the memory controller 210 sequentially writes data into a plurality of block strings according to the sequence of the block strings, and writes data in the same block string according to the sequence of the planes P1 to P4. Assuming that all the block strings are blank, in order to write a write data capable of filling up 4 physical blocks, the memory controller 210 stores the write data into all the physical blocks (e.g., physical block P1 (1), physical block P2 (1), physical block P3 (1) and physical block P4 (1)) of the first blank block string (in this example, block string BS (1)) according to a first order. For another example, if the physical block P1 (1) of the block string BS (1) is not available for storing the data, and the other physical blocks are all available for storing the write data, the storage controller 210 stores the write data into the physical block P2 (1), the physical blocks P3 (1) and P4 (1) of the block string BS (1) and the physical block P1 (2) of the block string BS (2).
In this embodiment, the garbage collection management circuit unit 215 (or the garbage collection execution circuit 2151) is configured to receive an instruction from the processor 211 to execute a garbage collection operation on one or more block strings. The garbage collection management circuit unit 215 (or the collection block string recording circuit 2152) is configured to record information corresponding to the one or more block strings on which the garbage collection operation is performed. Details of the data writing method according to the embodiments of the present invention, and functions of the memory controller 210 and the garbage collection management circuit unit 215 corresponding to the data writing method will be described in detail below with reference to the drawings.
FIG. 2A is a flow chart of a memory management method according to an embodiment of the invention. Referring to fig. 1 and 2A, in step S211, in response to the garbage collection executing circuit 2151 completing the garbage collection operation, the garbage collection managing circuit unit 215 (or the garbage collection block string recording circuit 2152) identifies one or more garbage collection block strings to be executed with the garbage collection operation.
In particular, the processor 211 may record valid data count values for a plurality of strings of blocks of the rewritable non-volatile memory module 220. When an empty block string is just full of data, the effective data count value of the block string is maximum. When the valid data count value of a block string falls below a valid data threshold (or when the invalid data count of a block string is above a valid data threshold), the processor 211 records a block string index value of the block string in preparation for performing a garbage collection operation on the block string (which may also be referred to as a source block string). At a specific time, the processor 211 may instruct the garbage collection execution circuit 2151 to perform garbage collection operation on the source block string, and copy the remaining valid data in the source block string to an available physical block. After the copying is completed, the garbage collection operation performed on this source block string is also completed. At this time, the remaining valid data of the source block string also becomes invalid data, and the source block string that completes the garbage collection operation may be referred to as a collection block string. That is, the valid data originally stored in the reclaiming block string are all reclaimed, and the currently stored data are all invalid data. That is, after the garbage collection operation for one or more block strings is completed, the one or more block strings become one or more collection block strings, and the processor 211 identifies a block string index value (also referred to as a collection block string index value) of the one or more collection block strings. A block string index value (e.g., BS (1) described above) of a block string may be used by elements of the memory controller 210 to identify the block string and a plurality of physical blocks in the block string. In addition, the block string index value may also be used to indicate the location of the corresponding block string in the rewritable nonvolatile memory module 220.
The processor 211 may reuse the recycling block string. Specifically, the processor 211 may perform an erase operation on the recycling block string at an appropriate timing (e.g., at the leisure of the storage device) so that the physical blocks in the recycling block string become blank physical blocks, and thus may be written with data. In addition, in one embodiment, the processor 211 may also select the recycling block string to perform the write operation first, and perform the erase operation on the recycling block string before writing the data corresponding to the write operation.
Next, in step S212, the garbage collection management circuit unit 215 (or the collection block string recording circuit 2152) updates the garbage collection information table in the buffer memory according to the one or more collection block strings. Specifically, the garbage collection management circuit unit 215 (or the garbage collection block string recording circuit 2152) records the identified garbage collection block string index value to the garbage collection information table, and counts the total number of the garbage collection block string index values recorded in the garbage collection information table. The configuration of the garbage collection information table will be described below with reference to fig. 4.
Fig. 4 is a schematic diagram illustrating a data structure of a garbage collection information table according to an embodiment of the present invention. Referring to fig. 4, in the present embodiment, a garbage collection information table 400 is maintained in the buffer memory 216. The garbage collection information table 400 mainly includes a collection block string list and a collection block string number TRBN. The recovery block string list is used for recording one or more recovery block string index values RBI [1] to RBI [ X ]. X is a positive integer. The number of recovery block strings TRBN is used for recording the total number of all recovery block string index values RBI [1] to RBI [ X ] in the recovery block string list, namely, when the number of recovery block string index values in the recovery block string list is increased or decreased, the number of recovery block strings is correspondingly increased or decreased.
The recycling block string index value newly added to the recycling block string list becomes the last recycling block string index value of the recycling block string list. When a recycling block string index of the recycling block string list is deleted, all recycling block string index arranged behind the deleted recycling block string index are arranged forward. For example, when the RBI index value RBI [1] is deleted, RBI index values RBI [2] to RBI [ X ] following RBI index value RBI [1] are appended forward, i.e., the RBI list is arranged from RBI [2] to RBI [ X ]. It should be noted that, at this time, the number recorded by the number of recovery block strings TRBN is decremented by one. The size of the space occupied by the number of recycling block strings TRBN may be preset, and the size of the space occupied by each recycling block string index value may be preset.
Returning first to fig. 2A, after completing recording the identified one or more recovery block string index values to the recovery block string list in the garbage collection information table, the garbage collection information table is also updated. Next, in step S213, the garbage collection management circuit unit 215 (or the collection block string recording circuit 2152) instructs the memory interface control circuit 213 to write the garbage collection information table into the rewritable nonvolatile memory module 220.
Referring to fig. 4 again, specifically, in the present embodiment, for the convenience of data management, the size of the garbage collection information table written into the rewritable nonvolatile memory module 220 is a predetermined size. The predetermined size is, for example, the size of one physical page, to which the present invention is not limited. In addition, before writing to the rewritable nonvolatile memory module 220, the garbage collection management circuit unit 215 (or the collection block string recording circuit 2152) attaches the data tag DT, the time stamp TS, and the padding data PD to the garbage collection information table.
The data tag DT is attached to the forefront of the garbage collection information table 400, and the data tag DT is used to indicate that the data tag DT and various data located behind the data tag DT are garbage collection information tables having a predetermined size. The size of the space occupied by the data tag DT may be preset.
The time stamp TS (also referred to as a first time stamp) is used to represent the point in time when the garbage collection information table 400 is written into the rewritable non-volatile memory module 220. The invention is not limited to the form of the time stamp. For example, in one embodiment, the time stamp may reflect the current device time of the storage device 20. For another example, in one embodiment, the memory controller 210 records a global time stamp that is used in conjunction with the operation of the memory controller 210 to assign the data requiring the time stamp. When the global time stamp is used/assigned, the count of global time stamps is incremented by one or other appropriate value. In other words, by comparing the time stamps in the two data, the order of the time points at which the two data are processed can be known. The size of the space occupied by the time stamp TS may be preset.
The pad data PD is used to make the size of the garbage collection information table 400 a predetermined size. Specifically, the garbage collection management circuit unit 215 (or the collection block string recording circuit 2152) calculates the data tag DT, the time stamp TS, the total space size commonly occupied by the collection block string number TRBN and the collection block string list in the garbage collection information table 400 after the current update, and subtracts the difference value obtained by subtracting the total space size from the predetermined size as the size of the padding data PD. In this way, after the padding data PD is added to the garbage collection information table 400, the total size of the garbage collection information table 400 can be set to the predetermined size.
Finally, the garbage collection management circuit unit 215 (or the collection block string recording circuit 2152) instructs the memory interface control circuit 213 to write the garbage collection information table 400 including the data tag DT, the time stamp TS, the collection block string number (totalRecycledBlockStripNumber) TRBN, the collection block string list and the fill data PD into the rewritable nonvolatile memory module 200. The above-described writing of the garbage collection information table 400 into the rewritable nonvolatile memory module 200 may also be referred to as performing a snapshot operation on the garbage collection information table 400. In one embodiment, garbage collection information table 400 is written to a system physical block in rewritable nonvolatile memory module 200.
It should be understood that the present invention is not limited to the manner in which the bit values of the pad data PD are set. For example, the pad data PD may be generated using a random function. Or the pad data PD may be generated using the data of the fixed embodiment.
In this embodiment, in addition to updating the garbage collection information table in response to the garbage collection operation performed, it is also possible to determine whether to update the garbage collection information table based on the use of the block string. Another method of updating the garbage collection information table is described below with reference to fig. 2B.
FIG. 2B is a flow chart of a memory management method according to an embodiment of the invention. Referring to fig. 2B, in step S221, the processor 211 uses the target block string. Specifically, when the processor 211 is to perform a write operation or a data merge operation to write a piece of data, the processor 211 selects one or more available block strings (also referred to as target block strings) from among the available block strings (availableblockstrings) in the rewritable nonvolatile memory module 220 to write the piece of data. The target block string selected to write data may also be considered a target block string that is used. The usable block strings include a reclaimed block string (recudbockstrip), a free block string (freeblockstrip), or a blank block string (empty blcokstrip) that has completed the garbage reclamation operation. In this embodiment, the processor 211 records the time stamp (also called a block string time stamp) corresponding to the target block string to the system physical block according to the time point when the target block string is selected for use. Alternatively, in another embodiment, the target block string itself has a Spare area (Spare area) for storing Metadata (Metadata) corresponding to the target block string, and the Metadata may record the block string time stamp of the target block string.
Next, in step S222, the garbage collection management circuit unit 215 (or the garbage collection string recording circuit 2152) compares the target block string index value of the target block string with the plurality of garbage collection string index values recorded in the garbage collection information table. Specifically, the garbage collection management circuit unit 215 (or the collection block string recording circuit 2152) identifies the block string index value (also referred to as the target block string index value) of the target block string to be used, and checks all the collection block string index values in the collection block string list of the garbage collection information table according to the target block string index value to find whether there is a collection block string index value matching/equal to the target block string index value.
Next, in step S223, in response to the target block string index value matching the target recycling block string index value of the plurality of recycling block string index values, the garbage collection management circuit unit 215 (or the recycling block string recording circuit 2152) updates the garbage collection information table according to the target recycling block string index value. Specifically, in response to a recycling block string index value (also referred to as a target recycling block index value) among the recycling block string index values matching the target block string index value, the garbage collection management circuit unit 215 (or the recycling block string recording circuit 2152) deletes (removes) the recycling block string index value from the recycling block string list of the garbage collection information table. In addition, the recovery management circuit unit 215 (or the recovery block string recording circuit 2152) updates the recovery block string number TRBN correspondingly (e.g., in the case where the number of the deleted recovery block string index values is one, the value recorded by the recovery block string number TRBN is subtracted by one). Thus, the garbage collection information table updating operation performed by the use of the target block string is completed. It should be noted that after the update operation of this embodiment is completed, no snapshot operation is performed on the garbage collection information table currently maintained in the buffer memory 216.
Since in this case the updated garbage collection information table is stored only in the buffer memory 216. Thus, if the storage device suddenly fails (also known as a sudden power down event), the garbage collection information table and other data stored in the buffer memory 216 are lost. Accordingly, garbage collection management circuit unit 215 may perform a recovery operation in response to the sudden power-down event to attempt to recover the garbage collection information table in buffer memory 216 prior to the sudden power-down.
Fig. 5 is a flowchart illustrating a recovery operation according to an embodiment of the present invention. Referring to fig. 5, in step S51, the recycling management circuit unit 215 (or the recycling block string recording circuit 2152) reads the latest garbage collection information table from the rewritable nonvolatile memory module 220. Specifically, assuming that the system physical block of the rewritable nonvolatile memory module 220 has already stored a plurality of garbage collection information tables, the garbage collection management circuit unit 215 (or the garbage collection block string recording circuit 2152) may identify the latest garbage collection information table from the plurality of garbage collection information tables according to the positions of the plurality of garbage collection information tables (for example, the physical address is the latest garbage collection information table in the last garbage collection information table). Then, the reclamation management circuit unit 215 (or the reclamation block string recording circuit 2152) reads the latest garbage collection information table from the rewritable nonvolatile memory module 220 into the buffer memory 216. In an embodiment, the reclamation management circuit unit 215 (or the reclamation block string recording circuit 2152) may identify the latest garbage collection information table according to the time stamps of the plurality of garbage collection information tables.
Next, in step S52, the reclamation management circuit unit 215 (or the reclamation block string recording circuit 2152) identifies the information table time stamp of the read garbage collection information table from the garbage collection information table. That is, the reclamation management circuit unit 215 (or the reclamation block string recording circuit 2152) reads the first time stamp (i.e., the information table time stamp) from the latest garbage reclamation information table.
Next, in step S53, the reclamation management circuit unit 215 (or the reclamation block string recording circuit 2152) identifies a plurality of reclamation block strings from the garbage reclamation information table. Specifically, the recycling management circuit unit 215 (or the recycling block string recording circuit 2152) reads all recycling block string index values from the recycling block list in the latest garbage recycling information table to identify corresponding recycling block strings.
Next, in step S54, the reclamation management circuit unit 215 (or the reclamation block string recording circuit 2152) identifies a plurality of block string time stamps corresponding to the plurality of reclamation block strings. For example, the recycling management circuit unit 215 (or recycling block string recording circuit 2152) reads a plurality of block string time stamps corresponding to a plurality of recycling block strings from the system physical block according to the read recycling block string index value or the identified plurality of recycling block strings.
Next, in step S55, the reclamation management circuit unit 215 (or reclamation block string recording circuit 2152) may compare the information table time stamp with the identified plurality of block string time stamps.
In response to the identified first recycling bin string of the plurality of recycling bin strings having a first bin string time stamp less than the information table time stamp, continuing to step S56, the recycling management circuit unit 215 (or recycling bin string recording circuit 2152) retains a first recycling bin string index value of the first recycling bin string in the garbage recycling information table. That is, the recycling management circuit unit 215 (or the recycling block string recording circuit 2152) does not delete the first recycling block string index value recorded in the recycling block string list in the garbage collection information table, wherein the block string time stamp of the first recycling block string corresponding to the first recycling block string index value is smaller than the information table time stamp.
On the other hand, in response to the identified second one of the plurality of recycling block strings having a second block string time stamp greater than the information table time stamp, continuing to step S57, the recycling management circuit unit 215 (or recycling block string recording circuit 2152) removes the second recycling block string index value of the second recycling block string from the garbage recycling information table. That is, the recycling management circuit unit 215 (or the recycling block string recording circuit 2152) deletes the second recycling block string index value recorded in the recycling block string list in the garbage collection information table, wherein the block string time stamp of the second recycling block string corresponding to the second recycling block string index value is greater than the information table time stamp.
In addition, in response to the identified third one of the plurality of recycling block strings being a NULL value (NULL), the recycling management circuit unit 215 (or recycling block string recording circuit 2152) removes the third recycling block string index value of the third recycling block string from the garbage recycling information table, continuing to step S58. That is, the recycling management circuit unit 215 (or the recycling block string recording circuit 2152) deletes the third recycling block string index value recorded in the recycling block string list in the garbage collection information table, wherein the block string time stamp of the third recycling block string corresponding to the third recycling block string index value is not present or is NULL (NULL).
In this embodiment, in the case that the block string time stamp of the third recovery block string corresponding to the third recovery block string index value does not exist or is NULL (NULL), the recovery management circuit unit 215 (or the recovery block string recording circuit 2152) may determine that the third recovery block string has been subjected to the erase operation, thereby causing the block string time stamp of the third recovery block string to be deleted. Next, in an embodiment, step S58 is followed by step S59, where the recycling management circuit unit 215 (or the recycling block string recording circuit 2152) may notify the processor 211 to add the third recycling block string index value to the free block string list. The free block string list is maintained in the buffer memory 216, and the erase operation is completed for a plurality of block strings corresponding to the plurality of block string index values recorded in the free block string list.
After all the block string time stamps are compared with the information table time stamp and the subsequent operations (e.g., steps S56, S57, S58) corresponding to the comparison result are also completed, the recovery management circuit unit 215 (or the recovery block string recording circuit 2152) completes the recovery operation.
It should be noted that, in the above embodiment, since the garbage collection operation is performed for one or more collection block strings, the garbage collection information table records information corresponding to the one or more collection block strings. However, the present invention is not limited thereto, and for example, in another embodiment, the garbage collection operation is performed for one or more physical blocks, so that the garbage collection information table records information corresponding to the one or more physical blocks.
In summary, according to the memory management method and the memory controller provided by the embodiments of the present invention, only when the garbage collection operation is completed, the collected physical block in which the garbage collection operation is performed is recorded in the garbage collection information table, and the garbage collection information table is written in the rewritable nonvolatile memory module. In addition, the memory management method and the memory controller can only update the garbage collection information table maintained in the buffer memory and not write the garbage collection information table into the rewritable nonvolatile memory module according to whether a plurality of recovery physical blocks recorded in the garbage collection information table are used, thereby reducing delay in storing information corresponding to garbage collection operations. In addition, the memory management method may also perform a restore operation to restore the garbage collection information table when a power-off event occurs. Thus, the working efficiency of the memory device can be improved.
Although the invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather may be modified or altered somewhat by persons skilled in the art without departing from the spirit and scope of the invention.
Claims (8)
1. A memory management method adapted to a storage device configured with a rewritable nonvolatile memory module having a plurality of physical blocks and the plurality of physical blocks are grouped into a plurality of block strings, wherein the plurality of physical blocks are divided into a plurality of planes in each of which physical blocks in the same arrangement order are composed into one block string, the method comprising:
identifying one or more recycling block strings of the plurality of block strings on which the garbage recycling operation is performed in response to completing the garbage recycling operation;
updating a garbage collection information table in a buffer memory according to the one or more collection block strings; and
writing the garbage collection information table into the rewritable nonvolatile memory module,
wherein the garbage collection information table written into the rewritable nonvolatile memory module includes:
A data tag, wherein the data tag is at the forefront of the garbage collection information table, and the data tag is used for indicating that the data tag and various data positioned behind the data tag are the garbage collection information table with a preset size,
wherein the plurality of data after the data tag are sequentially a first time stamp, a number of recycling block strings, a list of recycling block strings, and padding data,
wherein the first timestamp is used to represent a point in time when the garbage collection information table was written into the rewritable non-volatile memory module,
wherein the number of recovery block strings is used for recording the total number of index values of all recovery block strings in the recovery block string list,
wherein the recovery block serial table is used for recording a plurality of recovery block serial index values,
wherein the padding data is used to make the size of the garbage collection information table the predetermined size.
2. The memory management method of claim 1, further comprising:
using the target block string;
comparing the target block string index value of the target block string with a plurality of recovery block string index values recorded in the garbage recovery information table; and
And updating the garbage collection information table according to the target recycling block string index value in response to the target block string index value conforming to the target recycling block string index value in the recycling block string index values.
3. The memory management method of claim 1, wherein updating the garbage collection information table in the buffer memory according to the one or more reclamation block strings comprises:
adding the recycling block string index value of the one or more recycling block strings to a recycling block string list in the garbage recycling information table; and
and updating the number of recovery block strings in the garbage collection information table according to the total number of the one or more recovery block strings, wherein the number of recovery block strings is used for recording the total number of all recovery block string index values in the recovery block string list.
4. The memory management method of claim 1, further comprising:
performing a recovery operation corresponding to the garbage collection information table,
wherein the recovery operation comprises:
reading the latest garbage collection information table from the rewritable nonvolatile memory;
identifying an information table time stamp of the read garbage collection information table according to the garbage collection information table;
Identifying a plurality of recycling block strings according to the read garbage recycling information table; and
a plurality of block string time stamps corresponding to the plurality of recovery block strings are identified,
wherein a first recovery block string index value of a first recovery block string in the garbage collection information table is retained in response to the identified first block string time stamp of the first recovery block string being less than the information table time stamp,
wherein a second recovery block string index value of a second recovery block string of the plurality of recovery block strings is removed from the garbage collection information table in response to the identified second block string time stamp of the second recovery block string being greater than the information table time stamp,
wherein a third recovery block string index value for a third recovery block string of the plurality of recovery block strings is removed from the garbage collection information table in response to the identified third block string time stamp for the third recovery block string being a null value.
5. A memory controller for controlling a memory device configured with a rewritable non-volatile memory module, the memory controller comprising:
the connection interface circuit is used for being coupled to the host system;
A memory interface control circuit coupled to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of physical blocks, and the plurality of physical blocks are grouped into a plurality of block strings, wherein the plurality of physical blocks are divided into a plurality of planes, and physical blocks with the same arrangement order in each plane are formed into a block string;
a garbage collection management circuit unit; and
a processor coupled to the connection interface circuit, the memory interface control circuit, and the garbage collection management circuit unit,
wherein the garbage collection management circuit unit is configured to identify one or more recycling block strings of the plurality of block strings on which the garbage collection operation is performed in response to completion of the garbage collection operation,
wherein the garbage collection management circuit unit is further configured to update the garbage collection information table in the buffer memory according to the one or more recycling block strings,
wherein the processor is configured to instruct the memory interface control circuit to write the garbage collection information table into the rewritable non-volatile memory module,
wherein the garbage collection information table written into the rewritable nonvolatile memory module includes:
A data tag, wherein the data tag is at the forefront of the garbage collection information table, and the data tag is used for indicating that the data tag and various data positioned behind the data tag are the garbage collection information table with a preset size,
wherein the plurality of data are sequentially a first time stamp, a number of recycling block strings, a list of recycling block strings, and padding data,
wherein the first timestamp is used to represent a point in time when the garbage collection information table was written into the rewritable non-volatile memory module,
wherein the number of recovery block strings is used for recording the total number of index values of all recovery block strings in the recovery block string list,
wherein the recovery block serial table is used for recording a plurality of recovery block serial index values,
wherein the padding data is used to make the size of the garbage collection information table the predetermined size.
6. The memory controller of claim 5, wherein
The processor uses the target block string,
wherein the garbage collection management circuit unit compares a target block string index value of the target block string with a plurality of collection block string index values recorded in the garbage collection information table,
And the garbage collection management circuit unit updates the garbage collection information table according to the target recycling block string index value in response to the target block string index value conforming to the target recycling block string index value in the plurality of recycling block string index values.
7. The memory controller of claim 5, wherein in operation of the garbage collection management circuit unit further updating the garbage collection information table in the buffer memory according to the one or more collection block strings,
the garbage collection management circuit unit adds the recycling block string index value of the one or more recycling block strings to a recycling block string list in the garbage collection information table,
the garbage collection management circuit unit updates the number of the recovery block strings in the garbage collection information table according to the total number of the one or more recovery block strings, wherein the number of the recovery block strings is used for recording the total number of index values of all recovery block strings in the recovery block string list.
8. The memory controller of claim 5, wherein
The processor further instructs the garbage collection management circuit unit to perform a recovery operation corresponding to the garbage collection information table,
Wherein the recovery operation comprises:
the garbage collection management circuit unit reads the latest garbage collection information table from the rewritable nonvolatile memory;
the garbage collection management circuit unit identifies the information table time stamp of the read garbage collection information table according to the garbage collection information table;
the garbage collection management circuit unit identifies a plurality of collection block strings according to the read garbage collection information table; and
the garbage collection management circuit unit identifies a plurality of block string time stamps corresponding to the plurality of collection block strings,
wherein the garbage collection management circuit unit retains a first recycling block string index value of a first recycling block string in the garbage collection information table in response to the identified first block string time stamp of the first recycling block string being smaller than the information table time stamp,
wherein in response to the identified second one of the plurality of recycling block strings having a second block string time stamp greater than the information table time stamp, the garbage collection management circuit unit removes a second recycling block string index value of the second recycling block string from the garbage collection information table,
Wherein the garbage collection management circuit unit removes a third recycling block string index value of a third recycling block string from the garbage collection information table in response to the identified third block string time stamp of the third recycling block string being a null value.
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