CN110819950A - Preparation method of zinc sulfide thin film and thin film transistor with zinc sulfide thin film - Google Patents
Preparation method of zinc sulfide thin film and thin film transistor with zinc sulfide thin film Download PDFInfo
- Publication number
- CN110819950A CN110819950A CN201910980974.3A CN201910980974A CN110819950A CN 110819950 A CN110819950 A CN 110819950A CN 201910980974 A CN201910980974 A CN 201910980974A CN 110819950 A CN110819950 A CN 110819950A
- Authority
- CN
- China
- Prior art keywords
- thin film
- zinc sulfide
- sputtering
- gas source
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 134
- 229910052984 zinc sulfide Inorganic materials 0.000 title claims abstract description 91
- 239000005083 Zinc sulfide Substances 0.000 title claims abstract description 90
- DRDVZXDWVBGGMH-UHFFFAOYSA-N zinc;sulfide Chemical compound [S-2].[Zn+2] DRDVZXDWVBGGMH-UHFFFAOYSA-N 0.000 title claims abstract description 90
- 238000002360 preparation method Methods 0.000 title claims abstract description 18
- 238000004544 sputter deposition Methods 0.000 claims abstract description 52
- 239000010408 film Substances 0.000 claims abstract description 23
- 238000005477 sputtering target Methods 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims description 18
- 238000002161 passivation Methods 0.000 claims description 13
- 238000000059 patterning Methods 0.000 claims description 8
- 238000005086 pumping Methods 0.000 claims description 4
- 229920001621 AMOLED Polymers 0.000 abstract description 4
- 229910052751 metal Inorganic materials 0.000 description 17
- 239000002184 metal Substances 0.000 description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- 239000000758 substrate Substances 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000000151 deposition Methods 0.000 description 7
- 238000012545 processing Methods 0.000 description 7
- 235000012239 silicon dioxide Nutrition 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 238000000137 annealing Methods 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 238000012546 transfer Methods 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Images
Classifications
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/34—Sputtering
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/0623—Sulfides, selenides or tellurides
- C23C14/0629—Sulfides, selenides or tellurides of zinc, cadmium or mercury
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02551—Group 12/16 materials
- H01L21/02557—Sulfides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78681—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Mechanical Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
Abstract
A preparation method of a zinc sulfide thin film and a thin film transistor with the zinc sulfide thin film are provided, wherein the preparation method of the zinc sulfide thin film comprises the following steps: placing a sputtering target object in a tray in a sputtering cavity, placing zinc sulfide as the sputtering target object on an RF power supply in the sputtering cavity, wherein two gas source pipelines of the sputtering cavity are respectively connected with an Ar gas source and an H gas source2S, an air outlet pipe of the sputtering cavity is connected with a vacuum pump; under the condition that the Ar gas source and the H2S gas source are closed, the vacuum pump is used for ensuring that the cavity vacuum of the sputtering cavity is less than 1x10‑8And (5) Torr. The zinc sulfide film prepared by the preparation method has good transparency and stability, and different atmospheres are controlledAnnealing can realize the conductivity of different films, and the thin film transistor based on the zinc sulfide film can show good device performance and has the mobility of more than 1cm2V.s and a switching ratio of more than 104The prepared zinc sulfide thin film transistor can be used in pixel circuits such as AMLCD, AMOLED, Micro-LED and the like, and has low cost and good stability.
Description
Technical Field
The invention relates to the technical field of manufacturing of thin film transistors, in particular to a preparation method of a zinc sulfide thin film and a thin film transistor with the zinc sulfide thin film.
Background
Thin Film Transistors (TFTs) are key elements of displays, and most recent display technologies, such as Liquid Crystal Displays (LCDs) and Organic Light Emitting Diodes (OLEDs), almost adopt an active matrix driving method, which can achieve full color and high resolution, and greatly reduce crosstalk, while TFTs are essential elements of active matrix driving displays.
In the conventional active matrix driving display, an amorphous silicon (a-Si) TFT is used because of its advantages of low processing temperature, good uniformity, low manufacturing cost, etc. However, the field effect mobility of the a-Si TFT is low, limiting the display performance. In addition, polysilicon (poly-Si) is a high mobility TFT material developed in recent years, and the polysilicon TFT can increase the aperture ratio of a pixel, thereby improving the utilization rate of light and reducing power consumption. However, polysilicon TFT devices have poor uniformity and are difficult to use for large area displays. In addition, the manufacturing cost also becomes higher.
In recent years, metal oxide TFTs have been widely used, particularly Indium Gallium Zinc Oxide (IGZO) TFTs. The metal oxide film can be prepared at room temperature, is transparent under visible light, and has moderate preparation temperature compared with a-Si TFT and polysilicon TFT. However, metal oxide TFTs are rather unstable, very sensitive to moisture and light, and it is very difficult to obtain both n-type and p-type devices using the same material as the channel, and the price of indium metal rises every year, which limits their large scale application in the display field.
Disclosure of Invention
The invention provides a preparation method of a zinc sulfide thin film and a thin film transistor with the zinc sulfide thin film, aiming at solving the problems in the prior art.
In order to achieve the above object, the present invention provides a method for preparing a zinc sulfide thin film, comprising the steps of:
placing a sputtering target object in a tray in a sputtering cavity, placing zinc sulfide as the sputtering target object on an RF power supply in the sputtering cavity, wherein two gas source pipelines of the sputtering cavity are respectively connected with an Ar gas source and an H gas source2S, an air outlet pipe of the sputtering cavity is connected with a vacuum pump;
under the condition that the Ar gas source and the H2S gas source are closed, the vacuum pump is used for ensuring that the cavity vacuum of the sputtering cavity is less than 1x10- 8Torr；
Under the condition that the Ar gas source main valve is closed, opening a gas source pipeline of an Ar gas source, introducing Ar gas within a first preset time, then closing the gas source pipeline of the Ar gas source, and continuing to perform vacuum pumping treatment through a vacuum pump to ensure that the cavity vacuum of the sputtering cavity is less than 1x10-8Torr；
At H2When the S gas source main valve is closed, H is opened2The gas source pipeline of the S gas source is filled with H within a second preset time2S gas, then H is turned off2The gas source pipeline of the S gas source continues to be vacuumized by the vacuum pump, so that the cavity vacuum of the sputtering cavity is less than 1x10-8Torr；
And switching on the RF power supply to sputter zinc sulfide on a sputtering target object in a vacuum environment and form a zinc sulfide thin film.
As a further preferable technical scheme of the present invention, a baffle is further disposed in the sputtering chamber for sputtering the zinc sulfide, the baffle is used for preventing the zinc sulfide thin film in an initial state from sputtering onto the target substrate, and the thickness generated by sputtering the zinc sulfide thin film is 60 nm.
As a further preferable technical solution of the present invention, the first preset time and the second preset time are both at least one minute.
In a further preferred embodiment of the present invention, the power of the RF power source is 120W during sputtering.
According to another aspect of the present invention, the present invention further provides a thin film transistor having a zinc sulfide thin film, wherein the zinc sulfide thin film generated by any one of the above methods is disposed in the thin film transistor, so that the zinc sulfide thin film is used as an active layer of the thin film transistor.
In a further preferred embodiment of the present invention, the active layer is formed by patterning the zinc sulfide thin film after the zinc sulfide thin film is formed.
As a further preferable technical solution of the present invention, the thin film transistor has two structures of a bottom gate type and a top gate type;
when the thin film transistor is of a bottom gate type, the zinc sulfide thin film is generated by sputtering by taking a gate oxide layer of the thin film transistor as a sputtering target, an active layer formed by the zinc sulfide thin film is positioned between the gate oxide layer and a passivation layer of the thin film transistor, and a source contact electrode and a drain contact electrode of the thin film transistor are respectively connected to the active layer;
when the thin film transistor is of a top gate type, the zinc sulfide thin film is generated by sputtering by taking a buffer insulating layer of the thin film transistor as a sputtering target, an active layer formed by the zinc sulfide thin film is positioned between gate oxide layers of the buffer insulating layer of the thin film transistor, and a source contact electrode and a drain contact electrode of the thin film transistor are respectively connected to the active layer.
According to the preparation method of the zinc sulfide thin film and the thin film transistor with the zinc sulfide thin film, the preparation of the zinc sulfide thin film can be realized through the preparation process, the zinc sulfide thin film has good transparency and stability, the electric conductivity of different thin films can be realized by controlling different atmosphere annealing, the thin film transistor based on the zinc sulfide thin film can show good device performance, and the mobility is more than 1cm2V.s and a switching ratio of more than 104The prepared zinc sulfide thin film transistor can be used in pixel circuits such as AMLCD, AMOLED, Micro-LED and the like, and has the advantages of low cost, good stability and the like.
Drawings
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
FIG. 1 is a process flow diagram of one example provided by the method of preparing a zinc sulfide thin film of the present invention;
FIG. 2 is a schematic cross-sectional view of a bottom gate type TFT;
FIG. 3 is a graph of the transfer curves for bottom gate TFT at different Vds;
fig. 4 is a graph of the output of a bottom gate type thin film transistor at different Vgs;
FIG. 5 is a schematic cross-sectional view of a top-gate TFT;
FIG. 6 is a graph of the transfer curves for top gate type TFT at different Vds;
fig. 7 is a graph of output curves at different Vgs for a top gate type thin film transistor.
In the figure: 101. the transistor comprises a substrate, a grid electrode, a grid oxide layer, an active layer, a passivation layer, a grid electrode, a grid oxide layer, a grid electrode, a grid oxide layer, a grid oxide;
201. the transistor comprises a substrate 202, a gate electrode 203, an oxide layer 204, an active layer 205, a passivation layer 206, a drain contact electrode 207, a source contact electrode 208, a drain electrode pad209, a gate electrode pad210 and a source electrode pad.
The objects, features and advantages of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The invention will be further described with reference to the accompanying drawings and specific embodiments. In the preferred embodiments, the terms "upper", "lower", "left", "right", "middle" and "a" are used for clarity of description only, and are not used to limit the scope of the invention, and the relative relationship between the terms and the terms is not changed or modified substantially without changing the technical content of the invention.
As shown in fig. 1, a method for preparing a zinc sulfide thin film includes the steps of:
1001, placing a sputtering target in a tray in a sputtering cavity, placing zinc sulfide as a sputtering target on an RF power supply in the sputtering cavity, wherein two gas source pipelines of the sputtering cavity are respectively connected with an Ar gas source and H2S, an air outlet pipe of the sputtering cavity is connected with a vacuum pump;
the step 1001 is a preparation stage, in which the sputtering chamber is a closed space and the flow rate of the Ar gas source is20sccm，H2The flow rate of the S gas source is 1 sccm.
In this step 1003, in order to avoid the residual contaminated gas in the Ar gas path, the contaminated gas in the Ar gas path may be exhausted by vacuum pumping by introducing the Ar gas source.
In this step 1004, H is to be avoided2Residual polluted gas exists in the S gas path, and H is introduced simultaneously2And the S gas source can discharge the polluted gas in the gas circuit by vacuumizing.
In step 1005, the selected power of the RF power source is 120W, and it is required to ensure that the vacuum of the chamber in the closed sputtering chamber is sufficiently low, if the vacuum of the chamber is greater than 1 × 10-8Torr causes ZnO to be doped in the zinc sulfide thin film formed by sputtering.
In specific implementation, a baffle is further arranged in the sputtering cavity in the sputtering of the zinc sulfide, the baffle is used for preventing the zinc sulfide film in an initial state from being sputtered onto a target substrate, and the thickness generated by sputtering the zinc sulfide film is 60 nm.
In specific implementation, the first preset time and the second preset time are both at least one minute, and of course, the time can be reasonably adjusted according to specific situations.
The preparation method of the zinc sulfide film can realize the preparation of the zinc sulfide film through the preparation process, the zinc sulfide film has good transparency and stability, and the electric conductivity of different films can be realized by controlling different atmosphere annealing, so that the zinc sulfide film is better applied to a thin film transistor, and the thin film transistor has stable working characteristics.
The invention also provides a thin film transistor with the zinc sulfide thin film, wherein the zinc sulfide thin film generated by any method is arranged in the thin film transistor, so that the zinc sulfide thin film is used as an active layer of the thin film transistor.
In a specific implementation, the active layer is formed after the zinc sulfide thin film is generated and is subjected to patterning treatment.
In specific implementation, the thin film transistor has two structures of a bottom gate type and a top gate type;
when the thin film transistor is of a bottom gate type, as shown in fig. 2, the thin film transistor of the bottom gate type includes a substrate 101, a gate electrode 102, a gate oxide layer 103, a zinc sulfide thin film, a passivation layer 105, a drain contact electrode, and a source contact electrode, the zinc sulfide thin film is generated by sputtering with the gate oxide layer 103 of the thin film transistor as a sputtering target, an active layer 104 formed of the zinc sulfide thin film is located between the gate oxide layer 103 and the passivation layer 105 of the thin film transistor, and the source contact electrode and the drain contact electrode of the thin film transistor are respectively connected to the active layer 104;
the preparation process of the bottom gate type thin film transistor is as follows:
step S101, growing a buffer insulating layer made of silicon dioxide on the selected substrate 101;
in step S101, the selected substrate 101 is a silicon substrate 101, a glass substrate 101, or a quartz substrate 101; the silicon dioxide generates the buffer insulating layer by direct thermal oxidation, or generates the buffer insulating layer by a method of low pressure chemical vapor deposition (LPCVD method) or a method of Plasma Enhanced Chemical Vapor Deposition (PECVD); the thickness of the buffer insulating layer is 100nm to 1000 nm.
Step S102, depositing a layer of metal film on the buffer insulating layer, carrying out graphical processing on the metal film to form a grid electrode 102 of the thin film transistor, and then growing a layer of grid oxide layer 103 which coats the grid electrode 102 and is used for insulation on the grid electrode 102;
in step S102, the metal film is formed by DC sputtering of a metal material such as Al, Mo, Ti or ITO with a thickness of 100 nm;
in a specific implementation, the patterning process of the metal film comprises the following steps:
firstly, coating a layer of photoresist on the surface of a generated metal film, then transferring a preset grid 102 image on a mask to the photoresist through an exposure machine, and removing the photoresist of an unexposed part through development; then baking the mixture in a furnace at 120 ℃ for 10 minutes; removing the metal film part of the unexposed part by wet etching or dry etching; after the final etch is complete, the remaining photoresist is removed by an O2 plasma.
The gate oxide layer 103 is formed of a material of SiO2, SiNX, or high-k by a plasma enhanced chemical vapor deposition (LPCVD) method and has a thickness of 100 nm.
Step S103, growing a zinc sulfide film on the gate oxide layer 103 through sputtering, and carrying out graphical processing on the zinc sulfide film to form an active layer 104 of the thin film transistor;
step S104, depositing a passivation layer 105 wrapping the active layer 104 immediately after the patterning process of the active layer 104 is finished, and forming a through hole penetrating through the passivation layer 105 to the active layer 104;
in step S104, the passivation layer 105 is produced from SiO2, SiNx, or Al2O3 material by a plasma enhanced chemical vapor deposition method (PECVD) with a thickness of 100 nm; coating a layer of photoresist on the passivation layer 105, transferring the opening pattern to the photoresist by an exposure machine, and developing; then baking the mixture in a furnace at 120 ℃ for 10 minutes; and finally, etching a through hole by dry etching, and removing the residual photoresist by O2 plasma.
Step S105, depositing metals in the through holes, respectively, and performing patterning processing on each deposited metal to form a drain contact electrode 106 and a source contact electrode 107.
The metal deposited in the through hole is produced by sputtering Al, Mo, Ti, Au, Ag or ITO material, and the thickness is 150 nm; coating a layer of photoresist on the deposited metal layer, transferring a preset pattern onto the photoresist through an exposure machine, and then developing; baking for 10 minutes in a furnace at 120 ℃; the contact electrode was etched by dry etching and the remaining photoresist was removed by O2 plasma.
The zinc sulfide thin film has good transparency and stability, different electric conductivities of the thin films can be realized by controlling different atmosphere annealing, the thin film transistor based on the zinc sulfide thin film can show good device performance, the transfer curve diagram of the bottom gate type zinc sulfide thin film transistor is shown in figure 3, the output curve diagram of the bottom gate type zinc sulfide thin film transistor is shown in figure 4, and as can be seen from figures 3 and 4, the device works normally, the mobility is more than 1cm2V.s and a switching ratio of more than 104The prepared zinc sulfide thin film transistor can be used in pixel circuits such as AMLCD, AMOLED, Micro-LED and the like, and has the advantages of low cost, good stability and the like.
When the thin film transistor is of a top gate type, as shown in fig. 5, the thin film transistor of the top gate type includes a substrate 201, a gate electrode 202, a gate oxide layer 203, a ZnS thin film, a passivation layer 205, a drain contact electrode 206, a source contact electrode 207, a drain electrode pad208, a gate electrode pad209, and a source electrode pad210, the zinc sulfide thin film is generated by sputtering with a buffer insulating layer of the thin film transistor as a sputtering target, an active layer 204 formed of a zinc sulfide thin film is located between the buffer insulating layer 203 of the thin film transistor, and the source contact electrode 207 and the drain contact electrode 206 of the thin film transistor are respectively connected to the active layer 204.
The preparation process of the bottom gate type thin film transistor is as follows:
step S201, growing a buffer insulating layer made of silicon dioxide on the selected substrate 201;
step S202, a layer of zinc sulfide thin film is grown on the buffer insulating layer through sputtering, and the zinc sulfide thin film is subjected to patterning treatment to form an active layer 204 of the thin film transistor;
step S203, respectively depositing metal at two ends of the active layer 204, and carrying out graphical processing on the deposited metal to form a contact electrode;
the two contact electrodes are respectively a drain contact electrode 206 and a source contact electrode 207;
step S204, growing a layer of gate oxide layer 203 for insulation on the active layer 204 between the drain contact electrode and the source contact electrode, depositing a layer of metal film on the gate oxide layer 203, and carrying out graphical processing on the metal film to form a gate 202 of the thin film transistor;
step S205, depositing a passivation layer 205 wrapping the periphery of the drain contact electrode 206, the source contact electrode 207, the gate oxide layer 203 and the gate 202, and forming a drain electrode pad208 through hole and a source electrode pad210 through hole which respectively penetrate through the drain contact electrode 206 and the source contact electrode 207, and a gate electrode pad209 through hole which penetrates through the gate 202 on the passivation layer 205;
step S206, depositing metal in the drain electrode pad208 via hole, the source electrode pad210 via hole and the gate electrode pad209 via hole, respectively, and performing patterning processing on each deposited metal to form the drain electrode pad208 and the source electrode pad210, and the gate electrode pad 209.
The zinc sulfide thin film has good transparency and stability, different electric conductivities of the thin films can be realized by controlling different atmosphere annealing, the thin film transistor based ON the zinc sulfide thin film can show good device performance, a transfer curve diagram of a top gate type thin film transistor with the zinc sulfide thin film is shown in figure 6, an output curve diagram of a bottom gate type zinc sulfide thin film transistor is shown in figure 7, as can be seen from figures 6 and 7, the device works normally, the ON/OFF ratio is more than 10000, namely, the mobility is more than 1cm2V.s and a switching ratio of more than 104The prepared zinc sulfide thin film transistor can be used in pixel circuits such as AMLCD, AMOLED, Micro-LED and the like, and has low cost and stabilityGood and the like.
Although specific embodiments of the present invention have been described above, it will be appreciated by those skilled in the art that these are merely examples and that many variations or modifications may be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims.
Claims (7)
1. A preparation method of a zinc sulfide film is characterized by comprising the following steps:
placing a sputtering target object in a tray in a sputtering cavity, placing zinc sulfide as the sputtering target object on an RF power supply in the sputtering cavity, wherein two gas source pipelines of the sputtering cavity are respectively connected with an Ar gas source and an H gas source2S, an air outlet pipe of the sputtering cavity is connected with a vacuum pump;
under the condition that the Ar gas source and the H2S gas source are closed, the vacuum pump is used for ensuring that the cavity vacuum of the sputtering cavity is less than 1x10- 8Torr；
Under the condition that the Ar gas source main valve is closed, opening a gas source pipeline of an Ar gas source, introducing Ar gas within a first preset time, then closing the gas source pipeline of the Ar gas source, and continuing to perform vacuum pumping treatment through a vacuum pump to ensure that the cavity vacuum of the sputtering cavity is less than 1x10-8Torr；
At H2When the S gas source main valve is closed, H is opened2The gas source pipeline of the S gas source is filled with H within a second preset time2S gas, then H is turned off2The gas source pipeline of the S gas source is continuously vacuumized by a vacuum pump to ensure that the cavity vacuum of the sputtering cavity is less than 1x10-8Torr；
And switching on the RF power supply to sputter zinc sulfide on a sputtering target object in a vacuum environment and form a zinc sulfide thin film.
2. The method for preparing the zinc sulfide thin film according to claim 1, wherein a baffle plate is further arranged in the sputtering chamber for sputtering the zinc sulfide, the baffle plate is used for preventing the zinc sulfide from sputtering on other objects except the sputtering target, and the thickness of the zinc sulfide thin film generated by sputtering is 60 nm.
3. The method of claim 2, wherein the first predetermined time and the second predetermined time are both one minute.
4. The method according to claim 3, wherein the power of the RF power source is 120W during sputtering.
5. A thin film transistor having a zinc sulfide thin film, wherein the zinc sulfide thin film formed by the method of any one of claims 1 to 4 is provided in the thin film transistor so as to serve as an active layer of the thin film transistor.
6. The thin film transistor having a zinc sulfide thin film according to claim 5, wherein the active layer is formed by patterning after the zinc sulfide thin film is grown.
7. The thin film transistor having a zinc sulfide thin film according to claim 6, wherein the thin film transistor has both a bottom gate type and a top gate type structure;
when the thin film transistor is of a bottom gate type, the zinc sulfide thin film is generated by sputtering by taking a gate oxide layer of the thin film transistor as a sputtering target, an active layer formed by the zinc sulfide thin film is positioned between the gate oxide layer and a passivation layer of the thin film transistor, and a source contact electrode and a drain contact electrode of the thin film transistor are respectively connected to the active layer;
when the thin film transistor is of a top gate type, the zinc sulfide thin film is generated by sputtering by taking a buffer insulating layer of the thin film transistor as a sputtering target, an active layer formed by the zinc sulfide thin film is positioned between gate oxide layers of the buffer insulating layer of the thin film transistor, and a source contact electrode and a drain contact electrode of the thin film transistor are respectively connected to the active layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910980974.3A CN110819950A (en) | 2019-10-15 | 2019-10-15 | Preparation method of zinc sulfide thin film and thin film transistor with zinc sulfide thin film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910980974.3A CN110819950A (en) | 2019-10-15 | 2019-10-15 | Preparation method of zinc sulfide thin film and thin film transistor with zinc sulfide thin film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110819950A true CN110819950A (en) | 2020-02-21 |
Family
ID=69549453
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910980974.3A Pending CN110819950A (en) | 2019-10-15 | 2019-10-15 | Preparation method of zinc sulfide thin film and thin film transistor with zinc sulfide thin film |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110819950A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113684471A (en) * | 2021-08-02 | 2021-11-23 | 江苏鎏溪光学科技有限公司 | System and method for monitoring reaction atmosphere in chemical vapor deposition process |
-
2019
- 2019-10-15 CN CN201910980974.3A patent/CN110819950A/en active Pending
Non-Patent Citations (1)
| Title |
|---|
| 唐茜等: "磁控溅射法制备纳米级ZnS薄膜及其性能研究", 《四川大学学报》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113684471A (en) * | 2021-08-02 | 2021-11-23 | 江苏鎏溪光学科技有限公司 | System and method for monitoring reaction atmosphere in chemical vapor deposition process |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9608127B2 (en) | Amorphous oxide thin film transistor, method for manufacturing the same, and display panel | |
| TWI575087B (en) | Method of making oxide thin film transistor array, and device incorporating the same | |
| US9768323B2 (en) | Manufacture method of dual gate oxide semiconductor TFT substrate and structure thereof | |
| JP4341062B2 (en) | Thin film transistor and manufacturing method thereof | |
| US8101949B2 (en) | Treatment of gate dielectric for making high performance metal oxide and metal oxynitride thin film transistors | |
| US10707236B2 (en) | Array substrate, manufacturing method therefor and display device | |
| CN106128963B (en) | Thin film transistor (TFT) and preparation method, array substrate and preparation method, display panel | |
| US9799677B2 (en) | Structure of dual gate oxide semiconductor TFT substrate | |
| US9922995B2 (en) | Structure of dual gate oxide semiconductor TFT substrate including TFT having top and bottom gates | |
| CN102646683B (en) | Array substrate and manufacturing method thereof | |
| JP2008108985A (en) | Method of manufacturing semiconductor element | |
| CN102651343A (en) | Manufacturing method of array substrate, array substrate and display device | |
| US10170506B2 (en) | LTPS array substrate and method for producing the same | |
| TWI498970B (en) | Method for making a field effect transistor | |
| WO2017219412A1 (en) | Method for manufacturing top gate thin-film transistor | |
| WO2016086608A1 (en) | Thin-film transistor and preparation method therefor, array substrate and display device | |
| CN103354243A (en) | Thin film transistor, manufacturing method thereof and related device | |
| US10629746B2 (en) | Array substrate and manufacturing method thereof | |
| KR101257927B1 (en) | Thin film transistot and fabrication method of the same | |
| WO2019095408A1 (en) | Array substrate, manufacturing method thereof, and display panel | |
| CN110819950A (en) | Preparation method of zinc sulfide thin film and thin film transistor with zinc sulfide thin film | |
| US11289513B2 (en) | Thin film transistor and method for fabricating the same, array substrate and display device | |
| CN107316897A (en) | The preparation method of display base plate, display device and display base plate | |
| WO2016201610A1 (en) | Metal oxide thin-film transistor and preparation method therefor, and display panel and display device | |
| Yang et al. | Self-aligned gate and source drain contacts in inverted-staggered a-Si: H thin-film transistors fabricated using selective area silicon PECVD |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200221 |