CN110798050B - Duty ratio design method, system, medium and device for eliminating current sampling interference - Google Patents
Duty ratio design method, system, medium and device for eliminating current sampling interference Download PDFInfo
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- CN110798050B CN110798050B CN201911053495.3A CN201911053495A CN110798050B CN 110798050 B CN110798050 B CN 110798050B CN 201911053495 A CN201911053495 A CN 201911053495A CN 110798050 B CN110798050 B CN 110798050B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0009—Devices or circuits for detecting current in a converter
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention provides a duty ratio design method, a system, a medium and equipment for eliminating current sampling interference, wherein the duty ratio design method for eliminating the current sampling interference comprises the following steps: synchronously setting clock signals of a power factor corrector and a frequency converter so that the clock signals used by the power factor corrector and the frequency converter are the same; setting the switching frequency of the power factor corrector to be a fixed multiple of the switching frequency of the frequency converter under the same clock signal; setting the sampling time of the frequency converter according to the parity of the fixed multiple; comparing the magnitude relation between the duty ratio time and the sampling time of the frequency converter, and shifting the phase of the duty ratio of the power factor corrector according to the comparison result; the duty cycle time and the power factor corrector duty cycle are determined according to a switching period of the power factor corrector. The invention provides a control method of PFC duty ratio, which solves the problem of current sampling interference generated in the occasion of using PFC and a frequency converter simultaneously.
Description
Technical Field
The invention belongs to the field of frequency conversion control, relates to a duty ratio design method, and particularly relates to a duty ratio design method, a duty ratio design system, a duty ratio design medium and duty ratio design equipment for eliminating current sampling interference.
Background
Currently, the frequency conversion technology is widely applied to motor control, and an active PFC (power factor Correction) is required to reduce harmonic interference to a power grid on a occasion of being incorporated into the power grid. Current sampling is a key factor related to control performance and reliability in both PFC and converter designs.
Active power correction and frequency conversion techniques are typically based on Pulse Width Modulation (PWM) implementations. Due to the use of switching devices, pulse disturbances occur at both the on and off times. For the boost PFC, current sampling is carried out at the middle moment when the switching tube is switched on or switched off; for a three-phase two-level frequency converter, current sampling is carried out at the middle moment when the lower tube is completely closed. Because the two are independently controlled, the switching time of the PFC can be randomly coincided with the current sampling time of the frequency converter, so that the frequency converter can acquire an error current signal. The output current of the frequency converter is reconstructed by using the fundamental wave instead of oversampling by being limited by chip resources of the frequency converter, so that the output reliability of the system is deteriorated due to sampling error once, the efficiency of the system is reduced, and even shutdown is caused.
In the prior art, one solution is a sampling filtering technique, such as low-pass filtering or kalman filtering, which can partially solve the problem of sampling deviation, but the filtering technique inevitably brings problems of system resource occupation, response delay, and the like; another solution is to use an isolation device to fully isolate the signal, but the hardware cost of the isolation device is high and is limited by the bandwidth of the isolation device, which can degrade the system response.
Therefore, how to provide a duty cycle design method, system, medium and device for eliminating current sampling interference to solve the problem that the prior art cannot eliminate current sampling interference generated when a PFC and a frequency converter are used simultaneously under the conditions of ensuring system response speed and low hardware cost, and the like, is a technical problem to be solved urgently by those skilled in the art.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a duty cycle design method, system, medium and device for eliminating current sampling interference, which are used to solve the problem that the prior art cannot eliminate current sampling interference generated when a PFC and a frequency converter are used simultaneously under the conditions of ensuring system response speed and low hardware cost.
In order to achieve the above and other related objects, an aspect of the present invention provides a duty cycle design method for eliminating current sampling interference, including: synchronously setting clock signals of a power factor corrector and a frequency converter so that the clock signals used by the power factor corrector and the frequency converter are the same; setting the switching frequency of the power factor corrector to be a fixed multiple of the switching frequency of the frequency converter under the same clock signal; setting the sampling time of the frequency converter according to the parity of the fixed multiple; comparing the magnitude relation between the duty ratio time and the sampling time of the frequency converter, and shifting the phase of the duty ratio of the power factor corrector according to the comparison result; the duty cycle time and the power factor corrector duty cycle are determined according to a switching period of the power factor corrector.
In an embodiment of the present invention, the step of synchronizing the clock signals of the pfc and the inverter so that the clock signals used by the pfc and the inverter are the same includes: the method comprises the steps that a single chip is used for simultaneously completing the functions of the power factor corrector and the frequency converter, and a PWM clock unit inside the single chip is configured to be in a synchronous state; or the same external clock signal is respectively used as the clock signals of the power factor corrector and the frequency converter.
In an embodiment of the invention, the step of setting the switching frequency of the pfc to a fixed multiple of the switching frequency of the converter under the same clock signal includes: setting the switching frequency of the power factor corrector to a fixed odd multiple of the switching frequency of the frequency converter; or setting the switching frequency of the power factor corrector to a fixed even multiple of the switching frequency of the frequency converter.
In an embodiment of the present invention, a fixed multiple between the switching frequency of the pfc and the switching frequency of the frequency converter is defined as N, and the duty cycles of N sets of the pfc are used as a phase shifting period, where the duty cycles of each set of the pfc are counted as: the first duty cycle, the second duty cycle, and up to the nth duty cycle.
In an embodiment of the present invention, the step of setting the sampling time of the frequency converter according to the parity of the fixed multiple includes: when N is an odd number, setting the sampling time of the frequency converter at the central position of the duty ratio of the power factor corrector in (N +1)/2 times; and when N is an even number, setting the sampling time of the frequency converter at the end position of the duty ratio of the power factor corrector for N/2 times.
In an embodiment of the present invention, the step of comparing the magnitude relationship between the duty cycle time and the sampling time of the frequency converter, and shifting the phase of the duty cycle of the power factor corrector according to the comparison result includes: when the duty cycle time is less than the sampling time of the frequency converter, the duty cycle of the power factor corrector in the current phase-shifting period is shifted to the next phase-shifting period; the sampling time of the frequency converter is a fixed multiple of the minimum sampling time of the frequency converter; and when the duty cycle time is greater than the difference value obtained by subtracting the sampling time from the switching period of the frequency converter, combining the duty cycle of the power factor corrector in the current phase-shifting period with the duty cycle of the next power factor corrector.
In an embodiment of the present invention, when the sampling time of the frequency converter is set at the center of the duty cycle of the power factor corrector (N +1)/2 times, and the duty cycle time is less than the sampling time of the frequency converter, the duty cycle of the power factor corrector in the current phase shifting period is shifted to the next phase shifting period with respect to the generated current sampling interference; the step of shifting the duty cycle of the power factor corrector in the current phase-shifting period to the next phase-shifting period is to combine the high level of the duty cycle of the power factor corrector in the current phase-shifting period with the high level appearing in the next phase-shifting period for the first time; when the sampling time of the frequency converter is set at the end position of the duty ratio of the power factor corrector for N/2 times, and the duty ratio time is greater than the difference value of the sampling time subtracted from the switching period of the frequency converter, combining the duty ratio of the power factor corrector in the current phase shifting period with the duty ratio of the next power factor corrector aiming at the generated current sampling interference; the step of combining the duty cycle of the power factor corrector in the current phase-shifting period with the duty cycle of the next power factor corrector refers to combining the high level of the duty cycle of the power factor corrector in the current phase-shifting period with the high level of the duty cycle of the next power factor corrector in the same phase-shifting period.
In another aspect, the present invention provides a duty cycle design system for eliminating current sampling interference, where the duty cycle design system for eliminating current sampling interference includes: the clock synchronization module is used for synchronously setting clock signals of the power factor corrector and the frequency converter so as to enable the clock signals used by the power factor corrector and the frequency converter to be the same; the period setting module is used for setting the switching frequency of the power factor corrector to be a fixed multiple of the switching frequency of the frequency converter under the same clock signal; the sampling time setting module is used for setting the sampling time of the frequency converter according to the parity of the fixed multiple; the phase shifting module is used for comparing the magnitude relation between the duty ratio time and the sampling time of the frequency converter and shifting the phase of the duty ratio of the power factor corrector according to the comparison result; the duty cycle time and the power factor corrector duty cycle are determined according to a switching period of the power factor corrector.
Yet another aspect of the present invention provides a medium, on which a computer program is stored, which when executed by a processor implements the duty cycle design method for eliminating current sampling interference.
A final aspect of the invention provides an apparatus comprising: a processor and a memory; the memory is used for storing a computer program, and the processor is used for executing the computer program stored by the memory so as to enable the device to execute the duty cycle design method for eliminating the current sampling interference.
As described above, the duty cycle design method, system, medium and device for eliminating current sampling interference according to the present invention have the following advantages:
the interference source is avoided through clock synchronization, setting of current sampling time and phase shifting of duty ratio, so that the sampling value of current is more accurate, the accuracy and the precision of current control are improved, the torque output of the motor is stable, the rotating speed is stable, and the efficiency, the dynamic performance and the system stability of a motor control system are improved.
Drawings
Fig. 1 is a diagram illustrating an application background architecture of the duty cycle design method for eliminating current sampling interference according to an embodiment of the present invention.
Fig. 2 is a schematic flow chart of a duty cycle design method for eliminating current sampling interference according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of duty cycle phase shift in an embodiment of the method for designing a duty cycle to eliminate current sampling interference according to the present invention.
Fig. 4 is a schematic structural diagram of a duty cycle design method for eliminating current sampling interference according to an embodiment of the present invention.
Description of the element reference numerals
Duty ratio design system for eliminating current sampling interference
41 clock synchronization module
42 period setting module
43 sampling time setting module
44 phase shift module
Duty ratio design method for eliminating current sampling interference from S21-S24
Step (ii) of
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The technical principle of the duty ratio design method, the system, the medium and the equipment for eliminating the current sampling interference is as follows: synchronously setting clock signals of a power factor corrector and a frequency converter so that the clock signals used by the power factor corrector and the frequency converter are the same; setting the switching frequency of the power factor corrector to be a fixed multiple of the switching frequency of the frequency converter under the same clock signal; setting the sampling time of the frequency converter according to the parity of the fixed multiple; comparing the magnitude relation between the duty ratio time and the sampling time of the frequency converter, and shifting the phase of the duty ratio of the power factor corrector according to the comparison result; the duty cycle time and the power factor corrector duty cycle are determined according to a switching period of the power factor corrector.
Example one
The embodiment provides a duty cycle design method for eliminating current sampling interference, which comprises the following steps:
synchronously setting clock signals of a power factor corrector and a frequency converter so that the clock signals used by the power factor corrector and the frequency converter are the same;
setting the switching frequency of the power factor corrector to be a fixed multiple of the switching frequency of the frequency converter under the same clock signal;
setting the sampling time of the frequency converter according to the parity of the fixed multiple;
comparing the magnitude relation between the duty ratio time and the sampling time of the frequency converter, and shifting the phase of the duty ratio of the power factor corrector according to the comparison result; the duty cycle time and the power factor corrector duty cycle are determined according to a switching period of the power factor corrector.
The duty cycle design method for eliminating the current sampling interference provided by the present embodiment will be described in detail with reference to the drawings.
Referring to fig. 1, a background architecture diagram of an embodiment of a duty cycle design method for eliminating current sampling interference according to the present invention is shown. As shown in fig. 1, VIN represents a pulsating 100HZ dc current obtained by full-bridge rectification of an ac current in a strong current portion, and the PFC circuit employs a general BOOST circuit including an inductor L1, a switching tube Q1, a diode D1, and a dc bus capacitor C1. VIN is boosted by BOOST and then transmitted to a DC bus capacitor C1 at the rear stage, and is supplied to the inverter side to output and drive a variable frequency LOAD. Because of the presence of the PFC circuit, the PFC front side current waveform becomes a 100HZ half-sine waveform synchronized with the rectified voltage.
Specifically, during charging, the switching tube Q1 is closed and the input voltage flows through the inductor L1. Diode D1 prevents the capacitor from discharging to ground. Since the input is dc, the current in inductor L1 increases linearly at a rate that is related to the size of inductor L1. As the inductor L1 current increases, some energy is stored in the inductor L1. During the discharging process, the switching tube Q1 is turned off, and the current flowing through the inductor L1 does not immediately become 0 due to the current holding characteristic of the inductor, but slowly becomes 0 from the time of completion of charging. And the original circuit is disconnected, so that the inductor L1 can only discharge through a new circuit, that is, the inductor L1 starts to charge the dc bus capacitor C1, the voltage across the dc bus capacitor C1 rises, and at this time, the voltage is higher than the input voltage, and the boosting is finished.
Referring to fig. 2, a schematic flow chart of a duty cycle design method for eliminating current sampling interference according to an embodiment of the invention is shown. As shown in fig. 2, the method for designing a duty cycle to eliminate current sampling interference specifically includes the following steps:
and S21, synchronizing the clock signals of the power factor corrector and the frequency converter so that the clock signals used by the power factor corrector and the frequency converter are the same.
In the embodiment, a single chip is used for simultaneously completing the functions of the power factor corrector and the frequency converter, and a PWM clock unit inside the single chip is configured to be in a synchronous state; or the same external clock signal is respectively used as the clock signals of the power factor corrector and the frequency converter.
And S22, setting the switching frequency of the power factor corrector to be a fixed multiple of the switching frequency of the frequency converter under the same clock signal.
In this embodiment, the switching frequency of the power factor corrector is set to a fixed odd multiple of the switching frequency of the frequency converter; or setting the switching frequency of the power factor corrector to a fixed even multiple of the switching frequency of the frequency converter.
And S23, setting the sampling time of the frequency converter according to the parity of the fixed multiple.
In this embodiment, a fixed multiple between the switching frequency of the pfc and the switching frequency of the inverter is defined as N, and the duty cycles of N groups of the pfc are used as a phase shifting period, where the duty cycles of each group of the pfc are counted as: the first duty cycle, the second duty cycle, and up to the nth duty cycle.
Specifically, when N is an odd number, setting the sampling time of the frequency converter at the central position of (N +1)/2 times of duty ratio of the power factor corrector; and when N is an even number, setting the sampling time of the frequency converter at the end position of the duty ratio of the power factor corrector for N/2 times. Therefore, the minimum switch and sampling coincidence proportion can be ensured before the duty ratio phase shift adjustment is not carried out. On the basis, the following steps realize the effect of staggering the PFC switching time and the inverter sampling time when the duty ratio is too large or too small through the phase shift of the duty ratio.
S24, comparing the relation between the duty ratio time and the sampling time of the frequency converter, and shifting the phase of the duty ratio of the power factor corrector according to the comparison result; the duty cycle time and the power factor corrector duty cycle are determined according to a switching period of the power factor corrector. The duty cycle time refers to an active level time, for example, when the high level control switching device is turned on to operate, the duty cycle time refers to a high level time.
In this embodiment, when the duty cycle time is less than the sampling time of the frequency converter, the duty cycle of the power factor corrector in the current phase-shifting period is shifted to the next phase-shifting period, and the sampling time of the frequency converter is a fixed multiple of the minimum sampling time of the frequency converter. The specific value of the minimum sampling time of the frequency converter depends on a physical carrier applied in a frequency conversion system, such as an MCU, the minimum sampling time of the frequency converter depends on the ADC conversion frequency inside the MCU, and in practical application, a fixed multiple of the minimum sampling time of the frequency converter is adopted as the sampling time of current according to design requirements.
Specifically, when the sampling time of the frequency converter is set at the center position of the duty ratio of the power factor corrector (N +1)/2 times, and the duty ratio time is less than the sampling time of the frequency converter, aiming at the generated current sampling interference, the duty ratio of the power factor corrector in the current phase shifting period is shifted to the next phase shifting period; the step of shifting the duty cycle of the power factor corrector in the current phase-shifting period to the next phase-shifting period is to combine the high level of the duty cycle of the power factor corrector in the current phase-shifting period with the high level appearing in the next phase-shifting period for the first time.
In practical applications, a single MCU chip is used for clock synchronization. If the clock frequency of the MCU is 60MHZ, a synchronous PWM clock unit is internally configured, the PFC switching frequency is set to be 19.5HZ, the inversion control switching frequency of the frequency converter is 19.5/3 to 6.5KHZ, the fixed multiple N is odd number 3, and the sampling time of the frequency converter is set at the center of the PFC duty ratio of 2 times. In the operation of the circuit of the whole system, N is an odd number, and considering factors such as the minimum sampling time 333.34nS, PCB layout, component parameter difference and the like, the actual sampling period requires 5 times of the minimum sampling time, namely no current sampling interference signal exists in the range of 1.6667 uS. On the basis, when the PFC on duty ratio is equal to 3.25%, the sampling period is the same as the duty ratio time. Thus, below a duty cycle of 3.25%, two consecutive on periods are combined into one, i.e. two consecutive high level signals are combined into one, and moved to the next phase shifting period.
In this embodiment, when the duty cycle time is greater than a difference value obtained by subtracting a sampling time from a switching period of the frequency converter, the duty cycle of the power factor corrector in the current phase shifting period is combined with the duty cycle of the next power factor corrector.
Specifically, when the sampling time of the frequency converter is set at the end position of the duty cycle of the power factor corrector for N/2 times, and the duty cycle time is greater than the difference value obtained by subtracting the sampling time from the switching period of the frequency converter, aiming at the generated current sampling interference, the duty cycle of the power factor corrector in the current phase shifting period is combined with the duty cycle of the next power factor corrector; the step of combining the duty cycle of the power factor corrector in the current phase-shifting period with the duty cycle of the next power factor corrector refers to combining the high level of the duty cycle of the power factor corrector in the current phase-shifting period with the high level of the duty cycle of the next power factor corrector in the same phase-shifting period.
It should be noted that the combination of continuous high-level signals is only one embodiment of the present invention, and when the active level in the circuit is low, the low level is combined in the duty-cycle combination.
Referring to fig. 3, a schematic diagram of a duty cycle phase shift of an embodiment of a method for designing a duty cycle to eliminate current sampling interference is shown. As shown in fig. 3, S1 represents the PFC duty signal, S1' represents the phase-shifted and combined PFC duty signal, S2 represents the switching signal of the frequency converter, and time B is the current sampling time. When S1 is active at the same time as S2, the high time of S2 will generate interference at the transition of S1 level, which is shown as 4, and the interference at 3 is close to the current sampling time shown as B; when two adjacent high levels are combined through phase shifting, and then become continuous high levels between A, C time, the number of level jump of S1' at the high level time of S2 is reduced, and the current sampling interference around the B time is eliminated.
The present embodiment provides a computer storage medium having a computer program stored thereon, where the computer program is executed by a processor to implement the duty cycle design method for eliminating current sampling interference.
Those of ordinary skill in the art will understand that: all or part of the steps for implementing the above method embodiments may be performed by hardware associated with a computer program. The aforementioned computer program may be stored in a computer readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned computer-readable storage media comprise: various computer storage media that can store program codes, such as ROM, RAM, magnetic or optical disks.
The duty ratio design method for eliminating current sampling interference of the embodiment sets sampling time positions through clock synchronization; and comparing the magnitude relation between the duty cycle time and the sampling time of the frequency converter, and eliminating current sampling interference generated when the PFC and the frequency converter are used simultaneously in a mode of shifting the duty cycle of the power factor corrector according to a comparison result.
Example two
The present embodiment provides a duty cycle design system for eliminating current sampling interference, where the duty cycle design system for eliminating current sampling interference includes:
the clock synchronization module is used for synchronously setting clock signals of the power factor corrector and the frequency converter so as to enable the clock signals used by the power factor corrector and the frequency converter to be the same;
the period setting module is used for setting the switching frequency of the power factor corrector to be a fixed multiple of the switching frequency of the frequency converter under the same clock signal;
the sampling time setting module is used for setting the sampling time of the frequency converter according to the parity of the fixed multiple;
the phase shifting module is used for comparing the magnitude relation between the duty ratio time and the sampling time of the frequency converter and shifting the phase of the duty ratio of the power factor corrector according to the comparison result; the duty cycle time and the power factor corrector duty cycle are determined according to a switching period of the power factor corrector.
The duty cycle design system for eliminating current sampling interference provided by the present embodiment will be described in detail with reference to the drawings. It should be noted that the division of the modules of the following system is only a logical division, and the actual implementation may be wholly or partially integrated into one physical entity or may be physically separated. And the modules can be realized in a form that all software is called by the processing element, or in a form that all the modules are realized in a form that all the modules are called by the processing element, or in a form that part of the modules are called by the hardware. For example: the x module may be a separate processing element or may be integrated into a chip of the system described below. The x-module may be stored in the memory of the following system in the form of program code, and may be called by one of the processing elements of the following system to execute the functions of the following x-module. Other modules are implemented similarly. All or part of the modules can be integrated together or can be independently realized. The processing element described herein may be an integrated circuit having signal processing capabilities. In implementation, the steps of the above method or the following modules may be implemented by hardware integrated logic circuits in a processor element or instructions in software.
The following modules may be one or more integrated circuits configured to implement the above methods, for example: one or more Application Specific Integrated Circuits (ASICs), one or more Digital Signal Processors (DSPs), one or more Field Programmable Gate Arrays (FPGAs), and the like. When some of the following modules are implemented in the form of a program code called by a processing element, the processing element may be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling the program code. These modules may be integrated together and implemented in the form of a System-on-a-chip (SOC).
Referring to fig. 4, a schematic structural diagram of a duty cycle design system for eliminating current sampling interference according to an embodiment of the present invention is shown. As shown in fig. 4, the duty cycle design system 4 for eliminating current sampling interference includes: a clock synchronization module 41, a period setting module 42, a sampling time setting module 43, and a phase shifting module 44.
The clock synchronization module 41 is configured to synchronize clock signals of the power factor corrector and the frequency converter, so that the clock signals used by the power factor corrector and the frequency converter are the same.
In this embodiment, the clock synchronization module 41 is specifically configured to simultaneously complete the function of the power factor corrector and the function of the frequency converter by using a single chip, and configure the PWM clock unit inside the single chip to be in a synchronous state; or the same external clock signal is respectively used as the clock signals of the power factor corrector and the frequency converter.
The period setting module 42 is configured to set the switching frequency of the pfc to a fixed multiple of the switching frequency of the frequency converter under the same clock signal.
In this embodiment, the period setting module 42 is specifically configured to set the switching frequency of the power factor corrector to a fixed odd multiple of the switching frequency of the frequency converter; or setting the switching frequency of the power factor corrector to a fixed even multiple of the switching frequency of the frequency converter.
The sampling time setting module 43 is configured to set the sampling time of the frequency converter according to the parity of the fixed multiple.
In this embodiment, the sampling time setting module 43 is specifically configured to set the sampling time of the frequency converter to the center position of (N +1)/2 duty cycles of the pfc when N is an odd number; and when N is an even number, setting the sampling time of the frequency converter at the end position of the duty ratio of the power factor corrector for N/2 times.
The phase shift module 44 is configured to compare a magnitude relationship between duty cycle time and sampling time of the frequency converter, and shift a phase of the duty cycle of the power factor corrector according to a comparison result; the duty cycle time and the power factor corrector duty cycle are determined according to a switching period of the power factor corrector. The duty cycle time refers to an active level time, for example, when the high level control switching device is turned on to operate, the duty cycle time refers to a high level time.
In this embodiment, the phase shift module 44 is specifically configured to shift the duty cycle of the power factor corrector in the current phase shift period to the next phase shift period when the duty cycle time is less than the sampling time of the frequency converter; the sampling time of the frequency converter is a fixed multiple of the minimum sampling time of the frequency converter; and when the duty cycle time is greater than the difference value obtained by subtracting the sampling time from the switching period of the frequency converter, combining the duty cycle of the power factor corrector in the current phase-shifting period with the duty cycle of the next power factor corrector.
The duty ratio design system for eliminating the current sampling interference of the embodiment sets the sampling time position through clock synchronization; and comparing the magnitude relation between the duty cycle time and the sampling time of the frequency converter, and eliminating current sampling interference generated when the PFC and the frequency converter are used simultaneously in a mode of shifting the duty cycle of the power factor corrector according to a comparison result.
EXAMPLE III
The present embodiment provides an apparatus, comprising: a processor, memory, transceiver, communication interface, or/and system bus; the memory is used for storing a computer program, the communication interface is used for communicating with other equipment, and the processor and the transceiver are used for operating the computer program to enable the equipment to execute the steps of the duty cycle design method for eliminating the current sampling interference.
Specifically, the apparatus comprises: a processor, memory, transceiver, communication interface, or/and system bus; the memory is used for storing a computer program, the communication interface is used for communicating with other equipment, and the processor and the transceiver are used for operating the computer program to enable the equipment to execute the steps of the duty cycle design method for eliminating the current sampling interference.
The above-mentioned system bus may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The system bus may be divided into an address bus, a data bus, a control bus, and the like. The communication interface is used for realizing communication between the database access device and other equipment (such as a client, a read-write library and a read-only library). The Memory may include a Random Access Memory (RAM), and may further include a non-volatile Memory (non-volatile Memory), such as at least one disk Memory.
The Processor may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; the device can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic device, or discrete hardware components.
The protection scope of the duty cycle design method for eliminating current sampling interference according to the present invention is not limited to the execution sequence of the steps listed in this embodiment, and all the schemes of increasing, decreasing, and replacing the steps in the prior art according to the principle of the present invention are included in the protection scope of the present invention.
The invention also provides a duty cycle design system for eliminating current sampling interference, which can realize the duty cycle design method for eliminating current sampling interference, but the implementation device of the duty cycle design method for eliminating current sampling interference comprises but is not limited to the structure of the duty cycle design system for eliminating current sampling interference, and all structural modifications and substitutions in the prior art made according to the principle of the invention are included in the protection scope of the invention.
In summary, the duty cycle design method, system, medium and device for eliminating current sampling interference of the present invention avoid the interference source through clock synchronization, setting of current sampling time and phase shift of duty cycle, so that the current sampling value is more accurate, thereby improving the accuracy and precision of current control, stabilizing torque output and rotating speed, and improving the efficiency, dynamic performance and system stability of the motor control system. The invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (6)
1. A duty cycle design method for eliminating current sampling interference is characterized by comprising the following steps:
synchronously setting clock signals of a power factor corrector and a frequency converter so that the clock signals used by the power factor corrector and the frequency converter are the same;
setting the switching frequency of the power factor corrector to a fixed odd multiple of the switching frequency of the frequency converter; or setting the switching frequency of the power factor corrector to a fixed even multiple of the switching frequency of the frequency converter; defining a fixed multiple between the switching frequency of the power factor corrector and the switching frequency of the frequency converter as N, and taking N groups of duty cycles of the power factor corrector as a phase shifting period, wherein the duty cycles of each group of the power factor corrector are respectively counted as: the first duty cycle, the second duty cycle, until the Nth duty cycle;
when N is an odd number, setting the sampling time of the frequency converter at the central position of the duty ratio of the power factor corrector in (N +1)/2 times; when N is an even number, setting the sampling time of the frequency converter at the end position of the duty ratio of the power factor corrector for N/2 times;
comparing the magnitude relation between the duty ratio time and the sampling time of the frequency converter, and shifting the phase of the duty ratio of the power factor corrector according to the comparison result; the duty cycle time and the power factor corrector duty cycle are determined according to the switching period of the power factor corrector; when the duty cycle time is less than the sampling time of the frequency converter, the duty cycle of the power factor corrector in the current phase-shifting period is shifted to the next phase-shifting period; the sampling time of the frequency converter is a fixed multiple of the minimum sampling time of the frequency converter; and when the duty cycle time is greater than the difference value obtained by subtracting the sampling time from the switching period of the frequency converter, combining the duty cycle of the power factor corrector in the current phase-shifting period with the duty cycle of the next power factor corrector.
2. The method for designing duty cycle to eliminate current sampling interference according to claim 1, wherein the step of synchronizing the clock signals of the power factor corrector and the frequency converter so that the clock signals used by the power factor corrector and the frequency converter are the same comprises:
the method comprises the steps that a single chip is used for simultaneously completing the functions of the power factor corrector and the frequency converter, and a PWM clock unit inside the single chip is configured to be in a synchronous state; or
And respectively taking the same external clock signal as the clock signals of the power factor corrector and the frequency converter.
3. The method for designing duty cycle to eliminate current sampling interference according to claim 1,
when the sampling time of the frequency converter is set at the center position of the duty ratio of the power factor corrector (N +1)/2 times, and the duty ratio time is less than the sampling time of the frequency converter, aiming at the generated current sampling interference, the duty ratio of the power factor corrector in the current phase shifting period is shifted to the next phase shifting period; the step of shifting the duty cycle of the power factor corrector in the current phase-shifting period to the next phase-shifting period is to combine the high level of the duty cycle of the power factor corrector in the current phase-shifting period with the high level appearing in the next phase-shifting period for the first time;
when the sampling time of the frequency converter is set at the end position of the duty ratio of the power factor corrector for N/2 times, and the duty ratio time is greater than the difference value of the sampling time subtracted from the switching period of the frequency converter, combining the duty ratio of the power factor corrector in the current phase shifting period with the duty ratio of the next power factor corrector aiming at the generated current sampling interference; the step of combining the duty cycle of the power factor corrector in the current phase-shifting period with the duty cycle of the next power factor corrector refers to combining the high level of the duty cycle of the power factor corrector in the current phase-shifting period with the high level of the duty cycle of the next power factor corrector in the same phase-shifting period.
4. A duty cycle design system for eliminating current sampling interference is characterized by comprising:
the clock synchronization module is used for synchronously setting clock signals of the power factor corrector and the frequency converter so as to enable the clock signals used by the power factor corrector and the frequency converter to be the same;
the period setting module is used for setting the switching frequency of the power factor corrector to be a fixed odd multiple of the switching frequency of the frequency converter; or setting the switching frequency of the power factor corrector to a fixed even multiple of the switching frequency of the frequency converter; defining a fixed multiple between the switching frequency of the power factor corrector and the switching frequency of the frequency converter as N, and taking N groups of duty cycles of the power factor corrector as a phase shifting period, wherein the duty cycles of each group of the power factor corrector are respectively counted as: the first duty cycle, the second duty cycle, until the Nth duty cycle;
the sampling time setting module is used for setting the sampling time of the frequency converter at the center position of the duty ratio of the power factor corrector (N +1)/2 times when N is an odd number; when N is an even number, setting the sampling time of the frequency converter at the end position of the duty ratio of the power factor corrector for N/2 times;
the phase shifting module is used for comparing the magnitude relation between the duty ratio time and the sampling time of the frequency converter and shifting the phase of the duty ratio of the power factor corrector according to the comparison result; the duty cycle time and the power factor corrector duty cycle are determined according to the switching period of the power factor corrector; when the duty cycle time is less than the sampling time of the frequency converter, the duty cycle of the power factor corrector in the current phase-shifting period is shifted to the next phase-shifting period; the sampling time of the frequency converter is a fixed multiple of the minimum sampling time of the frequency converter; and when the duty cycle time is greater than the difference value obtained by subtracting the sampling time from the switching period of the frequency converter, combining the duty cycle of the power factor corrector in the current phase-shifting period with the duty cycle of the next power factor corrector.
5. A medium having stored thereon a computer program, characterized in that the program, when being executed by a processor, implements the method of duty cycle design for canceling current sampling interference according to any one of claims 1 to 3.
6. An apparatus for canceling current sampling interference, comprising: a processor and a memory;
the memory is used for storing a computer program, and the processor is used for executing the computer program stored by the memory to enable the device to execute the duty cycle design method for eliminating the current sampling interference according to any one of claims 1 to 3.
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| CN112019004B (en) * | 2020-07-30 | 2022-01-14 | 科华恒盛股份有限公司 | Switch control method and device for staggered parallel topology structure |
| CN111947713B (en) * | 2020-08-05 | 2022-08-12 | 深圳威迈斯新能源股份有限公司 | Sampling method and system |
| CN114252697B (en) * | 2020-09-23 | 2024-02-13 | 麦克维尔空调制冷(武汉)有限公司 | APF oversampling method, system and storage medium |
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| CN102832913B (en) * | 2012-08-21 | 2015-02-18 | 上海新进半导体制造有限公司 | Method and circuit for eliminating errors and duty ratio detection circuit |
| CN103856034B (en) * | 2012-11-30 | 2016-10-05 | 上海儒竞电子科技有限公司 | The power factor corrector that two-stage phase shift drives |
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