CN110783212A - Chip, preparation method thereof and electronic equipment - Google Patents
Chip, preparation method thereof and electronic equipment Download PDFInfo
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- CN110783212A CN110783212A CN201910922445.8A CN201910922445A CN110783212A CN 110783212 A CN110783212 A CN 110783212A CN 201910922445 A CN201910922445 A CN 201910922445A CN 110783212 A CN110783212 A CN 110783212A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13007—Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
- H01L2224/13018—Shape in side view comprising protrusions or indentations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13023—Disposition the whole bump connector protruding from the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Abstract
The application discloses a chip, a preparation method thereof and electronic equipment, wherein the preparation method of the chip comprises the following steps: providing a chip body, wherein the chip body is provided with a welding surface, and a plurality of welding pads are arranged on the welding surface; arranging a cover film on the welding surface, wherein the cover film is provided with through holes which correspond to the plurality of bonding pads one to one and expose the corresponding bonding pads, and the cover film covers at least part of the bonding pads; and carrying out ball planting operation on the exposed bonding pads. The preparation method provided by the application can improve the reliability of the chip welding process and reduce the thickness of an electronic product.
Description
Technical Field
The present disclosure relates to the field of chip technologies, and in particular, to a chip, a manufacturing method thereof, and an electronic device.
Background
With the improvement of the technology level, people have higher and higher requirements on electronic products, so that the development of the electronic products towards miniaturization and integration is promoted. The development of electronic products can not be separated from chips, and the chips can integrate a large number of circuits together, so that the volume of the electronic products can be effectively reduced. As the chip functions become more and more powerful, the number of pins of the chip also becomes more and more.
The inventor of the present application finds that, for a chip with a large number of pins, the chip is usually mounted in a transfer piece manner, specifically, the chip is placed on the transfer piece, and then the transfer piece is mounted on a circuit board, which increases the thickness of an electronic product although the convenience of mounting the chip is improved, and is not beneficial to the miniaturization development of the electronic product.
Disclosure of Invention
The chip, the manufacturing method thereof and the electronic device are mainly used for solving the technical problem that the reliability of a chip welding process can be improved and the thickness of an electronic product can be reduced.
In order to solve the technical problem, the application adopts a technical scheme that: provided is a method for manufacturing a chip, the method comprising: providing a chip body, wherein the chip body is provided with a welding surface, and a plurality of welding pads are arranged on the welding surface; arranging a cover film on the welding surface, wherein the cover film is provided with through holes which correspond to the bonding pads one to one and expose the bonding pads, and the cover film covers at least part of the bonding pads; and carrying out ball planting operation on the exposed bonding pads.
In order to solve the above technical problem, another technical solution adopted by the present application is: providing a chip, the chip comprising: the chip comprises a chip body, a plurality of bonding pads and a plurality of connecting wires, wherein the chip body is provided with a welding surface; the metal bumps are welded on the pads correspondingly, wherein the contact area between at least part of the metal bumps and the corresponding pads is smaller than the surface area of the corresponding pads.
In order to solve the above technical problem, the present application adopts another technical solution: the electronic equipment comprises a circuit board and the chip welded on the circuit board, wherein the chip is welded on the circuit board through the metal bumps.
The beneficial effect of this application is: according to the preparation method of the chip, the cover film is arranged on the welding face of the chip body, and the cover film covers at least part of the bonding pads, so that the distance between the ball planting faces for planting balls is increased, namely the bonding pads which are originally dense are evacuated, the follow-up direct ball planting on the welding face of the chip body can be facilitated, on one hand, the convenience of ball planting operation can be realized, on the other hand, the chip body can be directly connected with a circuit board through the metal lug arranged on the chip body after the ball planting operation, and finally the thickness of an electronic product is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
FIG. 1 is a schematic flow chart of one embodiment of a method for fabricating a chip according to the present application;
FIG. 2 is a diagram of a manufacturing process corresponding to the manufacturing method of FIG. 1;
FIG. 3 is a schematic structural diagram of an embodiment of a chip according to the present application;
fig. 4 is a schematic structural diagram of an embodiment of an electronic device according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic flow chart of an embodiment of a method for manufacturing a chip according to the present application.
With reference to fig. 2, the preparation method comprises:
s110: a chip body 1100 is provided, the chip body 1100 has a bonding surface 1110, and a plurality of bonding pads 1111 are disposed on the bonding surface 1110.
The chip body 1100 inputs and/or outputs signals through the bonding pads 1111 disposed on the bonding surface 1110, wherein the bonding pads 1111 may have a circular shape (as shown in fig. 2), a diamond shape, a rectangular shape, or other shapes, which is not limited herein.
The chip body 1100 may be obtained by a user from a supplier, and the chip body 1100 is provided with the pad 1111 when the chip body is shipped from a factory.
In the prior art, the chip body 1100 may be electrically connected to the circuit board by means of a mounting socket, specifically, the mounting socket is soldered to the circuit board and has a plurality of pins thereon, and when the chip body 1100 is placed on the mounting socket and the pads 1111 are in one-to-one contact with the pins on the mounting socket, the chip body 1100 is electrically connected to the circuit board.
S120: a cover film 1200 is disposed on the bonding surface 1110, and the cover film 1200 is provided with vias 1210 that correspond to the plurality of pads 1111 one to one and expose the corresponding pads 1111, where the cover film 1200 covers at least a portion of the pads 1111.
One via 1210 on the cover film 1200 corresponds to one pad 1111 on the chip body 1100, while the via 1210 exposes the pad 1111 corresponding thereto, and the cover film 1200 covers at least a part of the pad 1111, specifically, in an application scenario, a part of the pad 1111 is covered by the cover film 1200, another part of the pad 1111 is not covered by the cover film 1200, and in another application scenario, the cover film 1200 covers a part of the entire pad 1111.
The material of the cover film 1200 has a high temperature resistance, so that the cover film 1200 does not fall off during ball mounting, reflow soldering, and cleaning.
In the present embodiment, the cover film 1200 is a polyimide film having high temperature resistance, and the polyimide film may be disposed on the soldering surface 1110 by being attached. Of course, in other embodiments, the cover film 1200 may be a film of another high temperature resistant material, for example, the cover film 1200 may be polyvinylidene chloride, or the like, or the cover film 1200 may be disposed on the welding surface 1110 in another manner, for example, the cover film 1200 may be formed on the welding surface 1110 by coating, sputtering, or the like.
S130: a ball-planting operation is performed on the exposed pad 1111.
The ball-planting operation includes the steps of ball-planting, reflow soldering, cleaning and the like, specifically, the solder balls are fixed on the exposed bonding pads 1111, then the chip body 1100 fixed with the solder balls is subjected to reflow soldering treatment, the solder balls are changed into metal bumps 1300 welded on the bonding pads 1111 on the chip body 1100, and then redundant soldering flux, surface impurities and the like are washed away. Optionally, in other embodiments, before the ball mounting on the exposed pad 1111, a step of pre-cleaning the chip body 1100 is further included to wash away impurities, oxides, and the like on the surface of the chip body 1100, so as to keep the subsequent solder balls from being soldered on the exposed pad 1111.
After the chip 1000 is formed by performing ball-mounting operation on the exposed bonding pads 1111, the chip 1000 may be directly soldered to the circuit board through the metal bumps 1300.
In this embodiment, the cover film 1200 is disposed on the bonding surface 1110 of the chip body 1100, and the cover film 1200 covers at least part of the pads 1111, so that the distance between the ball-planting surfaces for ball planting is increased, which is equivalent to "evacuating" the originally dense pads 1111, which can facilitate the subsequent ball planting directly on the bonding surface 1110 of the chip body 1100, and further, on one hand, the convenience of the ball-planting operation can be realized, and on the other hand, the chip body 1100 can be connected with a circuit board through the metal bumps 1300 disposed thereon after the ball-planting operation, compared with the mounting method in the prior art, the thickness of the electronic product can be reduced in this embodiment.
In this embodiment, the chip 1000 manufactured by the above manufacturing method is a Central Processing Unit (CPU) chip.
In the prior art, the CPU chip is powerful, its output pad is more and intensive, in addition the CPU chip is installed through the mode that adopts the mount pad, and in this embodiment, after getting the CPU chip (being equivalent to chip body 1100) from the supplier, carry out secondary operation to the CPU chip, can increase the interval that is used for welding the face of weld of metal lug 1300, be convenient for follow-up ball planting operation, and after the ball planting operation, can directly pass through metal lug 1300 with the CPU chip after processing and weld on the circuit board, compare prior art, can save the space of mount pad, and then can reduce the thickness of product.
In the case where the chip 1000 is a CPU chip, a capacitor, a resistor, and the like are generally disposed on the bonding surface 1110 of the chip body 1100, and thus an opening (not shown) for exposing the capacitor and the like is disposed on the cover film 1200.
In the present embodiment, before step S120, the method further includes: the cover film 1200 provided with a plurality of vias 1210 is formed in advance.
Specifically, after the cover film 1200 provided with the plurality of via holes 1210 is formed, the cover film 1200 is disposed on the bonding surface 1110 of the chip body 1100, so that compared with a method of disposing a complete film on the chip body 1100 and then forming the via holes 1210, damage to the chip body 1100 in a process of forming the via holes 1210 can be avoided. In other embodiments, a complete film may be formed on the chip body 1100, and then the cover film 1200 having the plurality of vias 1210 may be formed by opening holes in the complete film.
In one application scenario, the plurality of vias 1210 are formed by laser drilling, and in another application scenario, the plurality of vias 1210 are formed by mechanical drilling. Wherein the formation of the via 1210 is not limited herein.
After step S130, the cover film 1200 may be removed, or the cover film 1200 may be remained, which is not limited herein. Wherein the cover film 1200 can be removed by chemical corrosion or the like. It is understood that the finally prepared chip 1000 does not include the cover film 1200 when the cover film 1200 is removed, and the finally prepared chip 1000 includes the cover film 1200 when the cover film 1200 remains.
In this embodiment, as shown in fig. 2, at least a portion of the via 1210 has a size smaller than a size of the pad 1111 corresponding to the via 1210, that is, an area of at least a portion of the via 1210 is smaller than a surface area of the pad 1111 corresponding to the via 1210, so that the cover film 1200 can be ensured to cover at least a portion of the pad 1111, in an application scenario, the plurality of vias 1210 includes a first via and a second via, wherein the size of the first via is greater than or equal to the size of the pad 1111 corresponding to the first via, and the size of the second via is smaller than the size of the pad 1111 corresponding to the second via, so that a portion of the pad 1111 is covered by the cover film 1200, and another portion of the pad 1111 is not covered by the cover film 1200, and at this time, the first via and the second via may be; in another application scenario, the sizes of the vias 1210 are smaller than the size of the corresponding pad 1111, so that the covering film 1200 can cover part of the entire pad 1111.
Of course, in other embodiments, when the size of all the vias 1210 is equal to or larger than the size of the corresponding pad 1111, the cover film 1200 may cover all the pads 1111, so long as the vias 1210 do not completely overlap the corresponding pads 1111.
The shape of the via 1210 may be matched with the shape of the corresponding pad 1111, as shown in fig. 2, both of which are circular, or may not be matched, for example, the pad 1111 is rectangular, and the via 1210 is circular, which is not limited herein.
In summary, the size of the via 1210 can be designed according to a specific application scenario, and is not limited herein.
Referring to fig. 3, fig. 3 is a schematic structural diagram of an embodiment of a chip according to the present application. The chip 2000 includes: chip body 2100, metal bump 2200.
The chip body 2100 has a bonding surface 2110, a plurality of bonding pads 2111 are disposed on the bonding surface 2110, and a plurality of metal bumps 2200 are correspondingly bonded on the bonding pads 2111, wherein a contact area between at least a portion of the metal bumps 2200 and the corresponding bonding pads 2111 is smaller than a surface area of the corresponding bonding pads 2111.
In one application scenario, the contact area between some of the metal bumps 2200 and the corresponding pads 2111 is smaller than the surface area of the corresponding pads 2111, the contact area between another some of the metal bumps 2200 and the corresponding pads 2111 is equal to the surface area of the corresponding pads 2111, and in another application scenario, the contact areas between all of the metal bumps 2200 and the corresponding pads 2111 are smaller than the surface area of the corresponding pads 2111.
The contact area between at least a portion of metal bump 2200 and corresponding pad 2111 is less than the surface area of corresponding pad 2111, meaning: during the formation of the metal bump 2200, at least a portion of the pad 2111 is masked so that the metal bump 2200 can be in contact with only the exposed portion of the pad 2111. At least part of the bonding pads 2110 are shielded, so that the distance between the bonding surfaces for bonding the metal bumps 2200 is increased, and the metal bumps 2200 can be smoothly formed on the bonding pads 2111 during subsequent ball mounting operation, so that the chip 2000 can be directly bonded on a circuit board through the metal bumps 2200.
With continued reference to fig. 4, chip 2000 further includes: the cover film 2300.
The cover film 2300 is disposed on the bonding surface 2110, the cover film 2300 is provided with via holes 2310 corresponding to the bonding pads 2111 one to one and allowing the corresponding metal bumps 2200 to pass through, and the size of the via holes 2310 is smaller than that of the corresponding bonding pads 2111.
Specifically, before the metal bump 2200 is formed on the chip body 2100, the cover film 2300 is provided on the bonding surface 2110 of the chip body 2100 so that the cover film 2300 covers at least a part of the pad 2111, while the cover film 2300 remains after the metal bump 2200 is formed.
By the arrangement of the cover film 2300, the distance between the ball-planting surfaces for planting balls can be increased.
Of course, in other embodiments, the chip 2000 may not include the cover film 2300, and specifically, the cover film 2300 is removed after the metal bump 2200 is formed.
In one application scenario, the cover film 2300 is a polyimide film. The polyimide film has high temperature resistance, and can ensure that the cover film 2300 cannot fall off from the chip body 2100 in the process of ball mounting operation. Of course, in other application scenarios, the material of the cover film 2300 may be other.
In one application scenario, the chip 2000 is a Central Processing Unit (CPU) chip. The CPU chip (corresponding to the chip body 2100 in the present embodiment) obtained from a supplier is subjected to secondary processing to form the CPU chip to which the metal bump 2200 is soldered, so that the CPU chip can be directly soldered to the circuit board through the metal bump 2200, and the thickness of the product can be reduced as compared with the case where the CPU chip is mounted by using a mounting base in the prior art.
The chip 2000 in this embodiment is prepared by the method for preparing the chip in the above embodiment, that is, the chip 2000 has the same or similar structure as the chip 1000 in the above embodiment, and the detailed preparation method can refer to the above embodiment and is not described herein again.
Referring to fig. 4, fig. 4 is a schematic structural diagram of an embodiment of an electronic device according to the present application. The electronic device 3000 includes a wiring board 3100 and a chip 3200.
The chip 3200 has the same structure as the chip in the previous embodiment, and reference may be made to the above embodiment for details, which are not described herein again.
Wherein chip 3200 is welded on circuit board 3100 through metal lug 3210, and in an application scenario, chip 3200 is the CPU chip, through with CPU chip lug weld on circuit board 3100, compares the mode installation CPU chip that adopts the mount pad among the prior art, and this application can reduce electronic equipment 3000's thickness.
In summary, in the chip manufacturing method of the present application, the cover film is disposed on the bonding surface of the chip body, and the cover film covers at least part of the bonding pads, so that the distance between the ball-planting surfaces for planting balls is increased, which is equivalent to evacuating the originally dense bonding pads, and the balls can be conveniently and directly planted on the bonding surface of the chip body in the following process, thereby achieving the convenience of the ball-planting operation, and enabling the chip body to be connected with the circuit board through the metal bumps disposed thereon after the ball-planting operation, and finally reducing the thickness of the electronic product.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. A method for manufacturing a chip, the method comprising:
providing a chip body, wherein the chip body is provided with a welding surface, and a plurality of welding pads are arranged on the welding surface;
arranging a cover film on the welding surface, wherein the cover film is provided with through holes which correspond to the bonding pads one to one and expose the bonding pads, and the cover film covers at least part of the bonding pads;
and carrying out ball planting operation on the exposed bonding pads.
2. The method for producing according to claim 1, characterized by further comprising, before the step of providing a cover film on the welding face:
the cover film provided with a plurality of the via holes is formed in advance.
3. The method according to claim 2, wherein the step of previously forming the cover film provided with the plurality of via holes includes:
and forming a plurality of via holes by adopting a laser hole opening mode.
4. The method of manufacturing according to claim 1, further comprising:
and removing the covering film.
5. The method of claim 1, wherein at least a portion of the via has a size smaller than a size of the pad corresponding thereto.
6. The method according to claim 1, wherein the coverlay film is a polyimide film, and/or the chip is a central processing unit chip.
7. A chip, wherein the chip comprises:
the chip comprises a chip body, a plurality of bonding pads and a plurality of connecting wires, wherein the chip body is provided with a welding surface;
the metal bumps are welded on the pads correspondingly, wherein the contact area between at least part of the metal bumps and the corresponding pads is smaller than the surface area of the corresponding pads.
8. The chip of claim 7, wherein the chip further comprises:
the cover film is arranged on the welding face and is provided with a plurality of through holes which are in one-to-one correspondence with the bonding pads and are used for corresponding to the metal lugs, and the size of each through hole is smaller than that of the corresponding bonding pad.
9. The chip according to claim 8, wherein the coverlay film is a polyimide film, and/or wherein the chip is a central processing unit chip.
10. An electronic device comprising a circuit board and the chip according to any one of claims 7 to 9 soldered on the circuit board, wherein the chip is soldered on the circuit board by the metal bumps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910922445.8A CN110783212A (en) | 2019-09-27 | 2019-09-27 | Chip, preparation method thereof and electronic equipment |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910922445.8A CN110783212A (en) | 2019-09-27 | 2019-09-27 | Chip, preparation method thereof and electronic equipment |
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| CN110783212A true CN110783212A (en) | 2020-02-11 |
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| CN201910922445.8A Pending CN110783212A (en) | 2019-09-27 | 2019-09-27 | Chip, preparation method thereof and electronic equipment |
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| US20020064931A1 (en) * | 2000-07-03 | 2002-05-30 | E. C. Ong | Method and apparatus for applying a protective over-coating to a ball-grid-array (BGA) structure |
| US6987319B1 (en) * | 2002-11-01 | 2006-01-17 | Amkor Technology, Inc. | Wafer-level chip-scale package |
| CN1956178A (en) * | 2005-10-24 | 2007-05-02 | 南茂科技股份有限公司 | Photoelectric chip package structure, manufacturing method and its chip carrier |
| CN101385403A (en) * | 2006-02-09 | 2009-03-11 | 日立化成工业株式会社 | Method for manufacturing multilayer wiring board |
| CN102254876A (en) * | 2010-05-21 | 2011-11-23 | 松下电器产业株式会社 | Semiconductor apparatus and semiconductor apparatus unit |
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