CN110780724A - Method for resetting flash memory device executed by storage controller of host - Google Patents

Abstract

The present invention relates to a method of resetting a flash memory device performed by a memory controller of a host, comprising the steps of: upon receiving a hardware reset command from the processor, driving the memory controller to perform less than a maximum number of normal reset operations; when the normal reset is unsuccessful, the drive memory controller performs a forced reset. Determining whether the forced reset is successful, and replying a message of success/failure of hardware reset to the microprocessor; after receiving the reset command from the host side, the microprocessor determines whether the reset command is a conventional reset command or a forced reset command; when the reset command is a normal reset command, reading first firmware from the storage unit through the access interface, and covering second firmware of the RAM with the first firmware; when the reset command is a forced reset command, the third firmware is acquired from the electronic device outside the flash memory, and the second firmware of the RAM is rewritten with the third firmware.

Description

Method for resetting flash memory device executed by storage controller of host

Technical Field

The invention belongs to the field of flash memories, and particularly relates to a flash memory device and a method for resetting the flash memory device by using the same.

Background

The storage mode of the flash memory is based on a Floating Gate (Floating Gate) technology, and one MOS transistor consists of two overlapped gates: the first is completely surrounded by oxide and the second is connected to the outside. The oxide layer between the outside connected gate and the other gate is equivalent to form an electronic isolation strip, so that the electrons in the gate can be kept for a long time. The process of charging and discharging this isolated portion is called writing (program) and erasing (erase). The potential Vth inside the isolated part is changed due to charging and discharging, which is a typical operating principle of a MOS transistor. When a voltage is applied to a memory cell, we can respectively handle two situations: we identify a "1" when the voltage we apply is higher than Vth, and a "0" otherwise. Flash memory devices typically include NOR flash memory devices and NAND flash memory devices. NOR flash devices are random access, and a host accessing a NOR flash device can provide any address to the device on its address pins and immediately retrieve data stored at that address on the device data pins. While NAND flash memory devices are serial access.

NAND flash memory devices typically read or program several pages of data from memory cells at a time. Sometimes firmware stored in a RAM (random access memory) of a NAND flash memory device for operating an access interface connected to a memory cell may contain an error bit and must be updated with a copy stored in the NAND memory cell through a reset process. However, firmware stored in the NAND memory cell may be damaged, thereby causing deadlock during reset. Therefore, methods for resetting a flash memory device and apparatuses using the same to solve the above-described problems are needed.

Disclosure of Invention

The invention aims to provide a method for resetting a flash memory device to avoid the problem of deadlock caused in the resetting process, and the technical scheme is as follows:

a method of resetting a flash memory device performed by a storage controller of a host, comprising at least the steps of:

(1) upon receiving a hardware reset command from the processor, driving the memory controller to perform less than a maximum number of normal reset operations;

(2) when the normal reset is unsuccessful, the drive memory controller performs a forced reset. And determining whether the forced reset is successful, and replying a message of success/failure of hardware reset to the microprocessor.

(3) After receiving the reset command from the host side, the microprocessor determines whether the reset command is a conventional reset command or a forced reset command;

(4) when the reset command is a normal reset command, reading first firmware from the storage unit through the access interface, and covering second firmware of the RAM with the first firmware;

(5) when the reset command is a forced reset command, the third firmware is acquired from the electronic device outside the flash memory, and the second firmware of the RAM is rewritten with the third firmware.

Drawings

Fig. 1 is a system architecture of an electronic device.

FIG. 2 is a flow chart of a method of conventionally resetting a flash memory device by a memory controller.

FIG. 3 is a flow chart of a method of forcing a reset of a flash memory device by a memory controller.

FIG. 4 is a flow chart of a method of resetting a flash memory device by a microprocessor.

Detailed Description

FIG. 1 is an electronic device system architecture for use with the present invention. Electronic devices may be equipped with digital cameras, mobile phones, consumer electronics devices, and the like. The flash memory device includes a memory controller and a memory unit. System architecture electronics include a host side and a memory controller that communicate with each other through a flash interface. The flash memory interface may be a UFS (universal flash storage) interface, an eMMC (embedded multimedia card) interface, or the like. UFS and eMMC are common flash storage specifications that may lead to higher data transfer speeds and higher reliability for flash storage, and may not require the use of different types of flash memory cells for different adapters. The host side may include an interconnect layer associated with the memory controller. The host side may also contain an access interface to communicate with the processor of other electronic devices through the access interface using standard protocols, such as USB (universal serial bus), ATA (advanced technology attachment), SATA (serial ATA), PCI-E (peripheral component interconnect express), or others.

The microprocessor of the memory controller may communicate with the memory unit via the access interface using a DDR (double data rate) protocol, such as ONFI. The microprocessor may be a general purpose processor or MCU. The microprocessor loads firmware from the memory unit and stores it in the RAM at system boot. When UFS or eMMC commands and data are received from the host, the microprocessor executes the relevant code to write the data to the specified address of the memory cell and reads the data from its specified address through the indicated access interface. The access interface uses a number of electrical signals, including data lines, clock signals, and control lines, to coordinate the transfer of commands and data between the microprocessor and the memory unit. The data lines are used to transmit commands, addresses and data. The control lines are used to issue control signals such as CE (chip enable), ALE (address latch enable), CLE (command latch enable), WE (write enable), and the like.

Since flash memory has been operating for some time, firmware stored in RAM may be corrupted. In some implementations, the processing unit may issue a hardware reset command for updating firmware of the DRAM using firmware of the memory unit. However, if the firmware of the memory location has been corrupted, the hardware reset will cause a deadlock. Deadlock can therefore be avoided with the reset method of the present invention.

1. FIG. 2 is a method performed by a memory controller of a host to conventionally Reset a Normal Reset flash memory device, comprising the steps of:

(1) receiving a hardware reset command from a processor through a host side access interface;

(2) the controller at the host side starts a counter; .

(3) The controller of the host side drives the interconnection layer of the host side to send a normal reset command to the memory controller;

(4) receiving a result of the normal reset from the controller through the interconnect layer;

(5) the memory controller passes through the interconnect layer on the host side and determines whether the normal reset was successful based on the result.

When the conventional reset fails, performing step (6) the controller at the host side increases the counter by 1;

when the normal reset is successful, the go step (7) loop ends and the host side controller replies with a message through the host side access interface indicating that the hardware reset has been successful to the processor.

Step (8) is then performed to determine whether the counter value equals or exceeds the threshold value. When the counter value does not exceed the threshold, the next iteration of the loop is performed. When the counter value equals or exceeds the threshold, the cycle ends and the controller on the host side drives the interconnect layer on the host side to send a force Reset Super Reset command to the memory controller.

2. FIG. 3 is a method performed by a host storage controller to force a reset of a flash memory device, comprising the steps of:

(1) and when the conventional reset fails, starting forced reset. The controller at the host side drives the interconnection layer at the host side to send a forced reset command to the storage controller;

(2) receiving a result of the forced reset from the memory controller through the interconnect layer;

(3) the memory controller determines whether the forced reset is successful according to a result of the normal reset through an interconnection layer of the host side.

And (4) when the forced reset fails, replying a message indicating that the hardware reset has failed to the processor through the host side access interface.

And (5) when the forced reset is successful, replying a message indicating that the hardware reset is successful to the processor through the host side access interface.

The conventional reset command of step (3) of fig. 2 and the forced reset command of step (1) of fig. 3 may be distinguished by different reset type flags of the same UFS or eMMC command. For example, a reset type flag of "O" of the UFS or eMMC command indicates a conventional reset command. A reset type flag of UFS or eMMC command "1" indicates a forced reset command.

3. FIG. 4 is a flow chart of a method performed by a microprocessor of a memory controller for resetting a flash memory device, the process of which is as follows:

(1) receiving a reset command over an interconnect layer;

(2) the microprocessor judges whether the reset command is a conventional reset command or a forced reset command;

(3) when the received UFS or eMMC command is a normal reset command, executing boot code of an area of the ROM to read firmware from the storage unit and write firmware to the RAM;

(4) when the received UFS or eMMC command is a forced reset command, executing an activation code of an area of the ROM, wherein the activation code is used for acquiring firmware from electronic equipment outside the flash memory;

in step (4) of fig. 3, the firmware may be downloaded from a download site connected to the internet or a LAN (local area network), or may be acquired from another memory. The microprocessor also drives the access interface to program the fetched firmware into the memory unit to replace the original firmware.

(5) After rewriting the firmware of the RAM, it is determined whether the rewritten firmware is correct. The firmware may contain a CRC (cyclic redundancy check) code, in which case the microprocessor may use a decoder to check the CRC code of the firmware in the RAM to determine if the firmware is correct.

And (5) when the overlaid firmware is correct, performing step (6) to drive the interconnection layer to reply a message that the reset is successful to the host side. And (5) when the covered firmware is incorrect, performing the step (7) to drive the No path layer to reply a reset failure message to the host side.

Claims (1)

1. A method of resetting a flash memory device performed by a storage controller of a host, comprising at least the steps of:

(1) upon receiving a hardware reset command from the processor, driving the memory controller to perform less than a maximum number of normal reset operations;

(2) when the normal reset is unsuccessful, the drive memory controller performs a forced reset. And determining whether the forced reset is successful, and replying a message of success/failure of hardware reset to the microprocessor.

(3) After receiving the reset command from the host side, the microprocessor determines whether the reset command is a conventional reset command or a forced reset command;

(4) when the reset command is a normal reset command, reading first firmware from the storage unit through the access interface, and covering second firmware of the RAM with the first firmware;

(5) when the reset command is a forced reset command, the third firmware is acquired from the electronic device outside the flash memory, and the second firmware of the RAM is rewritten with the third firmware.

Images