CN110767541A - Wafer bonding method - Google Patents

Wafer bonding method Download PDF

Info

Publication number
CN110767541A
CN110767541A CN201911028550.3A CN201911028550A CN110767541A CN 110767541 A CN110767541 A CN 110767541A CN 201911028550 A CN201911028550 A CN 201911028550A CN 110767541 A CN110767541 A CN 110767541A
Authority
CN
China
Prior art keywords
wafer
bodies
wafer bodies
vacuum environment
room temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201911028550.3A
Other languages
Chinese (zh)
Inventor
闫一方
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Su Normal University Semiconductor Materials and Equipment Research Institute Pizhou Co Ltd
Original Assignee
Su Normal University Semiconductor Materials and Equipment Research Institute Pizhou Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Su Normal University Semiconductor Materials and Equipment Research Institute Pizhou Co Ltd filed Critical Su Normal University Semiconductor Materials and Equipment Research Institute Pizhou Co Ltd
Priority to CN201911028550.3A priority Critical patent/CN110767541A/en
Publication of CN110767541A publication Critical patent/CN110767541A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185Joining of semiconductor bodies for junction formation
    • H01L21/187Joining of semiconductor bodies for junction formation by direct bonding

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

The invention provides a wafer bonding method, and relates to the technical field of semiconductor preparation. The wafer bonding method comprises the following steps: s1, preparing two wafer bodies, firstly immersing the two wafer bodies into a hydrofluoric acid solution to remove a natural oxidation layer on the surfaces of the wafer bodies, then taking out the wafer bodies to carry out drying treatment on the wafer bodies, and then polishing the front surfaces and the back surfaces of the two wafer bodies by using polishing equipment to keep the smoothness of the surfaces of the two wafer bodies; s2, pre-bonding two wafer bodies at room temperature, then transferring the bonded wafer bodies into a vacuum environment, extracting gas in the vacuum environment, adjusting the pressure in the vacuum environment to be within a range of 2x10 (-7) -4x10 (-7) Pa, and then introducing nitrogen into the vacuum environment. By processing the wafer, the wafer can be subjected to bonding reaction at room temperature without traditional high-temperature annealing, so that the wafer bonding efficiency is improved, the wafer bonding cost is reduced, and the thermal expansion and thermal stress between materials and structures are greatly reduced.

Description

Wafer bonding method
Technical Field
The invention relates to the technical field of semiconductor preparation, in particular to a wafer bonding method.
Background
The semiconductor refers to a material with conductivity between a conductor and an insulator at normal temperature, and has wide application in radio, television and temperature measurement, for example, a diode is a device made of semiconductor, and a semiconductor refers to a material with controllable conductivity ranging from an insulator to a conductor, and the importance of the semiconductor is very great from the viewpoint of technology or economic development.
The wafer refers to a silicon wafer used for manufacturing a silicon semiconductor integrated circuit, and is called a wafer because the shape is circular; at present, the wafer bonding condition generally needs to be under a high temperature condition, not only the bonding efficiency is low, but also the wafer bonding cost is increased, and the materials and the structures still have obvious thermal expansion and thermal stress.
Disclosure of Invention
Technical problem to be solved
Aiming at the defects of the prior art, the invention provides a wafer bonding method, which solves the problems that the bonding efficiency is lower, the wafer bonding cost is increased and obvious thermal expansion and thermal stress still exist between materials and structures because the wafer bonding condition generally needs to be at a high temperature at present.
(II) technical scheme
In order to achieve the purpose, the invention is realized by the following technical scheme: a wafer bonding method comprises the following steps:
s1, preparing two wafer bodies, firstly immersing the two wafer bodies into a hydrofluoric acid solution to remove a natural oxidation layer on the surfaces of the wafer bodies, then taking out the wafer bodies to carry out drying treatment on the wafer bodies, and then polishing the front surfaces and the back surfaces of the two wafer bodies by using polishing equipment to keep the smoothness of the surfaces of the two wafer bodies;
s2, pre-bonding two wafer bodies at room temperature, transferring the bonded wafer into a vacuum environment, extracting gas in the vacuum environment, adjusting the pressure in the vacuum environment to be within a range of 2x10 (-7) -4x10 (-7) Pa, introducing nitrogen into the vacuum environment, and separating the bonded two wafer bodies after 1-2 hours;
s3, decomposing the residual oxide film on the surface of the wafer and desorbing hydrogen adsorbed on the surface until the oxide film on the surface of the wafer and the adsorbed hydrogen are completely removed, and then taking the wafer out of the vacuum environment;
s4, stacking the two wafer bodies together, adding a small amount of distilled water between the two wafer bodies, then placing the wafer bodies into a closed environment, adding a small amount of carbon tetrafluoride into the closed environment, treating the surface of the wafer by using fluorine-containing plasma, then taking out the two wafer bodies, laminating the two wafer bodies, and standing at room temperature;
s5, in the process of placing the wafer body at room temperature, the volume of the silicon oxyfluoride layer after absorbing water expands, so that the atomic scale contact area between the wafers is increased, and more Si-O-Si covalent bonds are formed.
Preferably, the concentration of the hydrofluoric acid solution in the step 1 is 2-10%.
Preferably, the rotation speed of the polishing device in the step 1 is 1000-.
Preferably, the volume of the carbon tetrafluoride added in the step 4 is 2-5% of the volume in the closed environment.
Preferably, the two wafer bodies in the step 4 are placed at room temperature for 20-24 hours.
(III) advantageous effects
The invention provides a wafer bonding method. The method has the following beneficial effects:
1. according to the wafer bonding method, the wafer is processed, so that the wafer can be subjected to bonding reaction at room temperature, the traditional high-temperature annealing is not needed, the wafer bonding efficiency is improved, the wafer bonding cost is reduced, and the thermal expansion and the thermal stress between materials and structures are greatly reduced.
2. The wafer bonding method is simple in operation mode, is non-toxic and harmless in the bonding process, and ensures the health of workers.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to a plurality of embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The first embodiment is as follows:
the embodiment of the invention provides a wafer bonding method, which comprises the following steps:
s1, preparing two wafer bodies, firstly immersing the two wafer bodies into a hydrofluoric acid solution to remove a natural oxidation layer on the surfaces of the wafer bodies, then taking out the wafer bodies to carry out drying treatment on the wafer bodies, and then polishing the front surfaces and the back surfaces of the two wafer bodies by using polishing equipment to keep the smoothness of the surfaces of the two wafer bodies;
s2, pre-bonding two wafer bodies at room temperature, transferring the bonded wafer into a vacuum environment, extracting gas in the vacuum environment, adjusting the pressure in the vacuum environment to 2x10 (-7) Pa, introducing nitrogen into the vacuum environment, and separating the bonded two wafer bodies after 1 hour;
s3, decomposing the residual oxide film on the surface of the wafer and desorbing hydrogen adsorbed on the surface until the oxide film on the surface of the wafer and the adsorbed hydrogen are completely removed, and then taking the wafer out of the vacuum environment;
s4, stacking the two wafer bodies together, adding a small amount of distilled water between the two wafer bodies, then placing the wafer bodies into a closed environment, adding a small amount of carbon tetrafluoride into the closed environment, treating the surface of the wafer by using fluorine-containing plasma, then taking out the two wafer bodies, laminating the two wafer bodies, and standing at room temperature;
s5, in the process of placing the wafer body at room temperature, the volume of the silicon oxyfluoride layer after absorbing water expands, so that the atomic scale contact area between the wafers is increased, and more Si-O-Si covalent bonds are formed.
Through processing the wafer, the wafer can carry out bonding reaction at room temperature, traditional high-temperature annealing is not needed, the wafer bonding efficiency is improved, the wafer bonding cost is reduced, thermal expansion and thermal stress between materials and structures are greatly reduced, the operation mode is simple, the bonding process is non-toxic and harmless, and the physical health of workers is guaranteed.
Wherein the concentration of the hydrofluoric acid solution in the step 1 is 2%, the working rotating speed of the polishing equipment in the step 1 is 1000r/min, the polishing time of the wafer body is 1min, the volume of the carbon tetrafluoride added in the step 4 is 2% of the volume in the closed environment, and the time for placing the two wafer bodies at room temperature in the step 4 is 20 hours.
Example two:
the embodiment of the invention provides a wafer bonding method, which comprises the following steps:
s1, preparing two wafer bodies, firstly immersing the two wafer bodies into a hydrofluoric acid solution to remove a natural oxidation layer on the surfaces of the wafer bodies, then taking out the wafer bodies to carry out drying treatment on the wafer bodies, and then polishing the front surfaces and the back surfaces of the two wafer bodies by using polishing equipment to keep the smoothness of the surfaces of the two wafer bodies;
s2, pre-bonding two wafer bodies at room temperature, transferring the bonded wafer into a vacuum environment, extracting gas in the vacuum environment, adjusting the pressure in the vacuum environment to 3x10 (-7) Pa, introducing nitrogen into the vacuum environment, and separating the bonded two wafer bodies after 1.5 hours;
s3, decomposing the residual oxide film on the surface of the wafer and desorbing hydrogen adsorbed on the surface until the oxide film on the surface of the wafer and the adsorbed hydrogen are completely removed, and then taking the wafer out of the vacuum environment;
s4, stacking the two wafer bodies together, adding a small amount of distilled water between the two wafer bodies, then placing the wafer bodies into a closed environment, adding a small amount of carbon tetrafluoride into the closed environment, treating the surface of the wafer by using fluorine-containing plasma, then taking out the two wafer bodies, laminating the two wafer bodies, and standing at room temperature;
s5, in the process of placing the wafer body at room temperature, the volume of the silicon oxyfluoride layer after absorbing water expands, so that the atomic scale contact area between the wafers is increased, and more Si-O-Si covalent bonds are formed.
Wherein the concentration of the hydrofluoric acid solution in the step 1 is 6%, the working rotating speed of the polishing equipment in the step 1 is 1500r/min, the polishing time of the wafer body is 1.5min, the volume of the carbon tetrafluoride added in the step 4 is 3.5% of the volume in the closed environment, and the time for placing the two wafer bodies at room temperature in the step 4 is 22 hours.
Example three:
the embodiment of the invention provides a wafer bonding method, which comprises the following steps:
s1, preparing two wafer bodies, firstly immersing the two wafer bodies into a hydrofluoric acid solution to remove a natural oxidation layer on the surfaces of the wafer bodies, then taking out the wafer bodies to carry out drying treatment on the wafer bodies, and then polishing the front surfaces and the back surfaces of the two wafer bodies by using polishing equipment to keep the smoothness of the surfaces of the two wafer bodies;
s2, pre-bonding two wafer bodies at room temperature, transferring the bonded wafer into a vacuum environment, extracting gas in the vacuum environment, adjusting the pressure in the vacuum environment to 4x10 (-7) Pa, introducing nitrogen into the vacuum environment, and separating the bonded two wafer bodies after 2 hours;
s3, decomposing the residual oxide film on the surface of the wafer and desorbing hydrogen adsorbed on the surface until the oxide film on the surface of the wafer and the adsorbed hydrogen are completely removed, and then taking the wafer out of the vacuum environment;
s4, stacking the two wafer bodies together, adding a small amount of distilled water between the two wafer bodies, then placing the wafer bodies into a closed environment, adding a small amount of carbon tetrafluoride into the closed environment, treating the surface of the wafer by using fluorine-containing plasma, then taking out the two wafer bodies, laminating the two wafer bodies, and standing at room temperature;
s5, in the process of placing the wafer body at room temperature, the volume of the silicon oxyfluoride layer after absorbing water expands, so that the atomic scale contact area between the wafers is increased, and more Si-O-Si covalent bonds are formed.
Wherein the concentration of the hydrofluoric acid solution in the step 1 is 10%, the working rotating speed of the polishing equipment in the step 1 is 2000r/min, the polishing time of the wafer body is 2min, the volume of the carbon tetrafluoride added in the step 4 is equal to the volume in the closed environment, and the time for placing the two wafer bodies at room temperature in the step 4 is 24 hours.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims (5)

1. A wafer bonding method is characterized in that: the method comprises the following steps:
s1, preparing two wafer bodies, firstly immersing the two wafer bodies into a hydrofluoric acid solution to remove a natural oxidation layer on the surfaces of the wafer bodies, then taking out the wafer bodies to carry out drying treatment on the wafer bodies, and then polishing the front surfaces and the back surfaces of the two wafer bodies by using polishing equipment to keep the smoothness of the surfaces of the two wafer bodies;
s2, pre-bonding two wafer bodies at room temperature, transferring the bonded wafer into a vacuum environment, extracting gas in the vacuum environment, adjusting the pressure in the vacuum environment to be within a range of 2x10 (-7) -4x10 (-7) Pa, introducing nitrogen into the vacuum environment, and separating the bonded two wafer bodies after 1-2 hours;
s3, decomposing the residual oxide film on the surface of the wafer and desorbing hydrogen adsorbed on the surface until the oxide film on the surface of the wafer and the adsorbed hydrogen are completely removed, and then taking the wafer out of the vacuum environment;
s4, stacking the two wafer bodies together, adding a small amount of distilled water between the two wafer bodies, then placing the wafer bodies into a closed environment, adding a small amount of carbon tetrafluoride into the closed environment, treating the surface of the wafer by using fluorine-containing plasma, then taking out the two wafer bodies, laminating the two wafer bodies, and standing at room temperature;
s5, in the process of placing the wafer body at room temperature, the volume of the silicon oxyfluoride layer after absorbing water expands, so that the atomic scale contact area between the wafers is increased, and more Si-O-Si covalent bonds are formed.
2. The wafer bonding method of claim 1, wherein: the concentration of the hydrofluoric acid solution in the step 1 is 2-10%.
3. The wafer bonding method of claim 1, wherein: the rotation speed of the polishing device in the step 1 is 1000-2000r/min, and the polishing time of the wafer body is 1-2 min.
4. The wafer bonding method of claim 1, wherein: and the volume of the carbon tetrafluoride added in the step 4 is 2-5% of the volume in the closed environment.
5. The wafer bonding method of claim 1, wherein: and the two wafer bodies in the step 4 are placed at room temperature for 20-24 hours.
CN201911028550.3A 2019-10-28 2019-10-28 Wafer bonding method Pending CN110767541A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201911028550.3A CN110767541A (en) 2019-10-28 2019-10-28 Wafer bonding method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201911028550.3A CN110767541A (en) 2019-10-28 2019-10-28 Wafer bonding method

Publications (1)

Publication Number Publication Date
CN110767541A true CN110767541A (en) 2020-02-07

Family

ID=69334397

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911028550.3A Pending CN110767541A (en) 2019-10-28 2019-10-28 Wafer bonding method

Country Status (1)

Country Link
CN (1) CN110767541A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111785614A (en) * 2020-06-18 2020-10-16 上海空间电源研究所 Bonding structure capable of reducing voltage loss and preparation method thereof

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1241803A (en) * 1998-05-15 2000-01-19 佳能株式会社 Process for manufacturing semiconductor substrate as well as semiconductor thin film and multilayer structure
US20040152282A1 (en) * 2000-02-16 2004-08-05 Ziptronix, Inc. Method for low temperature bonding and bonded structure
TW200525585A (en) * 2003-10-13 2005-08-01 Mattson Tech Inc System and method for removal of photoresist in transistor fabrication for integrated circuit manufacturing
CN1860590A (en) * 2003-05-19 2006-11-08 齐普特洛尼克斯公司 Method of room temperature covalent bonding
CN101494177A (en) * 2008-01-23 2009-07-29 胜高股份有限公司 Method for producing bonded wafer
CN105632902A (en) * 2015-12-30 2016-06-01 哈尔滨工业大学 High and low temperature controllable wafer bonding method through semiconductor refrigeration sheet
CN105745739A (en) * 2013-11-18 2016-07-06 富士胶片株式会社 Semiconductor substrate treatment liquid, treatment method, and manufacturing method of semiconductor substrate product using these
TW201743367A (en) * 2016-06-14 2017-12-16 Shin Etsu Handotai Co Ltd Bonded wafer manufacturing method

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1241803A (en) * 1998-05-15 2000-01-19 佳能株式会社 Process for manufacturing semiconductor substrate as well as semiconductor thin film and multilayer structure
US20040152282A1 (en) * 2000-02-16 2004-08-05 Ziptronix, Inc. Method for low temperature bonding and bonded structure
CN1860590A (en) * 2003-05-19 2006-11-08 齐普特洛尼克斯公司 Method of room temperature covalent bonding
TW200525585A (en) * 2003-10-13 2005-08-01 Mattson Tech Inc System and method for removal of photoresist in transistor fabrication for integrated circuit manufacturing
CN101494177A (en) * 2008-01-23 2009-07-29 胜高股份有限公司 Method for producing bonded wafer
CN105745739A (en) * 2013-11-18 2016-07-06 富士胶片株式会社 Semiconductor substrate treatment liquid, treatment method, and manufacturing method of semiconductor substrate product using these
CN105632902A (en) * 2015-12-30 2016-06-01 哈尔滨工业大学 High and low temperature controllable wafer bonding method through semiconductor refrigeration sheet
TW201743367A (en) * 2016-06-14 2017-12-16 Shin Etsu Handotai Co Ltd Bonded wafer manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111785614A (en) * 2020-06-18 2020-10-16 上海空间电源研究所 Bonding structure capable of reducing voltage loss and preparation method thereof
CN111785614B (en) * 2020-06-18 2022-04-12 上海空间电源研究所 Bonding structure capable of reducing voltage loss and preparation method thereof

Similar Documents

Publication Publication Date Title
CN105185720B (en) A kind of ultra-thin thermal oxide wafer bonding technique for strengthening bond strength
CN103606521A (en) Manufacturing process of transient voltage suppression diode chip
EP3190633A1 (en) Wet-etching method for n-type double-sided battery
CN113161230B (en) Diffusion process of phosphorus-boron synchronous one-time diffusion graded junction chip
CN102569531B (en) Passivating method for polycrystalline silicon chips
CN111146311A (en) Boron diffusion method and N-type solar cell preparation method
EP2887383A1 (en) Soi wafer manufacturing method
CN103227245B (en) A kind of P type quasi-monocrystalline silicon too can the manufacture method of positive electricity pond PN junction
CN111668088A (en) Processing method of silicon carbide substrate
CN102832160B (en) Preparation method of SOI (silicon on insulator) silicon wafer
KR102447215B1 (en) SOI Wafer Manufacturing Method
CN110767541A (en) Wafer bonding method
CN202905718U (en) Silicon wafer with polycrystalline silicon gathering structure
EP1965413A1 (en) Method for manufacturing soi substrate, and soi substrate
CN103367409A (en) Preparation method for germanium substrate and La-based high-dielectric constant gate dielectric material
CN103474332B (en) Promote the lithographic method of netted growth Web Growth
CN103066150A (en) Method for manufacturing selective emitting electrode battery in one-step diffusion mode
CN105226135A (en) A kind of silicon heterogenous solar cell and preparation method thereof
CN106653677A (en) SOI wafer preparation method
JPH07193072A (en) Manufacture of semiconductor device
CN110233174A (en) The preparation method of gate dielectric layer that insulate and its preparation method of silicon carbide device and silicon carbide device
JP2008270592A (en) Manufacturing method of soi substrate
CN102915909A (en) Method for improving internal environment of acid tank type silicon wafer rinsing equipment
Choi et al. Chemical HF treatment for rear surface passivation of crystalline silicon solar cells
KR101462563B1 (en) Crystalline Silicon Wafer Solar Cell Etching Method and Apparatus using SiFx Barrier, Method and Apparatus for Fabricating Solar Cell using the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20200207

RJ01 Rejection of invention patent application after publication