CN110765715B - GPU chip rendering output unit performance simulation method and platform - Google Patents
GPU chip rendering output unit performance simulation method and platform Download PDFInfo
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- CN110765715B CN110765715B CN201911147540.1A CN201911147540A CN110765715B CN 110765715 B CN110765715 B CN 110765715B CN 201911147540 A CN201911147540 A CN 201911147540A CN 110765715 B CN110765715 B CN 110765715B
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Abstract
The invention relates to the technical field of computer hardware verification, in particular to a rendering output unit performance verification method and platform for a GPU chip. The method comprises the steps of constructing a Graphic Processing Unit (GPU) chip TLM virtual prototype platform based on SystemC (the virtual prototype verification platform comprises a rasterization unit, a rendering output unit, a color buffer unit and a depth buffer unit), converting a TLM transaction level port of the GPU rendering output unit into a hardware signal level port, embedding a rendering output RTL unit into the TLM virtual prototype platform, and carrying out module-level and system-level functional simulation on RTL of the GPU to verify whether the rendering output unit meets performance indexes of a corresponding model. Before the FPGA stage, whether the performance of the GPU rendering output unit meets the requirements or not can be verified in advance, and the development and verification work of the subsequent stage of the GPU chip are accelerated.
Description
Technical Field
The invention relates to the technical field of computer hardware verification, in particular to a GPU performance simulation method and platform based on a SystemC TLM virtual prototype.
Background
With the increasing number of graphics applications, early solutions for graphics rendering by CPU alone have been difficult to meet the ever-increasing graphics processing demands of performance and technology, and graphics processors (Graphic Processing Unit, GPU) have grown. The first GPU product released in Nvidia in 1999 has been developed by GPU technology, which mainly goes through a fixed function pipeline stage, a separate shader architecture stage, and a unified shader architecture stage, so that the graphics processing capability is continuously improved, and the application field is gradually expanded from the initial graphics drawing to the general computing field. The GPU pipeline has high speed, parallel characteristics and flexible programmable capability, and provides a good operation platform for graphic processing and general parallel computing.
For the software/hardware architecture and design of very large scale integrated circuit chips like GPUs, how to span from the traditional specification document to the hardware RTL circuit implementation becomes an important and urgent problem in the engineering practice process. In order to shorten the huge gap from the system architecture document to the hardware RTL circuit realization, the functions and architecture of the whole circuit system must be described by adopting a high-level modeling language between the two stages, and meanwhile, the complex signal timing and gate circuit of the hardware circuit cannot be involved.
The transaction level model (Transaction Level Models, TLM) is a higher level of abstraction than the RTL level, at which level the executable specification of the hardware can be quickly built, creating a system model quickly, from the initial functional specification of the system. By adding timing details to the system, the performance of the system can be evaluated and the structure of the system can be explored.
The system C is a modeling platform based on C++ which is established and maintained by OSCI (Open SystemC Initiative) organization, is completely written in C++ language, consists of a carefully designed C++ class library and a simulation kernel, supports modeling and simulation of hardware at various levels of abstraction of a gate level, an RTL level, a system level and the like, and is open source code. The SystemC supports the hardware/software collaborative design, can describe the structure of a complex system consisting of hardware and software, and supports the description of the hardware, the software and the interfaces in the C++ environment. The system C can be used for realizing the abstraction of functional modules, communication modules, software modules and hardware modules at various system level levels, and the introduced port and the data type description of signals, clock and delay concepts are based on the idea that the description of the software and the hardware is unified into a modeling language. The accurate model of the software algorithm, the architecture of hardware, the interface of the SoC and the design of the system level can be quickly and effectively built by using the SystemC, and the design is simulated, verified and optimized (the simulation speed is 10-100 times that of the simulation speed by using the VHDL or Verilog model by using the SystemC). The most basic building block of SystemC is a module (module), which may contain other modules or processes and methods (methods) like functions in the C language to implement a certain behavior. The modules communicate with other modules via interfaces (ports) that are connected by signals. A complete system is made up of a number of modules, each containing one or more processes and methods, which are operated in parallel, with signals being communicated between them. Clock is a special signal used to control timing and synchronize the process during simulation. The design method based on the SystemC supports the designer to model on different layers, reduces the code quantity and the workload, provides higher working efficiency, and can simulate the SystemC more efficiently and rapidly compared with the traditional method.
Disclosure of Invention
In order to solve the problems in the prior art, a method for simulating the performance of a rendering output unit facing a GPU chip is provided, and the method comprises the following steps:
1) Building a performance simulation platform aiming at a GPU chip-oriented rendering output unit by adopting a SystemC language and a transaction level modeling TLM method;
2) The port conversion of the rendering output unit in the performance simulation platform only converts an external transaction level port into a hardware signal level port, and the rendering output RTL unit is embedded into the port conversion of the rendering output unit;
3) Collecting input and output time sequences of the rendering output RTL unit through port conversion of the rendering output unit, and counting the performance efficiency of the rendering output RTL unit so as to achieve the purpose of performance simulation verification of the rendering output RTL unit;
preferably, the method for realizing the conversion into the hardware signal level port comprises the following steps: the port of the rendering output unit converts the input transaction of the monitoring sampling rasterization unit (2), and converts the transaction content into hardware signal high-low level driving taking a clock cycle as a unit according to the read-write attribute of the transaction;
preferably, the method for realizing the port conversion of the rendering output RTL unit embedded into the rendering output unit comprises the following steps: embedding a rendering output RTL unit into a port of the rendering output unit for conversion through signal docking;
preferably, the manner of performing performance simulation on the rendering output RTL unit is as follows:
the rasterizing unit sends the chip metadata to the port conversion of the rendering output unit of the GPU chip, the port conversion of the rendering output unit sends the received data to the rendering output RTL unit, and meanwhile, the signal output of the rendering output RTL unit is monitored and counted, so that the purpose of performance simulation verification of the rendering output RTL unit is achieved.
The invention also provides a rendering output unit performance simulation platform facing the GPU chip for executing the simulation method, which comprises a rendering output unit port conversion unit, a rendering output RTL unit, a rasterization unit, a color buffer unit and a depth buffer unit;
the rendering output unit port converts and receives the piece metadata sent by the rasterization unit and transmits the piece metadata to the rendering output RTL unit through the signal level port;
the port conversion of the rendering output unit receives the output of the rendering output RTL unit, counts the data quantity and the simulation time, and calculates the performance of the rendering output unit;
the rendering output RTL unit receives the chip metadata from the port conversion of the rendering output unit, performs hardware register transmission level operation, and outputs the result to the port conversion of the rendering output unit;
the rasterizing unit sends the piece metadata subjected to the rasterizing operation to a rendering output unit port for conversion;
the color buffer area unit receives and stores the output converted by the port of the rendering output unit;
the depth buffer zone unit receives and stores the output converted by the rendering output unit port;
preferably, the simulation platform comprises a rendering output unit port conversion unit, a rendering output RTL unit, a rasterization unit, a color buffer unit and a depth buffer unit.
The rendering output unit port conversion comprises a rasterExport port, the port is connected with a rasterPort port of the rasterization unit, and the ports are communicated through a RasterIf interface;
the rendering output unit port conversion comprises a colorBufPort port, the port is connected with a colorBufPort port of the color buffer unit, and the ports are communicated through a ColorBufIf interface;
the rendering output unit port conversion comprises a depthBufPort port which is connected with a depthBufExport port of the depth buffer unit, and the ports are communicated through a depthBufif interface;
the rasterizing unit comprises a rasterPort port, the port is connected with a rasterExport port converted by a rendering output unit port, and the ports are communicated through a Rasterif interface;
the color buffer zone unit comprises a colorBufExport port, the port is connected with a colorBufExport port converted by a rendering output unit port, and the ports are communicated through a ColorBufIf interface;
the depth buffer zone unit comprises a depthBufExport port which is connected with a depthBufPort port converted by a rendering output unit port, and the depthBufIf ports are communicated through a depthBufIf interface.
In summary, the beneficial technical effects of the invention are as follows:
1. performing TLM modeling on the performance of the GPU according to module division by adopting SystemC, and replacing TLM modules of any level in the GPU with RTL codes, so that the actual working performance of the RTL is tested in a simulation mode, and whether the performance of the RTL codes meets the requirements can be judged by referring to the performance indexes of the corresponding modules in the virtual prototype;
2. the prior work of testing the RTL performance in the FPGA stage is advanced to the virtual prototype verification stage, so that the progress of the project is accelerated, and the cost of later iteration of the project is reduced;
drawings
FIG. 1 is a performance simulation platform of a rendering output unit of a GPU chip of the present invention.
Wherein: 1. rendering output unit port conversion; 1-1, rendering and outputting an RTL unit; 2. a rasterizing unit; 3. a color buffer unit; 4. depth buffer unit.
Detailed Description
The present invention will now be described in detail with reference to the accompanying drawings.
In one embodiment of the present invention, a method for simulating performance of a rendering output unit facing a GPU chip is provided, the method comprising the following steps:
1) Building a performance simulation platform aiming at a GPU chip-oriented rendering output unit by adopting a SystemC language and a transaction level modeling TLM method;
2) The rendering output unit port conversion 1 in the performance simulation platform only converts an external transaction level port into a hardware signal level port, and the rendering output RTL unit 1-1 is embedded into the rendering output unit port conversion 1;
3) Collecting input and output time sequences of the rendering output RTL unit 1-1 through the port conversion 1 of the rendering output unit, and counting the performance efficiency of the rendering output RTL unit 1-1 so as to achieve the purpose of performance simulation verification of the rendering output RTL unit 1-1;
the method for realizing the conversion into the hardware signal level port comprises the following steps: the port conversion 1 of the rendering output unit monitors the input transaction of the sampling rasterization unit 2, and converts the transaction content into hardware signal high-low level driving taking a clock cycle as a unit according to the read-write attribute of the transaction;
the method for realizing the embedding of the rendering output RTL unit 1-1 into the port conversion 1 of the rendering output unit comprises the following steps: embedding the rendering output RTL unit 1-1 into the port conversion 1 of the rendering output unit through signal docking;
the implementation mode for performing performance simulation on the rendering output RTL unit 1-1 is as follows:
the rasterizing unit 2 sends the piece metadata to the GPU chip rendering output unit port conversion 1, the rendering output unit port conversion 1 sends the received data to the rendering output RTL unit 1-1, and meanwhile, the signal output of the rendering output RTL unit 1-1 is monitored and counted, so that the purpose of performance simulation verification of the rendering output RTL unit 1-1 is achieved.
In one embodiment, the manner of implementing performance simulation for the render output RTL unit is:
the rasterizing unit sends the piece metadata to the GPU chip rendering output unit port conversion 1, the rendering output unit port conversion 1 sends the received data to the rendering output RTL unit, and meanwhile, the signal output of the rendering output RTL unit is monitored and counted, so that the purpose of performance simulation verification of the rendering output unit is achieved.
In one embodiment, a GPU chip-oriented rendering output unit performance simulation platform is provided for executing the simulation method, including a rendering output unit port conversion 1, a rendering output RTL unit 1-1, a rasterization unit 2, a color buffer unit 3, and a depth buffer unit 4, where the method further includes:
the port conversion 1 of the rendering output unit receives the piece metadata sent by the rasterization unit and transmits the piece metadata to the rendering output RTL unit 1-1 through the signal level port;
the port conversion 1 of the rendering output unit receives the output of the rendering output RTL unit 1-1, counts the data quantity and the simulation time, and calculates the performance of the rendering output unit;
the rendering output RTL unit 1-1 receives the piece metadata from the rendering output unit port conversion 1, performs hardware register transmission level operation, and outputs the result to the rendering output unit port conversion 1;
the rasterizing unit 2 sends the piece metadata subjected to the rasterizing operation to the rendering output unit port conversion 1;
the color buffer unit 3 receives and stores the output of the port conversion 1 of the rendering output unit;
the depth buffer unit 4 receives and stores the output of the rendering output unit port conversion 1;
in one embodiment, the emulation platform includes a render output unit port conversion 1, a render output RTL unit 1-1, a rasterization unit 2, a color buffer unit 3, and a depth buffer unit 4.
The rendering output unit port conversion 1 comprises a rasterExport port which is connected with a rasterPort port of the rasterization unit 2, and the ports are communicated through a Rasterif interface;
the rendering output unit port conversion 1 comprises a colorBufPort port, the colorBufPort port is connected with a colorBufPort port of the color buffer unit 3, and the ports are communicated through a ColorBufIf interface;
the rendering output unit port conversion 1 comprises a depthBufPort port, the depthBufExport port is connected with the depthBufExport port of the depth buffer unit 4, and the ports are communicated through a depthBufif interface;
the rasterizing unit 2 comprises a rasterPort port which is connected with a rasterExport port of the rendering output unit port conversion 1, and the ports are communicated through a Rasterif interface;
the color buffer zone unit 3 comprises a colorBufExport port, the port is connected with a colorBufExport port of the rendering output unit port conversion 1, and the ports are communicated through a ColorBufIf interface;
the depth buffer unit 4 includes a depthBufExport port, which is connected to a depthBufExport port of the port conversion 1 of the rendering output unit, and the above ports communicate with each other through a depthbufeif interface.
Finally, it should be noted that the above embodiments are merely illustrative of the technical solution of the present invention, and not limiting thereof; although the invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art will understand that; the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (3)
1. The rendering output unit performance simulation method facing the GPU chip is characterized by comprising the following steps of:
1) Building a performance simulation platform aiming at a GPU chip-oriented rendering output unit by adopting a SystemC language and a transaction level modeling TLM method;
2) The method comprises the steps that a rendering output unit port conversion (1) in a performance simulation platform only converts an external transaction level port into a hardware signal level port, and a rendering output RTL unit (1-1) is embedded into the rendering output unit port conversion (1);
3) Collecting input and output time sequences of the rendering output RTL unit (1-1) through the port conversion (1) of the rendering output unit, and counting the performance efficiency of the rendering output RTL unit (1-1), so as to achieve the purpose of performance simulation verification of the rendering output RTL unit (1-1);
the method for realizing the conversion into the hardware signal level port comprises the following steps: the port conversion of the rendering output unit (1) monitors the input transaction of the sampling rasterization unit (2), and converts the transaction content into hardware signal high-low level driving taking a clock cycle as a unit according to the read-write attribute of the transaction;
the method for realizing the port conversion (1) of the rendering output RTL unit (1-1) embedded into the rendering output unit comprises the following steps: embedding a rendering output RTL unit (1-1) into a rendering output unit port conversion (1) through signal docking;
the method for realizing performance simulation of the rendering output RTL unit (1-1) comprises the following steps:
the rasterizing unit (2) sends the piece metadata to the GPU chip rendering output unit port conversion (1), the rendering output unit port conversion (1) sends the received data to the rendering output RTL unit (1-1), and meanwhile, the signal output of the rendering output RTL unit (1-1) is monitored and counted, so that the purpose of performance simulation verification of the rendering output RTL unit (1-1) is achieved.
2. A GPU-chip oriented rendering output unit performance simulation platform for performing the method of claim 1, wherein: the simulation platform comprises a rendering output unit port conversion unit (1), a rendering output RTL unit (1-1), a rasterization unit (2), a color buffer unit (3) and a depth buffer unit (4);
the rendering output unit port conversion (1) is used for receiving the piece metadata sent by the rasterization unit and transmitting the piece metadata to the rendering output RTL unit (1-1) through the signal level port;
the port conversion (1) of the rendering output unit is used for receiving the output of the rendering output RTL unit (1-1), counting the data quantity and the simulation time and calculating the performance of the rendering output unit;
the rendering output RTL unit (1-1) is used for receiving the piece metadata from the rendering output unit port conversion (1), performing hardware register transmission level operation, and outputting the result to the rendering output unit port conversion (1);
the rasterizing unit (2) is used for sending the piece metadata subjected to the rasterizing operation to the port conversion (1) of the rendering output unit;
the color buffer unit (3) is used for receiving and storing the output of the port conversion (1) of the rendering output unit;
the depth buffer unit (4) is used for receiving and storing the output of the rendering output unit port conversion (1).
3. The GPU-chip oriented host interface unit performance simulation platform of claim 2, wherein:
the rendering output unit port conversion (1) comprises a rasterExport port, the port is connected with a rasterPort port of the rasterization unit (2), and the ports are communicated through a RasterIf interface;
the rendering output unit port conversion (1) comprises a colorbuf port, the colorbuf port is connected with a colorbuf port of the color buffer unit (3), and the ports are communicated through a colorbuf interface;
the rendering output unit port conversion (1) comprises a depthBufPort port, the depthBufExport port is connected with a depthBufExport port of the depth buffer unit (4), and the ports are communicated through a depthBufif interface;
the rasterization unit (2) comprises a rasterPort port, the port is connected with a rasterExport port of the port conversion (1) of the rendering output unit, and the ports are communicated through a Rasterif interface;
the color buffer zone unit (3) comprises a colorBufExport port, the port is connected with a colorBufExport port of the rendering output unit port conversion (1), and the ports are communicated through a ColorBufIf interface;
the depth buffer unit (4) comprises a depthBufExport port which is connected with a depthBufPort port of the rendering output unit port conversion (1), and the depthBufIf ports are communicated through a depthBufIf interface.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3382652A1 (en) * | 2017-04-01 | 2018-10-03 | INTEL Corporation | Tile-based immediate mode rendering with early hierarchical-z |
| CN109446740A (en) * | 2018-12-20 | 2019-03-08 | 湖南国科微电子股份有限公司 | A kind of system on chip framework performance emulation platform |
| CN109598077A (en) * | 2018-12-11 | 2019-04-09 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of graphics pipeline device and modeling method based on GPU chip |
| CN109669832A (en) * | 2018-12-11 | 2019-04-23 | 中国航空工业集团公司西安航空计算技术研究所 | One kind is towards GPU graphics chip pipeline unit performance verification method and platform |
| CN109710229A (en) * | 2018-12-11 | 2019-05-03 | 中国航空工业集团公司西安航空计算技术研究所 | One kind is towards GPU graphics chip pipeline unit framework verification method and platform |
| CN109711003A (en) * | 2018-12-11 | 2019-05-03 | 中国航空工业集团公司西安航空计算技术研究所 | One kind is towards GPU graphics chip pipeline unit functional simulation method and platform |
| CN109753280A (en) * | 2018-12-11 | 2019-05-14 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of graphics processor TLM model image output method based on SystemC |
| GB201907765D0 (en) * | 2019-05-31 | 2019-07-17 | Imagination Tech Ltd | Graphics processing units and methods using render progression checks |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8134561B2 (en) * | 2004-04-16 | 2012-03-13 | Apple Inc. | System for optimizing graphics operations |
| US10706493B2 (en) * | 2017-12-29 | 2020-07-07 | Intel Corporation | Apparatus and method for display virtualization using mapping between virtual and physical display planes |
-
2019
- 2019-11-21 CN CN201911147540.1A patent/CN110765715B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3382652A1 (en) * | 2017-04-01 | 2018-10-03 | INTEL Corporation | Tile-based immediate mode rendering with early hierarchical-z |
| CN109598077A (en) * | 2018-12-11 | 2019-04-09 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of graphics pipeline device and modeling method based on GPU chip |
| CN109669832A (en) * | 2018-12-11 | 2019-04-23 | 中国航空工业集团公司西安航空计算技术研究所 | One kind is towards GPU graphics chip pipeline unit performance verification method and platform |
| CN109710229A (en) * | 2018-12-11 | 2019-05-03 | 中国航空工业集团公司西安航空计算技术研究所 | One kind is towards GPU graphics chip pipeline unit framework verification method and platform |
| CN109711003A (en) * | 2018-12-11 | 2019-05-03 | 中国航空工业集团公司西安航空计算技术研究所 | One kind is towards GPU graphics chip pipeline unit functional simulation method and platform |
| CN109753280A (en) * | 2018-12-11 | 2019-05-14 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of graphics processor TLM model image output method based on SystemC |
| CN109446740A (en) * | 2018-12-20 | 2019-03-08 | 湖南国科微电子股份有限公司 | A kind of system on chip framework performance emulation platform |
| GB201907765D0 (en) * | 2019-05-31 | 2019-07-17 | Imagination Tech Ltd | Graphics processing units and methods using render progression checks |
Non-Patent Citations (4)
| Title |
|---|
| 任向隆 ; 田泽 ; 张骏 ; 颜哲 ; 韩立敏 ; .支持双路显示的GPU显示控制单元设计与实现.小型微型计算机系统.2015,(09),全文. * |
| 田泽 ; 张淑 ; 张骏 ; 许宏杰 ; 黎小玉 ; 郭蒙 ; .图形处理器片段处理单元的设计与实现.计算机应用.2014,(S2),全文. * |
| 田泽 ; 韩立敏 ; 张骏 ; 任向隆 ; .并行处理二维图形加速引擎结构设计.计算机工程与设计.2015,(03),全文. * |
| 邓军勇 ; 李涛 ; 蒋林 ; 韩俊刚 ; 沈绪榜 ; .面向OpenGL的图形加速器设计与实现.西安电子科技大学学报.(06),全文. * |
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