CN110765468A - Encryption card - Google Patents
Encryption card Download PDFInfo
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- CN110765468A CN110765468A CN201810850456.5A CN201810850456A CN110765468A CN 110765468 A CN110765468 A CN 110765468A CN 201810850456 A CN201810850456 A CN 201810850456A CN 110765468 A CN110765468 A CN 110765468A
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- encryption
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
- G06F21/602—Providing cryptographic facilities or services
Abstract
The invention discloses an encryption card, which at least comprises a slave interface, a host interface and an encryption and decryption engine, wherein the slave interface is used for accessing a front-stage host device, the host interface is used for cascading a rear-stage encryption card, and the encryption and decryption engine is connected with the slave interface and the host interface and is used for executing tasks to be processed distributed to the encryption card according to a control instruction. By adopting the technical scheme of the invention, a plurality of encryption cards can be cascaded through the standard interface, and the encryption cards can be infinitely expanded theoretically so as to meet the requirements of various encryption and decryption applications.
Description
Technical Field
The invention relates to the technical field of data security, in particular to an encryption card.
Background
The encryption card is a commonly used data encryption and decryption device, but in the prior art, the encryption card is usually used as an independent unit to realize data encryption and decryption operation, and after the encryption and decryption are completed, the data are directly returned to a task sender. The encryption card mechanism in the prior art can improve the data encryption and decryption efficiency of the encryption card only by the timely response of the host, and seriously occupies host resources to a certain extent.
Therefore, it is necessary to provide a technical solution to solve the technical problems of the prior art.
Disclosure of Invention
In view of the above, it is necessary to provide an encryption card, which can cascade a plurality of encryption cards through a standard interface, and can expand the encryption card infinitely to meet the requirements of various encryption and decryption applications in theory; meanwhile, a memory is arranged in the encryption card, and data communication is realized by adopting a standard memory interface and a standard protocol, so that the encryption and decryption functions are encapsulated in the memory protocol, and the host computer realizes the allocation and acquisition of encryption and decryption tasks through a memory instruction, thereby greatly improving the utilization rate of host computer resources.
In order to overcome the defects of the prior art, the technical scheme of the invention is as follows:
an encryption card at least comprises a slave interface, a host interface and an encryption and decryption engine, wherein the slave interface is used for accessing a front-stage host device, the host interface is used for cascading a rear-stage encryption card, and the encryption and decryption engine is connected with the slave interface and the host interface and is used for executing a task to be processed distributed to the encryption card according to a control instruction;
the encryption and decryption engine further comprises a control unit, a data encryption and decryption unit, a random number generator and a memory, wherein,
the random number generator is used for generating a random number under the control of the control unit as a key for data encryption and decryption operation;
the data encryption and decryption unit at least comprises an encryption processing unit, a decryption processing unit and a key storage unit, and the encryption processing unit is used for executing data encryption operation; the decryption processing unit is used for executing data decryption operation; the key storage unit is used for storing a key;
the memory is provided with an encryption storage unit and a decryption storage unit, wherein the encryption storage unit and the decryption storage unit are respectively provided with a plurality of storage units which are respectively used for storing data after encryption operation or decryption operation is executed;
the control unit is connected with the data encryption and decryption unit and the memory and is used for acquiring the instruction sent by the host computer, analyzing the instruction and executing corresponding processing;
when the obtained instruction is a write instruction and the write address is an encryption storage unit, the control unit sends the task to be processed to the data encryption and decryption unit, and the task to be processed is directly stored in the corresponding storage unit after being encrypted by the encryption processing unit; when the obtained instruction is a write instruction and the write address is a decryption storage unit, the control unit sends the task to be processed to the data encryption and decryption unit, and the task to be processed is directly stored in the corresponding storage unit after being decrypted by the decryption processing unit; simultaneously, the control unit feeds back a task completion message to the host, wherein the feedback task completion message at least comprises the address information of the storage unit corresponding to the task;
and when the acquired instruction is a read instruction, the control unit acquires the address information in the instruction, reads the data information of the storage unit corresponding to the address and sends the data information to the host.
As the preferred technical scheme, the encryption card is provided with a plurality of encryption and decryption engines, and each encryption and decryption engine is provided with a unique identification number.
As a preferred technical solution, the encryption and decryption engine further comprises an algorithm storage unit, and the algorithm storage unit is connected with the control unit and the data encryption and decryption unit and is used for storing the algorithm for data encryption and decryption; and the data encryption and decryption unit selects a corresponding encryption algorithm according to the control instruction of the control unit.
As a preferred technical solution, the encryption card further includes a buffer unit, and the buffer unit is connected to the control unit and is used for buffering data.
As a preferred technical solution, the memory adopts a plurality of eMMC chips, and the plurality of eMMC chips are cascaded through a bus.
As a preferred technical solution, when the control unit executes a write operation, it selects an idle storage unit and sends its address information and the task to be processed to the data encryption and decryption unit together; and the data encryption and decryption unit directly stores the processed tasks into the storage unit after executing encryption and decryption operations.
As a preferred technical solution, the control unit sets an engine state table, where the engine state table is used to record the state of each encryption/decryption engine and dynamically update the state of each encryption/decryption engine so that the control unit can allocate tasks to be processed.
As a preferred technical solution, the control unit sets a memory mapping table, where the memory mapping table is used to record each task and the address of the corresponding memory unit.
As a preferred technical solution, the memory mapping table further sets a storage flag bit, where the storage flag bit is used to identify a read-write state of data in a storage unit, and the data in the storage unit is read out and then releases the storage space for a subsequent write operation.
As a preferred technical solution, the slave interface or the host interface adopts any one of an SD interface, a USB interface, and a SATA interface.
Compared with the prior art, the encryption card can be cascaded through a standard interface, and can be infinitely expanded theoretically to meet the requirements of various encryption and decryption applications; meanwhile, a memory is arranged in the encryption card, and data communication is realized by adopting a standard memory interface and a protocol, so that the encryption and decryption functions are encapsulated in the memory protocol, and the host realizes encryption and decryption task allocation and acquisition through a memory instruction, can be autonomously controlled, does not need real-time response, and greatly improves the utilization rate of host resources.
Drawings
FIG. 1 is a schematic block diagram of an encryption card of the present invention.
FIG. 2 is a schematic block diagram of an encryption card according to another embodiment of the present invention.
FIG. 3 is a diagram of the cascade of encryption cards according to the present invention.
Fig. 4 is a schematic block diagram of an encryption/decryption engine according to the present invention.
FIG. 5 is a flow chart of a data encryption and decryption method of an encryption card according to the present invention.
Flow diagram of a data processing method.
The following specific embodiments will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
The technical solution provided by the present invention will be further explained with reference to the accompanying drawings.
Referring to fig. 1, a schematic block diagram of an encryption card architecture of the present invention is shown, which at least includes a slave interface, a host interface and an encryption/decryption engine, wherein the slave interface is used for accessing a previous-stage host device, the host interface is used for cascading a subsequent-stage encryption card, and the encryption/decryption engine is connected to the slave interface and the host interface, and is used for executing a task to be processed assigned to the encryption card according to a control instruction. Preferably, the slave interface or the host interface adopts any one of an SD interface, a USB interface, or a SATA interface.
Referring to fig. 2, a schematic block diagram of an encryption card architecture according to another embodiment of the present invention is shown, in which a plurality of encryption/decryption engines are disposed in an encryption card, so that the stronger the concurrent data processing capability is greatly improved. Meanwhile, each encryption card and each encryption and decryption engine thereof are provided with a unique identification number, so that addressing control can be conveniently realized.
Referring to fig. 3, which is a schematic diagram showing the cascade connection of the encryption cards of the present invention, the encryption card of the present invention can cascade a plurality of encryption cards through a standard interface, so that the encryption card can be infinitely expanded theoretically to meet the requirements of various encryption and decryption applications. In a preferred embodiment, the tree-shaped expansion model is adopted to realize the cascade expansion of the encryption cards. Furthermore, in cascade control, because each encryption and decryption engine is internally provided with an ID with a unique identifier, the encryption and decryption host generates a mapping table of all engines under the framework, directly distributes encryption and decryption tasks for each encryption and decryption engine by using the ID and updates the load capacity mapping table; each encryption and decryption engine receives the ID of the encryption and decryption task and processes the task if the IDs are matched; otherwise, the task is sent to the next-level encryption card cascaded with the task. By adopting the technical scheme, data direct transmission can be realized, and the time for traversing each encryption card during each distribution is saved, so that the processing capacity is improved.
In a preferred embodiment, the encryption and decryption host monitors the encryption cards at regular time and updates the engine mapping table, and the information processing frequency of each encryption card is ensured to be basically equal by maintaining the mapping table and adopting an equalization algorithm. Thereby avoiding the damage of the storage unit of a certain encryption card due to frequent storage.
Referring to fig. 4, a schematic block diagram of the encryption and decryption engine of the present invention is shown, further comprising a control unit, a data encryption and decryption unit, a random number generator and a memory, wherein,
the random number generator is used for generating a random number under the control of the control unit as a key for data encryption and decryption operation;
the data encryption and decryption unit at least comprises an encryption processing unit, a decryption processing unit and a key storage unit, wherein the encryption processing unit is used for executing data encryption operation; the decryption processing unit is used for executing data decryption operation; the key storage unit is used for storing a key;
the memory is provided with an encryption storage unit and a decryption storage unit, wherein the encryption storage unit and the decryption storage unit are respectively provided with a plurality of storage units which are respectively used for storing data after encryption operation or decryption operation is executed;
the control unit is connected with the data encryption and decryption unit and the memory and is used for acquiring the instruction sent by the host computer, analyzing the instruction and executing corresponding processing;
when the obtained instruction is a write instruction and the write address is an encryption storage unit, the control unit sends the task to be processed to the data encryption and decryption unit, and the task to be processed is directly stored in the corresponding storage unit after being encrypted by the encryption processing unit; when the obtained instruction is a write instruction and the write address is a decryption storage unit, the control unit sends the task to be processed to the data encryption and decryption unit, and the task to be processed is directly stored in the corresponding storage unit after being decrypted by the decryption processing unit; meanwhile, after the processed task is stored, the control unit feeds back a task completion message to the host, wherein the feedback task completion message at least comprises the address information of the storage unit corresponding to the task;
and when the acquired instruction is a read instruction, the control unit acquires the address information in the instruction, reads the data information of the storage unit corresponding to the address and sends the data information to the host.
By adopting the technical scheme, the memory is arranged in the encryption card, the data communication is realized by adopting the standard storage interface and the protocol, the encryption and decryption functions are encapsulated in the storage protocol, the encryption and decryption operation can be realized by adopting the read-write instruction by the host, the host can be controlled independently, the real-time response is not needed, and the utilization rate of the host resources is greatly improved. For an external host, the encryption card is equivalent to a common external common storage device, such as a usb disk, a hard disk, and the like. Different from the prior art, the invention also has the data encryption and decryption functions under the normal read-write operation. Under the framework of the invention, the data encryption operation is equivalent to writing the data to be encrypted into the encryption card, and other operations can be processed after the host computer sends a write instruction without waiting; and after the encryption and decryption operation is finished, the encryption card sends a notification instruction to inform the host that the encryption operation of the corresponding task is finished, and the host acquires the data information stored in the corresponding address through a reading instruction to finish an encryption/decryption operation flow.
In the technical scheme, the encryption/decryption operation and the address space are bound, and the specific encryption/decryption operation type can be analyzed by identifying the address space, so that the encryption/decryption operation is greatly simplified.
In addition, a plurality of storage units are arranged in the memory; each storage unit is used for storing one task, and each data encryption and decryption unit is correspondingly distributed with a plurality of storage units, so that the data encryption and decryption unit can cache a plurality of tasks; meanwhile, the data encryption and decryption unit directly stores the tasks in the corresponding storage units after completing encryption/decryption operation; the control unit is also connected with the memory and can directly read the data information in the memory. By adopting the framework, the writing and reading of the memory are completed through two independent channels, and the data encryption and decryption unit can be absorbed in the data encryption and decryption, so that the data encryption and decryption efficiency is greatly improved.
In a preferred embodiment of the present invention, when the control unit executes the write operation, it selects a free storage unit and sends its address information and the task to be processed to the data encryption and decryption unit; and the data encryption and decryption unit directly stores the processed tasks into the storage unit after executing encryption and decryption operations. That is, the control unit allocates the free storage module to store the task while allocating the task, thereby conveniently establishing the mapping relationship. By adopting the technical scheme, the data encryption and decryption unit can be directly stored to the corresponding storage unit after the encryption and decryption operation is completed, meanwhile, the control unit directly reads and writes the storage unit, and the data are fed back to the host and the data encryption and decryption process are completely independent, so that the processing efficiency is greatly improved.
Furthermore, the control unit sets a memory mapping table, and the memory mapping table is used for recording the address of each task and the corresponding memory unit. And simultaneously, a storage flag bit is also set in the storage mapping table, the storage flag bit is used for identifying the read-write state of the data in the storage unit, and the storage space is released for subsequent write-in operation after the data in the storage unit is read out. By adopting the technical scheme, the states of data reading and writing in the storage unit are identified by setting the storage flag bit, at least including ready and done states, and when the state is set as ready, the tasks are stored in the corresponding storage units after encryption/decryption; the state is done, which indicates that corresponding data has been read from the storage unit, and the storage space can be released, so that the storage unit can store circularly, and the utilization rate of the storage space is greatly improved.
Further, the control unit sets an engine state table, and the engine state table is used for recording the state of each encryption and decryption engine and dynamically updating the state of each encryption and decryption engine so that the control unit can distribute the tasks to be processed. The control unit reasonably regulates and controls the work of the encryption and decryption engine according to the engine state table, and after the task is stored, the data encryption and decryption unit can process the next encryption and decryption task.
The storage mapping table at least comprises a task number, an engine number, engine state information and storage address information, wherein the task number is a unique identification number set by each received task; the engine number is an identification number of an encryption/decryption engine which carries out encryption/decryption operation on the task; the engine state information is the working state of the data encryption and decryption process; the storage address information is address information of a storage unit stored after the task performs encryption/decryption operation. Specifically, after receiving a task sent by a host, a control unit establishes an IO task and determines a corresponding task number, and after the IO task completes a specified operation, corresponding feedback is performed on the host; after an IO task is established, the control unit allocates an idle encryption and decryption engine to process the task, wherein the state information at least comprises busy and idle, and the state setting busy represents that the data encryption and decryption unit is performing data processing; the status is set to idle, which indicates that the data encryption and decryption unit completes the processing task, so that the data encryption and decryption unit can undertake a new task. By adopting the technical scheme, the process state of any task, the working state of the encryption and decryption engine and the address space state of the memory can be clearly known through the memory mapping table, so that the encryption and decryption processing of the task is facilitated.
In a preferred embodiment, the encryption and decryption engine further comprises an algorithm storage unit for storing an algorithm for data encryption and decryption, and the algorithm storage unit is connected with the control unit and the data encryption and decryption unit; and the data encryption and decryption unit selects a corresponding encryption algorithm according to the control instruction of the control unit. Further, the control unit receives a configuration command of the host, wherein the configuration command is used for configuring the encryption and decryption encryption algorithm type of the data encryption and decryption unit, and the encryption algorithm is at least one of AES-128/256, SM2, SM3, SM4, RSA, 3DES or SHA. Meanwhile, the configuration instruction also comprises the data length of the task to be processed, and the control unit redistributes the address space of the storage unit for the data encryption and decryption unit according to the configuration instruction. For example, if the current encryption task size is 2K, and the length after processing by the SM2 encryption algorithm is 4K, the storage space is reallocated by using the 4K space as the basic storage unit. By adopting the technical scheme, the dynamic allocation of the storage units is realized, so that an encryption algorithm can be set according to the requirements of users, and an optimal storage unit can be set according to actual requirements.
In the technical scheme, the control instruction is adopted to select the corresponding encryption algorithm, so that the complexity of the algorithm is increased to a certain extent. In a preferred embodiment, a plurality of encryption and decryption encryption algorithms are arranged in the encryption card, and the algorithm types are directly bound with a specific storage address space. That is, a plurality of encryption storage units and decryption storage units are arranged in a memory, each encryption storage unit or decryption storage unit is bound with the type of a specific encryption algorithm, data write operation is performed on the encryption storage unit at a specified address, a controller analyzes an encryption command of a corresponding encryption and decryption algorithm, similarly, the data write operation controller analyzes a decryption command of the decryption storage unit at the specified address into a decryption command of the corresponding encryption and decryption algorithm, the data encryption and decryption unit selects the corresponding encryption and decryption algorithm to perform encryption and decryption operation, after the encryption and decryption processing is finished, the data after the encryption and decryption processing is stored in the encryption/decryption storage unit, the controller informs a host of read operation performed on the address, and the read data is the data after the encryption and decryption processing is finished. By adopting the technical scheme, the algorithm type is directly bound with the specific storage address space, so that the data communication protocol is greatly simplified.
In a preferred embodiment, the encryption card further includes a buffer unit, and the buffer unit is connected to the control unit and is configured to buffer data.
In a preferred embodiment, the memory adopts a plurality of eMMC chips, and the plurality of eMMC chips are cascaded through a bus.
Referring to fig. 5, a flow chart of the data encryption and decryption method of the encryption card of the present invention is shown, which includes the following steps:
step S1: the host sends an instruction to the encryption card;
step S2: the encryption card acquires instructions sent by the host computer and distributes the instructions to the encryption and decryption engines;
step S3: the encryption and decryption engine analyzes the instruction and executes corresponding operation;
step S4: after the operation is finished, feeding back a message to the host;
the encryption and decryption engine at least comprises a control unit, a data encryption and decryption unit and a memory, wherein the data encryption and decryption unit at least comprises an encryption processing unit and a decryption processing unit, and the encryption processing unit is used for executing data encryption operation; the decryption processing unit is used for executing data decryption operation;
the memory is provided with an encryption storage unit and a decryption storage unit, wherein the encryption storage unit and the decryption storage unit are respectively provided with a plurality of storage units which are respectively used for storing data after encryption operation or decryption operation is executed;
in the step S3, in the above step,
when the obtained instruction is a write instruction and the write address is an encryption storage unit, the control unit sends the task to be processed to the data encryption and decryption unit, and the task to be processed is directly stored in the corresponding storage unit after being encrypted by the encryption processing unit; when the obtained instruction is a write instruction and the write address is a decryption storage unit, the control unit sends the task to be processed to the data encryption and decryption unit, and the task to be processed is directly stored in the corresponding storage unit after being decrypted by the decryption processing unit;
when the obtained instruction is a read instruction, the control unit obtains address information in the instruction and reads data information of a storage unit corresponding to the address;
in the step S4, in the above step,
after the write command is executed, the control unit feeds back a task completion message to the host, wherein the feedback task completion message at least comprises the address information of the storage unit corresponding to the task;
and after the reading instruction is executed, the control unit sends the data information of the corresponding storage unit to the host.
As a preferred technical solution, the encryption card at least includes a slave interface, a host interface and an encryption/decryption engine, wherein the slave interface is used for accessing a previous-stage host device, the host interface is used for cascading a next-stage encryption card, and the encryption/decryption engine is connected with the slave interface and the host interface and is used for executing a task to be processed assigned to the encryption card according to a control instruction.
The above description of the embodiments is only intended to facilitate the understanding of the method of the invention and its core idea. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. An encryption card is characterized by at least comprising a slave interface, a host interface and an encryption and decryption engine, wherein the slave interface is used for accessing a front-stage host device, the host interface is used for cascading a rear-stage encryption card, and the encryption and decryption engine is connected with the slave interface and the host interface and is used for executing tasks to be processed distributed to the encryption card according to a control instruction;
the encryption and decryption engine further comprises a control unit, a data encryption and decryption unit, a random number generator and a memory, wherein,
the random number generator is used for generating a random number under the control of the control unit as a key for data encryption and decryption operation;
the data encryption and decryption unit at least comprises an encryption processing unit, a decryption processing unit and a key storage unit, and the encryption processing unit is used for executing data encryption operation; the decryption processing unit is used for executing data decryption operation; the key storage unit is used for storing a key;
the memory is provided with an encryption storage unit and a decryption storage unit, wherein the encryption storage unit and the decryption storage unit are respectively provided with a plurality of storage units which are respectively used for storing data after encryption operation or decryption operation is executed;
the control unit is connected with the data encryption and decryption unit and the memory and is used for acquiring the instruction sent by the host computer, analyzing the instruction and executing corresponding processing;
when the obtained instruction is a write instruction and the write address is an encryption storage unit, the control unit sends the task to be processed to the data encryption and decryption unit, and the task to be processed is directly stored in the corresponding storage unit after being encrypted by the encryption processing unit; when the obtained instruction is a write instruction and the write address is a decryption storage unit, the control unit sends the task to be processed to the data encryption and decryption unit, and the task to be processed is directly stored in the corresponding storage unit after being decrypted by the decryption processing unit; simultaneously, the control unit feeds back a task completion message to the host, wherein the feedback task completion message at least comprises the address information of the storage unit corresponding to the task;
and when the acquired instruction is a read instruction, the control unit acquires the address information in the instruction, reads the data information of the storage unit corresponding to the address and sends the data information to the host.
2. The encryption card according to claim 1, wherein the encryption card is provided with a plurality of encryption/decryption engines, each encryption/decryption engine being provided with a unique identification number.
3. The encryption card according to claim 1 or 2, wherein the encryption/decryption engine further comprises an algorithm storage unit, connected to the control unit and the data encryption/decryption unit, for storing an algorithm for data encryption/decryption; and the data encryption and decryption unit selects a corresponding encryption algorithm according to the control instruction of the control unit.
4. The encryption card according to claim 1 or 2, further comprising a buffer unit connected to the control unit for buffering data.
5. The encryption card of claim 1 or 2, wherein the memory is implemented by a plurality of eMMC chips, and the plurality of eMMC chips are cascaded through a bus.
6. The encryption card according to claim 1 or 2, wherein when the control unit performs a write operation, it selects a free memory location and sends its address information to the data encryption/decryption unit together with the task to be processed; and the data encryption and decryption unit directly stores the processed tasks into the storage unit after executing encryption and decryption operations.
7. The encryption card according to claim 1 or 2, wherein the control unit sets an engine status table for recording the status of each encryption/decryption engine and dynamically updated for the control unit to assign the tasks to be processed.
8. The encryption card according to claim 1 or 2, wherein the control unit sets a memory map for recording an address of each task and its corresponding memory unit.
9. The encryption card according to claim 8, wherein the memory mapping table further sets a storage flag bit for identifying the read/write status of the data in the storage unit, and the data in the storage unit is read out to release the storage space for the subsequent write operation.
10. The encryption card according to claim 1 or 2, wherein the slave interface or the host interface adopts any one of an SD interface, a USB interface or a SATA interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810850456.5A CN110765468A (en) | 2018-07-28 | 2018-07-28 | Encryption card |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810850456.5A CN110765468A (en) | 2018-07-28 | 2018-07-28 | Encryption card |
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| CN110765468A true CN110765468A (en) | 2020-02-07 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112713993A (en) * | 2020-12-24 | 2021-04-27 | 天津国芯科技有限公司 | Encryption algorithm module accelerator and high-speed data encryption method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112713993A (en) * | 2020-12-24 | 2021-04-27 | 天津国芯科技有限公司 | Encryption algorithm module accelerator and high-speed data encryption method |
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Application publication date: 20200207 |