CN110764605B - Multi-core processor control method and device, electronic equipment and storage medium - Google Patents
Multi-core processor control method and device, electronic equipment and storage medium Download PDFInfo
- Publication number
- CN110764605B CN110764605B CN201911044356.4A CN201911044356A CN110764605B CN 110764605 B CN110764605 B CN 110764605B CN 201911044356 A CN201911044356 A CN 201911044356A CN 110764605 B CN110764605 B CN 110764605B
- Authority
- CN
- China
- Prior art keywords
- cores
- core
- temperature
- processor
- switching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3293—Power saving characterised by the action undertaken by switching to a less power-consuming processor, e.g. sub-CPU
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/16—Constructional details or arrangements
- G06F1/20—Cooling means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Human Computer Interaction (AREA)
- Power Sources (AREA)
Abstract
The application provides a multi-core processor control method, a multi-core processor control device, electronic equipment and a computer storage medium, wherein when the number of first cores of a multi-core processor of the electronic equipment is smaller than the total number of cores of the multi-core processor, a first temperature of each first core and a second temperature of each second core are obtained, the multi-core processor at least comprises two cores, the first cores are cores in a working state, and the second cores are cores in an idle state; determining a third core according to the first temperature, wherein the third core is a core in an overheat state; and switching at least one second core into a working state according to the second temperature, and switching at least one third core into an idle state. The processor cores are dynamically switched based on the temperature of the processor cores, so that the cores of the processor in the working state are always the cores with lower temperature, the performance of the multi-core processor is not required to be reduced, and the power consumption is reduced.
Description
Technical Field
The present application relates to the field of processor control technologies, and in particular, to a method and an apparatus for controlling a multi-core processor, an electronic device, and a computer storage medium.
Background
Along with the development of the society, the use of intelligent equipment is more and more popular, in order to improve the performance of the intelligent equipment, a multi-core processor is often installed on the intelligent equipment, but because the heat dissipation efficiency of the intelligent equipment is limited, the situation that the temperature of certain cores in the multi-core processor is too high often occurs, the existing solution is generally that software isolation is adopted, namely some software isolation enables no task on the multi-core processor to run and enter a low power consumption mode, so that the temperature is reduced, but the mode can limit the performance of the multi-core processor, and the user experience is greatly reduced.
Disclosure of Invention
Based on the above problems, the present application provides a method and an apparatus for controlling a multi-core processor, an electronic device, and a computer storage medium, which can reduce power consumption without reducing the performance of the multi-core processor.
A first aspect of an embodiment of the present application provides a method for controlling a multi-core processor, which is applied to an electronic device, and the method includes:
when the number of first cores of a multi-core processor of the electronic equipment is smaller than the total number of cores of the multi-core processor, acquiring a first temperature of each first core and a second temperature of each second core, wherein the multi-core processor at least comprises two cores, the first cores are cores in a working state, and the second cores are cores in an idle state;
determining a third core according to the first temperature, wherein the third core is a core in an overheat state;
and switching at least one second core into a working state according to the second temperature, and switching at least one third core into an idle state.
A second aspect of embodiments of the present application provides a multicore processor control apparatus, including a processing unit and a communication unit, wherein,
the processing unit is used for acquiring a first temperature of each first core and a second temperature of each second core except the first cores when the number of the first cores of the multi-core processor of the electronic equipment is smaller than the total number of the cores of the multi-core processor, wherein the multi-core processor at least comprises two cores, the first cores are cores in a working state, and the second cores are cores in an idle state;
determining a third core according to the first temperature, wherein the third core is a core in an overheat state;
and switching at least one second core into a working state according to the second temperature, and switching at least one third core into an idle state.
A third aspect of the embodiments of the present application provides an electronic device, including a multi-core processor, a communication interface, and a memory, where the multi-core processor, the communication interface, and the memory are connected to each other, where the memory is used to store a computer program, and the computer program includes program instructions, and the multi-core processor is configured to call the program instructions to execute the method described in any step of the first aspect of the embodiments of the present application.
A fourth aspect of embodiments of the present application provides a computer storage medium storing a computer program, the computer program comprising program instructions that, when executed by a processor, cause the processor to perform the method as described in any one of the steps of the first aspect of embodiments of the present application.
A fifth aspect of embodiments of the present application provides a computer program product, wherein the computer program product comprises a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to perform some or all of the steps as described in any one of the methods of the first aspect of embodiments of the present application. The computer program product may be a software installation package.
By implementing the embodiment of the application, the following beneficial effects can be obtained:
according to the multi-core processor control method, the multi-core processor control device, the electronic equipment and the computer storage medium, when the number of first cores of a multi-core processor of the electronic equipment is smaller than the total number of cores of the multi-core processor, the first temperature of each first core and the second temperature of each second core are obtained, the multi-core processor at least comprises two cores, the first cores are cores in a working state, and the second cores are cores in an idle state; determining a third core according to the first temperature, wherein the third core is a core in an overheat state; and switching at least one second core into a working state according to the second temperature, and switching at least one third core into an idle state. The processor cores are dynamically switched based on the temperature of the processor cores, so that the cores of the processor in the working state are always the cores with lower temperature, the performance of the multi-core processor is not required to be reduced, and the power consumption is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a system architecture diagram of a multi-core processor control method provided in an embodiment of the present application;
fig. 2 is an application scenario diagram of a multi-core processor control method according to an embodiment of the present application;
fig. 3 is a schematic flowchart of a method for controlling a multi-core processor according to an embodiment of the present disclosure;
fig. 4 is a schematic flowchart of another method for controlling a multi-core processor according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure;
fig. 6 is a block diagram of structural units of a multi-core processor control device according to an embodiment of the present application.
Detailed Description
In order to make the technical solutions of the present application better understood, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first," "second," and the like in the description and claims of the present application and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
The electronic device according to the embodiments of the present application may be an electronic device with communication capability, and the electronic device may include various handheld devices with wireless communication function, vehicle-mounted devices, wearable devices, computing devices or other processing devices connected to a wireless modem, and various forms of User Equipment (UE), Mobile Stations (MS), terminal devices (terminal device), and so on.
The following describes embodiments of the present application in detail.
Fig. 1 is a system architecture diagram of a multi-core processor control method provided in an embodiment of the present application, including a plurality of cores 110, temperature sensors 120, and a core switching unit 130, where the cores 110 include at least one core 110 in an operating state and at least one core 110 in an idle state, the cores 110 may be integrated on the multi-core processor, each core 110 may be provided with at least one temperature sensor 120, the temperature sensors 120 are connected to the core switching unit 130, and the core switching unit 130 may perform a start-up or shut-down operation on the cores 110 according to temperature information received from the temperature sensors 120, so as to flexibly switch the cores 110 between the operating state and the idle state.
Through the system architecture, the processor cores can be dynamically switched based on the temperature of the processor cores to reduce the temperature of the processor cores, the performance of a multi-core processor is not required to be reduced, and the power consumption is reduced while the use experience of a user is greatly improved.
To more clearly illustrate the System architecture, an application scenario of the multi-core processor control method in the embodiment of the present application is described in detail below with reference to fig. 2, where fig. 2 is an application scenario diagram of a multi-core processor control method provided in the embodiment of the present application, and the multi-core processor control method includes a System-on-a-Chip (SoC) Chip, where the SoC Chip includes a plurality of cores, each of the cores is integrated with at least one temperature sensor, and the temperature sensor may be internally provided with a periodic timer to periodically and asynchronously obtain a temperature of each core, and when a temperature of a core in an operating state is too high, the core with an excessively high temperature is turned off, and the core with a lower temperature in an idle state is used to replace the core with an excessively high temperature, so that the temperature of the processor core can be dynamically switched based on the temperature of the processor core to lower the temperature of the processor core, the performance of the multi-core processor is not required to be reduced, and the power consumption is reduced while the use experience of a user is greatly improved.
A multi-core processing method in the embodiment of the present application is described in detail below with reference to fig. 3, where fig. 3 is a schematic flow diagram of a control method for a multi-core processor provided in the embodiment of the present application, and specifically includes the following steps:
When the number of the first cores of the multi-core processor of the electronic device is smaller than the total number of the cores of the multi-core processor, step 301 is executed, where the first cores are cores in a working state, and the second cores are cores in an idle state.
Wherein the first temperature and the second temperature may be asynchronously obtained by at least one temperature sensor provided on each core of the multi-core processor.
It should be noted that, a temperature difference meeting the temperature difference threshold needs to exist between the first temperature and the second temperature in the embodiment of the present application, for example, the temperature difference threshold may be set to 5 degrees celsius, if the obtained temperature difference between the first temperature and the second temperature is greater than or equal to 5 degrees celsius, the subsequent steps may be continuously performed, if the obtained temperature difference between the first temperature and the second temperature is less than 5 degrees celsius, at this time, the working state and the idle state are switched without practical beneficial effects, the number of cores in the working state needs to be increased to reduce the temperature, which does not belong to the scope of the embodiment of the present application, and details are not repeated here. In addition, the temperature difference threshold may be flexibly changed according to a scene, and the above examples do not limit the present application.
Optionally, the temperature sensor may be provided with a built-in periodic timer, for example, the first temperature and the second temperature are obtained every 5 seconds, and since the temperature of the core of the multi-core processor does not change suddenly, the first temperature and the second temperature are obtained periodically, which may save power consumption.
It should be noted that, the third core is a core in an overheat state, and the first core is a core in an operating state, and the operating state may include a normal operating state, an overheat state, and the like, so that the third core is actually screened from the first core, and the screening step may be as follows:
firstly, whether the first temperature is greater than a preset temperature threshold value or not can be judged, and if the first temperature is greater than the preset temperature threshold value, a first duration that the first temperature is greater than the preset temperature threshold value is obtained; then, it may be determined whether the first duration is greater than or equal to a predetermined time threshold, and if the first duration is greater than or equal to the predetermined time threshold, the third core is determined.
Specifically, the first temperature may include temperature data of a plurality of first cores, the first time period may also include a plurality of time period data in which the first temperature exceeds the preset temperature threshold, and when the temperature of any one of the first cores is greater than the preset temperature threshold and the time period is greater than the preset time threshold, the first core may be determined to be a third core, that is, a core in an overheat state.
Optionally, after determining whether the first duration is greater than or equal to a preset time threshold, if the first duration is less than the preset time threshold, the step of obtaining the first temperature is executed again.
The third core is determined according to the first temperature, so that an accurate core in an overheat state can be obtained, preparation is made for switching of subsequent cores, the use experience of a user is improved, power consumption is reduced, whether the working state of the core is switched or not is judged by setting the running time threshold of the processor core, the performance loss of the memory caused by frequently switching the state of the core in a short time can be avoided, and the working efficiency of the core is improved.
Wherein, the number N of the second cores and the number M of the third cores are obtained, and the N, M is a positive integer, and then, whether the number N of the second cores is greater than or equal to the number M of the third cores is determined, and at this time, two switching paths exist,
if the number N of the second cores is greater than or equal to the number M of the third cores, the second core is a first switching path, and since the number of the second cores is greater, in the first switching path, all the third cores may be switched to an idle state, and the second cores corresponding to all the third cores may be switched to an operating state, specifically, the second core switching priority may be determined according to the ascending order of the second temperature, and the M second cores may be switched to the operating state according to the second core switching priority, and the M third cores may be switched to the idle state. For example, if there are two second cores with temperatures of 20 degrees celsius and 30 degrees celsius respectively, and there is only one third core with a temperature of 90 degrees celsius, then the two second cores may be arranged in ascending order according to the second temperature, the second core with a temperature of 20 degrees celsius is arranged at the first priority, the second core with a temperature of 30 degrees celsius is arranged at the second priority, and at this time, the third core with a temperature of 90 degrees celsius needs to be switched to the idle state, and the second core with a temperature of 20 degrees celsius of the first priority is selected to replace the third core to continue working;
if the number N of the second cores is smaller than the number M of the third cores, the second switching path is used, and because the number of the second cores is smaller, all the cores in the overheat state, that is, the third cores cannot be switched to the idle state, only the third cores having the same number as the second cores are selected to enter the idle state, and all the second cores are switched to the working state. For example, if there are three third cores with a temperature of 90 degrees celsius, 95 degrees celsius, and 98 degrees celsius, respectively, and there is only one second core with a temperature of 30 degrees celsius, then the third core switching priorities are ordered as: the third core at 98 degrees celsius, the third core at 95 degrees celsius, and the third core at 90 degrees celsius, at this time, the third core at 98 degrees celsius may be switched to an idle state, and the second core may be switched to a working state to replace the third core at 98 degrees celsius to continue working.
Optionally, in the second switching path, because the third core still continues to operate, in order to avoid a further increase in the temperature of the third core that continues to operate, the frequency of the third core that continues to operate may be reduced, and the frequency of the second core that has just been switched to an operating state may be increased, so that the temperature differences between the multiple cores may be balanced, and the temperature of the cores may be reduced as much as possible without changing the performance of the multi-core processor.
Optionally, if the number N of the second cores is smaller than the number M of the third cores after determining whether the number N of the second cores is greater than or equal to the number M of the third cores, the step of obtaining the first temperature is continuously performed.
By the method, the processor cores can be dynamically switched based on the temperature of the processor cores to reduce the temperature of the processor cores, the performance of the multi-core processor is not required to be reduced, and the power consumption is reduced while the use experience of a user is greatly improved.
Next, a detailed description is given to another multi-core processor control method in the embodiment of the present application with reference to fig. 4, where fig. 4 is a schematic flow diagram of another multi-core processor control method provided in the embodiment of the present application, and the method specifically includes the following steps:
The initial temperature is a plurality of groups of data, including the temperature of each core, when the multi-core processor needs to work, the initial temperature of each core of the multi-core processor can be obtained through the thermistor or the temperature sensor, and therefore preparation can be made for subsequently selecting the first core and the second core.
The priority of the operating cores can be determined according to the ascending order of the initial temperature, the highest priority of the operating cores is determined as the first core, and the rest are determined as the second core.
By determining the first core and the second core according to the initial temperature, which cores are operated and which cores are idle can be selected according to the temperature when the multi-core processor is started, and the power consumption is reduced while the performance is not reduced.
The steps not described in detail above can be referred to the method described in fig. 3, and are not described again here.
Through the steps, the processor cores can be dynamically switched based on the temperature of the processor cores to reduce the temperature of the processor cores, the performance of a multi-core processor is not required to be reduced, and the power consumption is reduced while the use experience of a user is greatly improved.
Referring to fig. 5 in accordance with the embodiment shown in fig. 3 and fig. 4, fig. 5 is a schematic structural diagram of an electronic device 500 provided in the embodiment of the present application, as shown in the figure, the electronic device 500 includes an application processor 501, a communication interface 502, and a memory 503, where the application processor 501, the communication interface 502, and the memory 503 are connected to each other through a bus 504, and the bus 504 may be a Peripheral Component Interconnect Standard (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus 504 may be divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one thick line is shown in FIG. 5, but this is not intended to represent only one bus or type of bus. Wherein the memory is for storing a computer program comprising program instructions, the application processor being configured for invoking the program instructions, performing the method of:
when the number of first cores of a multi-core processor of the electronic equipment is smaller than the total number of cores of the multi-core processor, acquiring a first temperature of each first core and a second temperature of each second core, wherein the multi-core processor at least comprises two cores, the first cores are cores in a working state, and the second cores are cores in an idle state;
determining a third core according to the first temperature, wherein the third core is a core in an overheat state;
and switching at least one second core into a working state according to the second temperature, and switching at least one third core into an idle state.
In one possible example, in the obtaining the first temperature of each first core and the second temperature of each second core other than the first core, the instructions in the program are specifically configured to: asynchronously acquiring the first temperature and the second temperature through at least one temperature sensor arranged on each core of the multi-core processor.
In one possible example, in the determining a third core based on the first temperature, the instructions in the program are specifically configured to: judging whether the first temperature is greater than a preset temperature threshold value or not;
if so, acquiring a first time length for which the first temperature is greater than the preset temperature threshold;
judging whether the first time length is greater than or equal to a preset time threshold value or not;
and if the first duration is greater than or equal to a preset time threshold, determining the third core.
In one possible example, in terms of switching at least one of the second cores to the operating state and at least one of the third cores to the idle state according to the second temperature, the instructions in the program are specifically configured to perform the following operations: acquiring the number N of the second cores and the number M of the third cores, wherein N, M is a positive integer;
judging whether the number N of the second cores is larger than or equal to the number M of the third cores;
if the number N of the second cores is greater than or equal to the number M of the third cores, determining a second core switching priority according to the ascending order of the second temperature;
and switching the M second cores into a working state and switching the M third cores into an idle state according to the second core switching priority.
In one possible example, after the determining whether the number N of second cores is greater than or equal to the number M of third cores, the instructions in the program are further specifically configured to: if the number N of the second cores is smaller than the number M of the third cores, determining a third core switching priority according to the descending order of the first temperature;
and switching the N third cores into an idle state and switching the N second cores into a working state according to the third core switching priority.
In one possible example, after the determining whether the first temperature is greater than the preset temperature threshold or after the determining whether the first time duration is greater than or equal to the preset time threshold, the instructions in the program are further specifically configured to: if the first temperature is not greater than a preset temperature threshold or the first time length is less than a preset time threshold, continuing to execute the step of obtaining the first temperature.
In one possible example, in a preceding aspect of the obtaining the first temperature of each first core and the second temperature of each second core other than the first core, the instructions in the program are further specifically configured to: acquiring the initial temperature of each core of a multi-core processor of the electronic equipment;
determining the first core and the second core according to the initial temperature.
The above description has introduced the solution of the embodiment of the present application mainly from the perspective of the method-side implementation process. It is understood that the electronic device comprises corresponding hardware structures and/or software modules for performing the respective functions in order to realize the above-mentioned functions. Those of skill in the art will readily appreciate that the present application is capable of hardware or a combination of hardware and computer software implementing the various illustrative elements and algorithm steps described in connection with the embodiments provided herein. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiment of the present application, the electronic device may be divided into the functional units according to the method example, for example, each functional unit may be divided corresponding to each function, or two or more functions may be integrated into one processing unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit. It should be noted that the division of the unit in the embodiment of the present application is schematic, and is only a logic function division, and there may be another division manner in actual implementation.
Fig. 6 is a block diagram of structural units of a multicore processor control apparatus 600 according to an embodiment of the present application. The multi-core processor control device 600 is applied to an electronic device, and comprises a processing unit 601, a communication unit 602 and a storage unit 603, wherein the processing unit 601 is used for executing any step in the method embodiments, and when data transmission such as transmission is executed, the communication unit 602 is optionally called to complete corresponding operation. The details will be described below.
The processing unit 601 is configured to obtain a first temperature of each first core and a second temperature of each second core when the number of first cores of a multi-core processor of the electronic device is smaller than the total number of cores of the multi-core processor, where the multi-core processor includes at least two cores, the first core is a core in a working state, and the second core is a core in an idle state;
determining a third core according to the first temperature, wherein the third core is a core in an overheat state;
and switching at least one second core into a working state according to the second temperature, and switching at least one third core into an idle state.
In one possible example, in terms of the obtaining the first temperature of each first core and the second temperature of each second core except the first core, the processing unit 601 is specifically configured to: asynchronously acquiring the first temperature and the second temperature through at least one temperature sensor arranged on each core of the multi-core processor.
In one possible example, in the aspect of determining the third core according to the first temperature, the processing unit 601 is specifically configured to: judging whether the first temperature is greater than a preset temperature threshold value or not;
if so, acquiring a first time length for which the first temperature is greater than the preset temperature threshold;
judging whether the first time length is greater than or equal to a preset time threshold value or not;
and if the first duration is greater than or equal to a preset time threshold, determining the third core.
In a possible example, in terms of switching at least one of the second cores to the working state and at least one of the third cores to the idle state according to the second temperature, the processing unit 601 is specifically configured to: acquiring the number N of the second cores and the number M of the third cores, wherein N, M is a positive integer;
judging whether the number N of the second cores is larger than or equal to the number M of the third cores;
if the number N of the second cores is greater than or equal to the number M of the third cores, determining a second core switching priority according to the ascending order of the second temperature;
and switching the M second cores into a working state and switching the M third cores into an idle state according to the second core switching priority.
In a possible example, after the determining whether the number N of second cores is greater than or equal to the number M of third cores, the processing unit 601 is specifically further configured to: if the number N of the second cores is smaller than the number M of the third cores, determining a third core switching priority according to the descending order of the first temperature;
and switching the N third cores into an idle state and switching the N second cores into a working state according to the third core switching priority.
In a possible example, after the determining whether the first temperature is greater than a preset temperature threshold, or after the determining whether the first time duration is greater than or equal to a preset time threshold, the processing unit 601 is further specifically configured to: if the first temperature is not greater than a preset temperature threshold or the first time length is less than a preset time threshold, continuing to execute the step of obtaining the first temperature.
In one possible example, in terms of the obtaining of the first temperature of each first core and the second temperature of each second core except the first core, the processing unit 601 is further specifically configured to: acquiring the initial temperature of each core of a multi-core processor of the electronic equipment;
determining the first core and the second core according to the initial temperature.
Embodiments of the present application also provide a computer storage medium, where the computer storage medium stores a computer program for electronic data exchange, the computer program enabling a computer to execute part or all of the steps of any one of the methods described in the above method embodiments, and the computer includes an electronic device.
Embodiments of the present application also provide a computer program product comprising a non-transitory computer readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any of the methods as described in the above method embodiments. The computer program product may be a software installation package, the computer comprising an electronic device.
It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required in this application.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the above-described division of the units is only one type of division of logical functions, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices or units, and may be an electric or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit may be stored in a computer readable memory if it is implemented in the form of a software functional unit and sold or used as a stand-alone product. Based on such understanding, the technical solution of the present application may be substantially implemented or a part of or all or part of the technical solution contributing to the prior art may be embodied in the form of a software product stored in a memory, and including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the above-mentioned method of the embodiments of the present application. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable memory, which may include: flash Memory disks, Read-only memories (ROMs), Random Access Memories (RAMs), magnetic or optical disks, and the like.
The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the above description of the embodiments is only provided to help understand the method and the core concept of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (7)
1. A multi-core processor control method is applied to electronic equipment and is characterized by comprising the following steps:
acquiring the initial temperature of each core of a multi-core processor of the electronic equipment;
determining a first core and a second core according to the initial temperature;
when the number of first cores of a multi-core processor of the electronic equipment is smaller than the total number of cores of the multi-core processor, acquiring a first temperature of each first core and a second temperature of each second core, wherein the multi-core processor at least comprises two cores, the first cores are cores in a working state, and the second cores are cores in an idle state; a temperature difference meeting a temperature difference threshold exists between the first temperature and the second temperature;
determining a third core according to the first temperature, wherein the third core is a core in an overheat state;
switching at least one of the second cores to an operating state and at least one of the third cores to an idle state according to the second temperature, including: obtaining the number N of the second cores and the number M of the third cores, where N, M is a positive integer, determining whether the number N of the second cores is greater than or equal to the number M of the third cores, determining a second core switching priority according to an ascending order of the second temperature if the number N of the second cores is greater than or equal to the number M of the third cores, switching the M second cores to an operating state according to the second core switching priority, switching the M third cores to an idle state, determining a third core switching priority according to a descending order of the first temperature if the number N of the second cores is less than the number M of the third cores, switching the N third cores to an idle state according to the third core switching priority, switching the N second cores to an operating state, and increasing the operating frequencies of the N second cores switched to the operating state, reducing the operating frequency of (M-N) of the third cores that are in an over-temperature condition.
2. The method of claim 1, wherein the obtaining the first temperature of each first core and the second temperature of each second core other than the first core comprises:
asynchronously acquiring the first temperature and the second temperature through at least one temperature sensor arranged on each core of the multi-core processor.
3. The method of claim 1, wherein determining a third core as a function of the first temperature comprises:
judging whether the first temperature is greater than a preset temperature threshold value or not;
if so, acquiring a first time length for which the first temperature is greater than the preset temperature threshold;
judging whether the first time length is greater than or equal to a preset time threshold value or not;
and if the first duration is greater than or equal to a preset time threshold, determining the third core.
4. The method of claim 3, wherein after determining whether the first temperature is greater than a preset temperature threshold, or after determining whether the first duration is greater than or equal to a preset time threshold, the method further comprises:
if the first temperature is not greater than a preset temperature threshold or the first time length is less than a preset time threshold, continuing to execute the step of obtaining the first temperature.
5. A multicore processor control apparatus, comprising a processing unit and a communication unit, wherein,
the processing unit is used for acquiring the initial temperature of each core of a multi-core processor of the electronic equipment, determining a first core and a second core according to the initial temperature, and acquiring the first temperature of each first core and the second temperature of each second core except the first cores when the number of the first cores of the multi-core processor of the electronic equipment is smaller than the total number of the cores of the multi-core processor, wherein the multi-core processor at least comprises two cores, the first cores are cores in a working state, and the second cores are cores in an idle state; a temperature difference meeting a temperature difference threshold exists between the first temperature and the second temperature;
determining a third core according to the first temperature, wherein the third core is a core in an overheat state;
switching at least one second core into a working state according to the second temperature, and switching at least one third core into an idle state;
the processing unit is specifically configured to obtain the number N of the second cores and the number M of the third cores, where N, M is a positive integer, determine whether the number N of the second cores is greater than or equal to the number M of the third cores, determine a second core switching priority according to an ascending order of the second temperature if the number N of the second cores is greater than or equal to the number M of the third cores, switch the M second cores to an operating state according to the second core switching priority, switch the M third cores to an idle state, determine a third core switching priority according to a descending order of the first temperature if the number N of the second cores is less than the number M of the third cores, switch the N third cores to an idle state according to the third core switching priority, and switch the N second cores to an operating state, and increasing the operating frequencies of the N second cores switched to the operating state, and decreasing the operating frequencies of (M-N) third cores in the overheat state.
6. An electronic device comprising a multi-core processor, a communication interface and a memory, the multi-core processor, the communication interface and the memory being interconnected, wherein the memory is configured to store a computer program comprising program instructions, the multi-core processor being configured to invoke the program instructions to perform the method of any of claims 1 to 4.
7. A computer storage medium, characterized in that the computer storage medium stores a computer program comprising program instructions which, when executed by a processor, cause the processor to carry out the method according to any one of claims 1 to 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911044356.4A CN110764605B (en) | 2019-10-30 | 2019-10-30 | Multi-core processor control method and device, electronic equipment and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911044356.4A CN110764605B (en) | 2019-10-30 | 2019-10-30 | Multi-core processor control method and device, electronic equipment and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110764605A CN110764605A (en) | 2020-02-07 |
| CN110764605B true CN110764605B (en) | 2021-11-02 |
Family
ID=69333096
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911044356.4A Active CN110764605B (en) | 2019-10-30 | 2019-10-30 | Multi-core processor control method and device, electronic equipment and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110764605B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112181124B (en) * | 2020-09-11 | 2023-09-01 | 华为技术有限公司 | Method for managing power consumption and related equipment |
| CN112579513B (en) * | 2020-12-08 | 2023-04-25 | 成都海光微电子技术有限公司 | Chip self-adaptive control circuit, method and system-level chip |
| CN113553176A (en) * | 2021-07-13 | 2021-10-26 | 北京比特大陆科技有限公司 | Core switching method of chip, electronic device and storage medium |
| CN114257549B (en) * | 2021-12-21 | 2023-01-10 | 北京锐安科技有限公司 | Flow forwarding method, device, equipment and storage medium |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1692326A (en) * | 2002-08-23 | 2005-11-02 | 英特尔公司 | Apparatus for thermal management of multiple core microprocessors |
| CN101114187A (en) * | 2006-07-26 | 2008-01-30 | 国际商业机器公司 | Method and apparatus for monitoring and controlling heat generation in a multi-core processor |
| CN104679586A (en) * | 2013-10-31 | 2015-06-03 | 三星电子株式会社 | Electronic systems including heterogeneous multi-core processors and method of operating same |
| CN106293914A (en) * | 2016-08-01 | 2017-01-04 | 深圳市金立通信设备有限公司 | A kind of method of task scheduling and terminal |
| CN106537285A (en) * | 2014-08-15 | 2017-03-22 | 英特尔公司 | Balanced control of processor temperature |
| CN106681453A (en) * | 2016-11-24 | 2017-05-17 | 电子科技大学 | Dynamic heat treatment method of high-performance multi-core microprocessor |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8402290B2 (en) * | 2008-10-31 | 2013-03-19 | Intel Corporation | Power management for multiple processor cores |
| US8601300B2 (en) * | 2011-09-21 | 2013-12-03 | Qualcomm Incorporated | System and method for managing thermal energy generation in a heterogeneous multi-core processor |
| KR101954668B1 (en) * | 2013-01-15 | 2019-06-12 | 삼성전자주식회사 | Method and apparatus for improving power efficiency in electronic device using heterogeneous multicore processor |
| US9582052B2 (en) * | 2014-10-30 | 2017-02-28 | Qualcomm Incorporated | Thermal mitigation of multi-core processor |
| CN107239348B (en) * | 2017-06-23 | 2020-05-15 | 厦门美图移动科技有限公司 | Multi-core processor scheduling method and device and mobile terminal |
| CN107390834A (en) * | 2017-06-30 | 2017-11-24 | 广东欧珀移动通信有限公司 | terminal device, temperature rise control method, control device and storage medium |
-
2019
- 2019-10-30 CN CN201911044356.4A patent/CN110764605B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1692326A (en) * | 2002-08-23 | 2005-11-02 | 英特尔公司 | Apparatus for thermal management of multiple core microprocessors |
| CN101114187A (en) * | 2006-07-26 | 2008-01-30 | 国际商业机器公司 | Method and apparatus for monitoring and controlling heat generation in a multi-core processor |
| CN104679586A (en) * | 2013-10-31 | 2015-06-03 | 三星电子株式会社 | Electronic systems including heterogeneous multi-core processors and method of operating same |
| CN106537285A (en) * | 2014-08-15 | 2017-03-22 | 英特尔公司 | Balanced control of processor temperature |
| CN106293914A (en) * | 2016-08-01 | 2017-01-04 | 深圳市金立通信设备有限公司 | A kind of method of task scheduling and terminal |
| CN106681453A (en) * | 2016-11-24 | 2017-05-17 | 电子科技大学 | Dynamic heat treatment method of high-performance multi-core microprocessor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110764605A (en) | 2020-02-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110764605B (en) | Multi-core processor control method and device, electronic equipment and storage medium | |
| CN108881012B (en) | Link aggregation method and related product | |
| CN108419281B (en) | Network switching method and device and communication terminal | |
| EP3544344B1 (en) | Method, user equipment and computer readable storage medium for switching the operation mode of a user equipment between carrier aggregation (ca) and non-ca operation modes | |
| CN108829510B (en) | Thread binding processing method and device | |
| CN103838353A (en) | Method and terminal for controlling processor operation | |
| CN110837456B (en) | Control method and device and electronic equipment | |
| CN109041255B (en) | Access method and UE | |
| US20160255614A1 (en) | Network Device, Terminal Device, and Voice Service Control Method | |
| CN113329436A (en) | Connection control method, terminal and storage medium | |
| CN105430726A (en) | Carrier aggregation (CA) function control method for communication terminal and communication terminal | |
| CN114208255A (en) | Communication method and apparatus, electronic apparatus, and computer-readable storage medium | |
| CN108595238B (en) | Display control method and device of application interface | |
| US9860175B2 (en) | Methods, systems, and computer program products for processing a packet | |
| CN107548019B (en) | Method and device for processing network beacon in wireless sensor network | |
| CN107708176A (en) | A kind of method for connecting network, network connection device and mobile terminal | |
| CN111237229B (en) | Method, device and equipment for controlling rotating speed of fan | |
| JP6661784B2 (en) | Information processing apparatus, control method for information processing apparatus, control program, and recording medium | |
| CN106507268A (en) | The method and device of dynamic authentication in a kind of mobile phone removal of home | |
| CN114788357A (en) | Method and apparatus for prioritized 5G NSA cell (re) selection | |
| CN112087775A (en) | Network control method and device | |
| CN108139960B (en) | Frequency modulation method, frequency modulation device and processing equipment of Central Processing Unit (CPU) | |
| CN112469057B (en) | gNB base station communication control method and device based on D2D reliability | |
| CN110213432A (en) | A kind of setting method of working frequency of chip, mobile terminal and storage medium | |
| CN115529095A (en) | Channel selection method, device, system and storage medium for radio frequency communication |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |