CN110752854B - Low-frequency communication front end framework - Google Patents
Low-frequency communication front end framework Download PDFInfo
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- CN110752854B CN110752854B CN201911013110.0A CN201911013110A CN110752854B CN 110752854 B CN110752854 B CN 110752854B CN 201911013110 A CN201911013110 A CN 201911013110A CN 110752854 B CN110752854 B CN 110752854B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
- H04B1/18—Input circuits, e.g. for coupling to an antenna or a transmission line
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- H—ELECTRICITY
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- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
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Abstract
The invention discloses a low-frequency communication front-end architecture, which comprises a frequency selection network and a low-noise amplifier with an open-loop structure, wherein the low-noise amplifier is connected with the frequency selection network, the output end of the low-noise amplifier is electrically connected with a low-pass error feedback circuit, and the output direct current bias point of the low-noise amplifier is stabilized through the low-pass error feedback circuit so as to enlarge the output dynamic range of the low-noise amplifier. The invention solves the problem that the receiving front end is difficult to have remote warning under low power consumption. The invention solves the problem that the warning dead zone occurs after the receiver approaches the transmitter.
Description
Technical Field
The invention relates to communication equipment, in particular to a low-frequency communication front-end architecture.
Background
In the prior art, low frequency communication devices have artificially specified a range within which a person or other animal can only move, beyond which a responsive alert or stimulus signal is required. To implement this application, it is necessary to wear a wearable device to a human or animal which will signal an alert to the wearer when approaching or crossing the boundary.
Conventional communication devices typically employ a simplex wireless communication device that includes both a transmitter and a receiver. Since the transmitter transmits at a fixed point, a fixed power supply can be used and there is no limit on power consumption. But since the receiver is on the wearer, a separate power supply is required. Unfortunately, the capacity of the independent power supply is generally small, and generally does not exceed 200mAh, and most applications only have 100mAh at most. In order to enable the receiver to operate for a longer time, to be convenient to wear and to be comfortable, it is required that the whole receiver can operate at a very low power consumption.
At present, some products are already on the market, but all have some disadvantages. For example, some products can detect a wider range, but are implemented under the premise of sacrificing power consumption, and the scheme is tested to reach about 1mA of receiving front end when working, that is, the standby time can not exceed 10 days even under the condition of 200 mAh. For another example, although the standby power consumption is only tens of uA, the SNR of the front end is low, and the boundary warning range is only about 1m, and when the wearer moves rapidly, the warning boundary is narrow or even no warning is issued.
Furthermore, in some products, due to non-linearity of the receive front-end, errors occur in the received encoded signal at large signals (when the receiver is close to the transmitter), resulting in dead zones in the receiver response when close to the transmitter.
Disclosure of Invention
Aiming at the defects in the prior art, the technical problem to be solved by the invention is to provide a low-frequency communication front-end architecture. The invention uses a brand-new framework, so that the receiving front end can work for a longer distance with lower standby power consumption, and the receiver has better anti-saturation characteristic and can not generate dead zone in the whole range close to the transmitter.
In order to solve the technical problem, the invention is realized by the following scheme: the invention discloses a low-frequency communication front-end architecture, which comprises a frequency selection network and a low-noise amplifier with an open-loop structure, wherein the low-noise amplifier is connected with the frequency selection network, the output end of the low-noise amplifier is electrically connected with a low-pass error feedback circuit, and the output direct current bias point of the low-noise amplifier is stabilized through the low-pass error feedback circuit so as to enlarge the output dynamic range of the low-noise amplifier.
Further, the low frequency communication front end architecture further includes:
the output buffer is electrically connected with the output end of the low-noise amplifier and is used for isolating the low-noise amplifier and a plurality of gain stage circuits of a post circuit so as to prevent the gain of the low-noise amplifier from being influenced by the post circuit;
a plurality of gain stage circuits connected in series, the first gain stage circuit being electrically connected to the output of the output buffer;
and the output shaping circuit is electrically connected with the gain stage circuit at the tail end, and the output end of the output shaping circuit outputs a digital output signal.
Further, the frequency-selecting network comprises an inductor L0 and a capacitor C0 which are connected in parallel, and the center frequency of the pass band is:
the inductor L0 and the capacitor C0 are connected in parallel and then are connected with the low noise amplifier;
the low noise amplifier comprises a P-channel transistor Q1, an N-channel transistor Q2, a P-channel transistor Q3, an N-channel transistor Q4 and a resistor R0;
after the inductor L0 and the capacitor C0 are connected in parallel, one end of the inductor L0 is connected with a source of an N-channel transistor Q2, the other end of the inductor L0 is connected with a source of an N-channel transistor Q4 and a VSS circuit, a gate of the N-channel transistor Q2 is connected with a gate of an N-channel transistor Q4, a resistor R0 is connected between a drain of the N-channel transistor Q2 and a drain of the P-channel transistor Q1, a drain of the N-channel transistor Q4 is connected with a drain of a P-channel transistor Q3, a gate of the P-channel transistor Q1 is connected with a gate of the P-channel transistor Q3, a source of the P-channel transistor Q1 is connected with a source of the P-channel transistor Q3 and connected to a VDD circuit, a gate and a drain of the N-channel transistor Q2 are connected, and a;
the low-pass error feedback circuit is electrically connected between a circuit node between the P-channel transistor Q1 and the gate of the P-channel transistor Q3 and a circuit node between the P-channel transistor Q3 and the drain of the N-channel transistor Q4, and the positive electrode of an amplifier A2 is also connected between the P-channel transistor Q3 and the drain of the N-channel transistor Q4;
and circuit nodes among the gain stage circuits are all electrically connected with an amplitude detector circuit for indicating the signal magnitude, and the amplitude detector circuit is a second amplifier.
Further, the low-pass error feedback circuit comprises an error amplifier a1, a capacitor C1 and a resistor R1, wherein one end of each of the resistor R1 and the capacitor C1 is connected to the positive terminal of the error amplifier a1, the other end of the resistor R1 is connected to a circuit node between the drain of the P-channel transistor Q3 and the drain of the N-channel transistor Q4, the other end of the capacitor C1 is grounded, the output terminal of the error amplifier a1 is connected to a circuit node between the gate of the P-channel transistor Q1 and the gate of the P-channel transistor Q3, and the negative terminal of the error amplifier a1 is grounded;
the resistor R1 and the capacitor C1 form a low-pass filter, the low-pass error feedback circuit and the P-channel transistor Q3 form a negative feedback circuit, and the low-noise amplifier outputs Vo1The direct current voltage and the reference voltage VrAnd the frequency transfer of the low-pass error feedback circuit and the low-noise amplifier is as follows:
with the transfer function, the circuit formed by the low-pass error feedback circuit and the low-noise amplifier is a bent filter, and the zero poles of the bent filter are respectively as follows:
when R is1＞＞1/(gm，A1N), the transfer function exhibits an elevated filter characteristic, so that the gain of the circuit is at a maximum and is a constant value when the operating frequency is higher than the pole:
Amax＝-9m，QxR1；
the buffer is a gain amplifier A2, the anode of the amplifier A2 is connected with the output end of the low noise amplifier, and the output end of the amplifier A2 is connected with a plurality of gain stage circuits which are connected in series;
the gain stage circuit comprises a first resistor, a second resistor, a first capacitor, a second capacitor and a first amplifier, one end of the first resistor is connected with the output end of the amplifier A2, the other end of the first resistor is connected with the first capacitor and the second capacitor respectively, the other end of the first capacitor is connected with the negative pole of the first amplifier and one end of the second resistor respectively, and the other end of the second resistor is connected with the output end of the first amplifier, the other end of the second capacitor, the negative pole end of the amplitude detector circuit and one end of the resistor of the next gain stage circuit.
Further, the frequency-selective network comprises an inductor L0 and a capacitor C0 which are connected in parallel;
the low noise amplifier comprises a P-channel transistor Q1, an N-channel transistor Q2, a P-channel transistor Q3, an N-channel transistor Q4 and a resistor R0;
after the inductor L0 and the capacitor C0 are connected in parallel, one end of the inductor L0 is connected to the source of an N-channel transistor Q2 and the VSS circuit, the other end of the inductor L is connected to the source of an N-channel transistor Q4, the gate of the N-channel transistor Q2 is connected to the gate of an N-channel transistor Q4, a resistor R0 is connected between the drain of the N-channel transistor Q2 and the drain of the P-channel transistor Q1, the drain of the N-channel transistor Q4 is connected to the drain of a P-channel transistor Q3, the gate of the P-channel transistor Q1 is connected to the gate of the P-channel transistor Q3, the source of the P-channel transistor Q1 and the source of the P-channel transistor Q3 are connected to the VDD circuit, the gate of the N-channel transistor Q2 and the drain of the P-channel transistor Q1 are.
Further, the frequency-selective network comprises an inductor L0 and a capacitor C0 which are connected in parallel;
the low noise amplifier comprises a P-channel transistor Q1, an N-channel transistor Q2, a P-channel transistor Q3, an N-channel transistor Q4 and a resistor R0;
after the inductor L0 and the capacitor C0 are connected in parallel, two ends of the inductor L0 are respectively connected to the gates of an N-channel transistor Q2 and an N-channel transistor Q4, the source of the N-channel transistor Q2 is connected to the source of the N-channel transistor Q4 and connected to a VSS circuit, a resistor R0 is connected between the drain of the N-channel transistor Q2 and the drain of the P-channel transistor Q1, the drain of the N-channel transistor Q4 is connected to the drain of a P-channel transistor Q3, the gate of the P-channel transistor Q1 is connected to the gate of the P-channel transistor Q3, the source of the P-channel transistor Q1 is connected to the source of the P-channel transistor Q3 and connected to the VDD circuit, the gate and the drain of the N-channel transistor Q2 are connected, and the gate of the P-channel transistor Q1 are.
Further, the frequency-selective network comprises an inductor L0 and a capacitor C0 which are connected in parallel;
the low noise amplifier comprises a P-channel transistor Q1, an N-channel transistor Q2, a P-channel transistor Q3, an N-channel transistor Q4, a resistor R10, a capacitor C10, a capacitor C11, a resistor R11 and a direct current power supply;
after the inductor L0 and the capacitor C0 are connected in parallel, one end of the inductor L0 is connected with the source of an N-channel transistor Q2 and a VSS circuit, the other end of the inductor L0 is connected with the source of an N-channel transistor Q4, a resistor R11 is connected between the grid of the N-channel transistor Q2 and the grid of the N-channel transistor Q4, a circuit node between the resistor R11 and the grid of the N-channel transistor Q4 is connected with a capacitor C11, the other end of the capacitor C11 is connected with the VSS circuit,
a diode is connected between the drain of the N-channel transistor Q2 and the drain of the P-channel transistor Q1, the positive electrode end of the diode is connected with the drain end of a P-channel transistor Q1, the drain of the N-channel transistor Q4 is connected with the drain of a P-channel transistor Q3, a resistor R10 is connected between the grid of the P-channel transistor Q1 and the grid of a P-channel transistor Q3, the source of the P-channel transistor Q1 is connected with the source of the P-channel transistor Q3 and connected to a VDD circuit, a capacitor C10 is connected to a circuit node between the resistor R10 and the grid of the P-channel transistor Q3, and the other end of the capacitor C10 is connected to the VDD circuit;
the gate and drain of the N-channel transistor Q2 are connected, and the gate and drain of the P-channel transistor Q1 are connected.
Further, the frequency-selective network comprises an inductor L0 and a capacitor C0 which are connected in parallel;
the inductor L0 and the capacitor C0 are connected in parallel and then are connected with the low noise amplifier;
the low noise amplifier comprises a P-channel transistor Q1, an N-channel transistor Q2, a P-channel transistor Q3, an N-channel transistor Q4, an N-channel transistor Q5 and a resistor R0;
after the inductor L0 and the capacitor C0 are connected in parallel, one end of the inductor L0 is connected with a source of an N-channel transistor Q2, the other end of the inductor L0 is connected with a source of an N-channel transistor Q4 and a VSS circuit, a gate of the N-channel transistor Q2 is connected with a gate of an N-channel transistor Q4, a resistor R0 is connected between a drain of the N-channel transistor Q2 and a drain of the P-channel transistor Q1, a drain of the N-channel transistor Q4 is connected with a drain of a P-channel transistor Q3, a gate of the P-channel transistor Q1 is connected with a gate of the P-channel transistor Q3, a source of the P-channel transistor Q1 is connected with a source of the P-channel transistor Q3 and connected to a VDD circuit, a gate and a drain of the N-channel transistor Q2 are connected, and;
the source electrode of the N-channel transistor Q5 is connected with a VSS circuit, the grid electrode of the N-channel transistor Q4 is connected with the drain electrode of the N-channel transistor Q4, the drain electrode of the N-channel transistor Q5 is connected with a load and a low-pass error feedback circuit, and the other end of the load is connected to a VDD circuit.
Further, the frequency-selective network comprises an inductor L0 and a capacitor C0 which are connected in parallel;
the low noise amplifier comprises a P-channel transistor Q1, an N-channel transistor Q2, a P-channel transistor Q3, an N-channel transistor Q4 and a resistor R0;
after the inductor L0 and the capacitor C0 are connected in parallel, one end of the inductor L0 is connected with a source of a P-channel transistor Q3 and a VSS circuit, the other end of the inductor L0 is connected with a source of a P-channel transistor Q1, a gate of the P-channel transistor Q1 is connected with a gate of a P-channel transistor Q3, a resistor R0 is connected between a drain of the P-channel transistor Q1 and a drain of the N-channel transistor Q2, a drain of the N-channel transistor Q4 is connected with a drain of the P-channel transistor Q3, a gate of the N-channel transistor Q2 is connected with a gate of the N-channel transistor Q4, a source of the N-channel transistor Q2 is connected with a source of the N-channel transistor Q4 and connected to the VDD circuit, a gate and a drain of the N-channel transistor Q2 are connected, and;
an output end of an error amplifier A1 on the low-pass error feedback circuit is connected to a circuit node between the grid of the N-channel transistor Q2 and the grid of the N-channel transistor Q4, a positive electrode end of the error amplifier A1 is connected with a capacitor C1 and a resistor R1, the other end of the capacitor C1 is grounded, and the other end of the resistor R1 is connected to a circuit node between the drain of the P-channel transistor Q3 and the drain of the N-channel transistor Q4.
Further, the P-channel transistor Q1, the N-channel transistor Q2, the P-channel transistor Q3, and the N-channel transistor Q4 can be replaced by a PNP transistor Q1, an NPN transistor Q2, a PNP transistor Q3, and an NPN transistor Q4, respectively.
Compared with the prior art, the invention has the beneficial effects that:
1. the problem that the receiving front end is difficult to have remote warning under low power consumption is solved.
2. The problem of the receiver appear warning dead zone after being close to the transmitter is solved.
Drawings
FIG. 1 is a schematic block diagram of the system architecture of the present invention.
FIG. 2 is a preferred embodiment of the system architecture of the present invention.
Fig. 3 shows another connection 1 of the lna and the frequency selective network according to the present invention.
Fig. 4 shows another connection 2 of the lna and the frequency selective network according to the present invention.
FIG. 5 shows a lower noise embodiment of the low noise amplifier and low pass error feedback circuit of the present invention.
FIG. 6 shows an embodiment of a two-stage low noise amplifier and low pass error feedback circuit according to the present invention.
Fig. 7 is a circuit diagram of the working principle of the low noise amplifier of the present invention under the condition of negative power supply.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, and thus the protection scope of the present invention is more clearly and clearly defined. It should be apparent that the described embodiments of the present invention are only some embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example 1: the concrete structure of the invention is as follows:
referring to fig. 1-2, the low frequency communication front end architecture of the present invention includes a frequency selective network, and further includes a low noise amplifier with an open loop structure, the low noise amplifier is connected to the frequency selective network, an output end of the low noise amplifier is electrically connected to a low pass error feedback circuit, and an output dc bias point of the low noise amplifier is stabilized by the low pass error feedback circuit to increase an output dynamic range of the low noise amplifier.
A preferred technical solution of this embodiment: the low frequency communication front end architecture of the present invention further comprises:
the output buffer is electrically connected with the output end of the low-noise amplifier and is used for isolating the low-noise amplifier and a plurality of gain stage circuits of a post circuit so as to prevent the gain of the low-noise amplifier from being influenced by the post circuit;
and the first gain stage circuit is electrically connected with the output end of the output buffer. (alternative: circuit nodes between gain stage circuits are all electrically connected with an amplitude detector circuit, and the amplitude detection circuit is a second amplifier).
And the output shaping circuit is electrically connected with the gain stage circuit at the tail end, and the output end of the output shaping circuit outputs a digital output signal.
A preferred technical solution of this embodiment: the frequency selection network comprises an inductor L0 and a capacitor C0 which are connected in parallel, and the center frequency of the passband is as follows:
the signal in this band enters the input of the noise amplifier, which in this example is the source terminal of an N-channel transistor Q2. The P-channel transistor Q1 and the N-channel transistor Q2 are diode-connected, so that the P-channel transistor Q1 and the N-channel transistor Q2 can be equivalent to a resistor much smaller than R0. Since the equivalent resistance of the N-channel transistor Q2 is much smaller than the sum of the equivalent resistances of the R0 and the P-channel transistor Q1, V can be known according to the resistance voltage division theoremi2Almost following ViVariation, Vi2The signal V is amplified by an N-channel transistor Q4 of an amplifier tubeo1To the output buffer of the subsequent stage. In addition to passing input signals, the N-channel transistor Q2 provides a dc bias voltage to the gate of the N-channel transistor Q4, and similarly the P-channel transistor Q1 also provides the gate of the P-channel transistor Q3, and the P-channel transistor Q3 and the N-channel transistor Q4 mirror the dc bias currents of the P-channel transistor Q1 and the P-channel transistor Q3, respectively, where the P-channel transistor Q1, the P-channel transistor Q3, the N-channel transistor Q2, and the N-channel transistor Q4 have the size (field effect transistor width to length ratio, bipolar transistor area, and the like) ratio of N and N is a number greater than 0. P-channel transistor Q3 as the negative current source for N-channel transistor Q4Since the dc resistance is very high, and the dc bias currents of the P-channel transistor Q3 and the N-channel transistor Q4 are not completely matched due to the manufacturing process problems, the output V is outputo1The DC bias voltage point can be directly sent to a power supply or a ground, and an amplified signal can be subjected to top cutting or bottom cutting or even cannot be amplified, so that a large number of harmonics are added while the signal is lost, and errors occur in a rear-stage circuit.
The inductor L0 and the capacitor C0 are connected in parallel and then are connected with the low noise amplifier;
the low noise amplifier comprises a P-channel transistor Q1, an N-channel transistor Q2, a P-channel transistor Q3, an N-channel transistor Q4 and a resistor R0;
after the inductor L0 and the capacitor C0 are connected in parallel, one end of the inductor L0 is connected with a source of an N-channel transistor Q2, the other end of the inductor L0 is connected with a source of an N-channel transistor Q4 and a VSS circuit, a gate of the N-channel transistor Q2 is connected with a gate of an N-channel transistor Q4, a resistor R0 is connected between a drain of the N-channel transistor Q2 and a drain of the P-channel transistor Q1, a drain of the N-channel transistor Q4 is connected with a drain of a P-channel transistor Q3, a gate of the P-channel transistor Q1 is connected with a gate of the P-channel transistor Q3, a source of the P-channel transistor Q1 and a source of the P-channel transistor Q3 are connected to a VDD circuit, a gate and a drain of the N-channel transistor Q2 are connected, and a gate and;
the low-pass error feedback circuit is electrically connected between a circuit node between the P-channel transistor Q1 and the gate of the P-channel transistor Q3 and a circuit node between the P-channel transistor Q3 and the drain of the N-channel transistor Q4, and the positive electrode of an amplifier a2 is also connected to a circuit node between the P-channel transistor Q3 and the drain of the N-channel transistor Q4.
A preferred technical solution of this embodiment: the low-pass error feedback circuit comprises an error amplifier A1, a capacitor C1 and a resistor R1, wherein one end of each of the resistor R1 and the capacitor C1 is connected to the positive electrode end of the error amplifier A1, the other end of the resistor R1 is connected to a circuit node between the drain electrode of the P-channel transistor Q3 and the drain electrode of the N-channel transistor Q4, the other end of the capacitor C1 is grounded, the output end of the error amplifier A1 is connected to a circuit node between the P-channel transistor Q1 and the gate electrode of the P-channel transistor Q3, and the negative electrode end of the error amplifier A1 is grounded.
A preferred technical solution of this embodiment: the resistor R1 and the capacitor C1 form a low-pass filter, the low-pass error feedback circuit and the P-channel transistor Q3 form a negative feedback circuit, and the low-noise amplifier outputs Vo1The direct current voltage and the reference voltage VrAre equal. In order to solve the above problems, a low-pass error feedback circuit is introduced, in this embodiment, the low-pass error feedback circuit is implemented by using a low-pass filter consisting of a resistor R1 and a capacitor C1 and an error amplifier A1, and since the low-pass error feedback circuit and a P-channel transistor Q3 form negative feedback according to the principle that the positive and negative input ends of an operational amplifier are virtual short, the output V of the low-noise amplifier is outputo1The direct current voltage and the reference voltage VrAnd thus stabilizes the output bias voltage. The transfer including the low-pass error feedback circuit and the low-noise amplifier can also be derived by derivation as:
with the transfer function, the circuit formed by the low-pass error feedback circuit and the low-noise amplifier is a bent filter, and the zero poles of the bent filter are respectively as follows:
when R is1＞＞1/(gm，A1N), the transfer function exhibits an elevated filter characteristic, so that the gain of the circuit is at a maximum and is a constant value when the operating frequency is higher than the pole:
Amax＝-9m，，Q4R1。
it can be seen that the gain of the circuit is only related to the transconductance of the N-channel transistor Q4 and the resistor R1 of the low pass filter, and when the dc bias current and the size of the N-channel transistor Q4 are determined, the required gain can be controlled by the resistor R1.
A preferred technical solution of this embodiment: the buffer is a gain amplifier A2, the anode of the amplifier A2 is connected with the output end of the low noise amplifier, and the output end of the amplifier A2 is connected with a plurality of gain stage circuits which are connected in series;
the gain stage circuit comprises a first resistor, a second resistor, a first capacitor, a second capacitor and a first amplifier, one end of the first resistor is connected with the output end of the amplifier A2, the other end of the first resistor is respectively connected with the first capacitor and the second capacitor, the other end of the first capacitor is respectively connected with the cathode of the first amplifier and one end of the second resistor, and the other end of the second resistor is connected with the output end of the first amplifier, the other end of the second capacitor, the cathode of the amplitude detector circuit and one end of the resistor of the next gain stage circuit;
and the amplitude detector circuit is a second amplifier which is electrically connected with the output end of the first amplifier.
The overall implementation of fig. 1, and the preferred embodiment of fig. 2. Fig. 2 shows bias voltages of the P-channel transistor Q1 and the N-channel transistor Q2 directly applied to gates of the P-channel transistor Q3 and the N-channel transistor Q4, fig. 5 shows an embodiment in which low-pass filtering is added to a bias output to suppress noise, and fig. 5 shows a feedback mode adopted by an even-numbered ultra-low noise amplifier, which is different from the feedback modes of odd-numbered stages in fig. 2 and 5. Specific implementation modes of the low noise amplifier and different connection relations with the frequency selection network are shown in fig. 2-4, embodiments of different input connection relations are shown in fig. 2 and fig. 5, different bias generation modes are shown, the implementation modes are not only field effect transistors, but also other amplifier tubes such as bipolar transistors can be used for realizing the structures.
In this embodiment, the output buffer is implemented by using a unity gain amplifier to isolate the front-stage output Vo1 and the rear-stage input Vo2, so that the rear-stage amplification stage does not affect the gain of the front-stage amplification stage, and the front-stage low-noise amplifier does not affect the passband characteristics of the rear-stage amplification stage. The signal is sent to the following gain stage after passing through the output buffer, and a band pass filter with gain is used as the gain stage in this embodiment. The use of band-limited amplifiers can effectively reduce noise, but the cost can increase as a result. In this embodiment, the gain stage 1 is a first-order active band-pass filter including a resistor R2, a capacitor C2, a resistor R3, a second capacitor (i.e., a capacitor C3), and an amplifier A3, and the structure of the gain stage n is similar to that of the first-order active band-pass filter.
In this embodiment, two hysteresis comparators are also provided to serve as an output shaping circuit and an amplitude detector, each hysteresis comparator is composed of a resistor R4, a resistor R5 and an amplifier a4, and the hysteresis comparator has a certain hysteresis window, so that when the signal output by the gain stage is small, the comparator does not output, and if the comparator has the shaped digital signal output, the output signal of the gain stage reaches the size of the hysteresis window. Therefore, the information on the distance can be indirectly obtained by whether the amplifier a4 or the amplifier a6 has an output. That is, the amplifier a4 and the amplifier a6 are very close to each other in terms of output, the amplifier a4 is not output, the amplifier a6 is medium in terms of output, and the amplifier a4 and the amplifier a6 are far from each other in terms of no output. By adding units such as a gain stage and a hysteresis comparator, more accurate distance information can be obtained.
Example 2:
fig. 3 shows another connection 1 of the low noise amplifier and the frequency selective network according to the present invention, as shown in fig. 3. The frequency-selecting network comprises an inductor L0 and a capacitor C0 which are connected in parallel;
the low noise amplifier comprises a P-channel transistor Q1, an N-channel transistor Q2, a P-channel transistor Q3, an N-channel transistor Q4 and a resistor R0;
after the inductor L0 and the capacitor C0 are connected in parallel, one end of the inductor L0 is connected to the source of an N-channel transistor Q2 and the VSS circuit, the other end of the inductor L0 is connected to the source of an N-channel transistor Q4, the gate of the N-channel transistor Q2 is connected to the gate of an N-channel transistor Q4, a resistor R0 is connected between the drain of the N-channel transistor Q2 and the drain of the P-channel transistor Q1, the drain of the N-channel transistor Q4 is connected to the drain of a P-channel transistor Q3, the gate of the P-channel transistor Q1 is connected to the gate of the P-channel transistor Q3, the source of the P-channel transistor Q1 is connected to the source of the P-channel transistor Q3 and connected to the VDD circuit, the gate and the drain of the N-channel transistor Q2 are connected, and the gate.
The connections of the latter circuit are the same as the latter circuit of fig. 2.
As in the embodiment of fig. 3, another method for selecting the input terminal of the lna is shown, in which one terminal of the frequency selective network is connected to the source terminal of the N-channel transistor Q4, or as in the embodiment of fig. 4, the frequency selective network is connected between the gates of the N-channel transistor Q2 and the N-channel transistor Q4, so that the input terminal of the frequency selective network and the lna can be selected in various ways.
Example 3:
fig. 4 shows another connection 2 of the lna and the frequency selective network according to the present invention, as shown in fig. 4.
The frequency-selecting network comprises an inductor L0 and a capacitor C0 which are connected in parallel;
the low noise amplifier comprises a P-channel transistor Q1, an N-channel transistor Q2, a P-channel transistor Q3, an N-channel transistor Q4 and a resistor R0;
after the inductor L0 and the capacitor C0 are connected in parallel, two ends of the inductor L0 are respectively connected to the gates of an N-channel transistor Q2 and an N-channel transistor Q4, the source of the N-channel transistor Q2 is connected to the source of the N-channel transistor Q4 and connected to a VSS circuit, a resistor R0 is connected between the drain of the N-channel transistor Q2 and the drain of the P-channel transistor Q1, the drain of the N-channel transistor Q4 is connected to the drain of a P-channel transistor Q3, the gate of the P-channel transistor Q1 is connected to the gate of the P-channel transistor Q3, the source of the P-channel transistor Q1 is connected to the source of the P-channel transistor Q3 and connected to the VDD circuit, the gate and the drain of the N-channel transistor Q2 are connected, and the gate of the P-channel transistor Q1 are.
The connections of the latter circuit are the same as the latter circuit of fig. 2.
Example 4:
FIG. 5 shows a lower noise embodiment of the low noise amplifier and low pass error feedback circuit of the present invention.
The frequency-selecting network comprises an inductor L0 and a capacitor C0 which are connected in parallel;
the low noise amplifier comprises a P-channel transistor Q1, an N-channel transistor Q2, a P-channel transistor Q3, an N-channel transistor Q4, a resistor R10, a capacitor C10, a capacitor C11, a resistor R11 and a direct current power supply;
after the inductor L0 and the capacitor C0 are connected in parallel, one end of the inductor L0 is connected with the source of an N-channel transistor Q2 and a VSS circuit, the other end of the inductor L0 is connected with the source of an N-channel transistor Q4, a resistor R11 is connected between the grid of the N-channel transistor Q2 and the grid of the N-channel transistor Q4, a circuit node between the resistor R11 and the grid of the N-channel transistor Q4 is connected with a capacitor C11, the other end of the capacitor C11 is connected with the VSS circuit,
a diode is connected between the drain of the N-channel transistor Q2 and the drain of the P-channel transistor Q1, the positive electrode end of the diode is connected with the drain end of a P-channel transistor Q1, the drain of the N-channel transistor Q4 is connected with the drain of a P-channel transistor Q3, a resistor R10 is connected between the grid of the P-channel transistor Q1 and the grid of a P-channel transistor Q3, the source of the P-channel transistor Q1 is connected with the source of the P-channel transistor Q3 and connected to a VDD circuit, a capacitor C10 is connected to a circuit node between the resistor R10 and the grid of the P-channel transistor Q3, and the other end of the capacitor C10 is connected to the VDD circuit;
the gate and drain of the N-channel transistor Q2 are connected, and the gate and drain of the P-channel transistor Q1 are connected.
Example 5:
FIG. 6 shows an embodiment of a two-stage low noise amplifier and low pass error feedback circuit according to the present invention.
The frequency-selective network comprises an inductor L0 and a capacitor C0 which are connected in parallel,
the inductor L0 and the capacitor C0 are connected in parallel and then are connected with the low noise amplifier;
the low noise amplifier comprises a P-channel transistor Q1, an N-channel transistor Q2, a P-channel transistor Q3, an N-channel transistor Q4, an N-channel transistor Q5 and a resistor R0;
after the inductor L0 and the capacitor C0 are connected in parallel, one end of the inductor L0 is connected with a source of an N-channel transistor Q2, the other end of the inductor L0 is connected with a source of an N-channel transistor Q4 and a VSS circuit, a gate of the N-channel transistor Q2 is connected with a gate of an N-channel transistor Q4, a resistor R0 is connected between a drain of the N-channel transistor Q2 and a drain of the P-channel transistor Q1, a drain of the N-channel transistor Q4 is connected with a drain of a P-channel transistor Q3, a gate of the P-channel transistor Q1 is connected with a gate of the P-channel transistor Q3, a source of the P-channel transistor Q1 is connected with a source of the P-channel transistor Q3 and connected to a VDD circuit, a gate and a drain of the N-channel transistor Q2 are connected, and;
the source electrode of the N-channel transistor Q5 is connected with a VSS circuit, the grid electrode of the N-channel transistor Q4 is connected with the drain electrode of the N-channel transistor Q4, the drain electrode of the N-channel transistor Q5 is connected with a load and a low-pass error feedback circuit, and the other end of the load is connected to a VDD circuit.
In the examples of fig. 2 to 6, the P-channel transistor Q1 and the N-channel transistor Q2 are transistors for generating bias voltages, respectively, and the bias voltages generated by the transistors can be generated by dividing voltages through the P-channel transistor Q1, the N-channel transistor Q2 and the resistor R0 as in fig. 2 to 4 and 6, or can be generated by generating voltage drops at the P-channel transistor Q1 and the N-channel transistor Q2 by using a current source as in fig. 5.
Besides, bias voltages generated by the P-channel transistor Q1 and the N-channel transistor Q2 are directly connected to the gates of the P-channel transistor Q3 and the N-channel transistor Q4, a low-pass filter composed of a resistor R10, a capacitor C10, a resistor R11 and a capacitor C11 can be added as shown in fig. 5, so that noise of the P-channel transistor Q1, the N-channel transistor Q2, the error amplifier a1 and the reference voltage Vr can be filtered out, and the signal-to-noise ratio of the low-noise amplifier is greatly improved.
In the example of fig. 6, in order to further improve the gain of the low noise amplifier, a two-stage structure may be adopted, but since the polarity of feedback changes, an integrator formed by connecting the resistor R1, the capacitor C1 and the error amplifier a1 in fig. 6 may be used as a low-pass error feedback circuit to achieve the purpose.
Example 6:
fig. 7 shows another wiring scheme of the present invention, and fig. 7 is a circuit diagram illustrating the operation principle of the low noise amplifier of the present invention in the case of negative power supply.
The frequency-selecting network comprises an inductor L0 and a capacitor C0 which are connected in parallel;
the low noise amplifier comprises a P-channel transistor Q1, an N-channel transistor Q2, a P-channel transistor Q3, an N-channel transistor Q4 and a resistor R0;
after the inductor L0 and the capacitor C0 are connected in parallel, one end of the inductor L0 is connected with a source of a P-channel transistor Q3 and a VSS circuit, the other end of the inductor L0 is connected with a source of a P-channel transistor Q1, a gate of the P-channel transistor Q1 is connected with a gate of a P-channel transistor Q3, a resistor R0 is connected between a drain of the P-channel transistor Q1 and a drain of the N-channel transistor Q2, a drain of the N-channel transistor Q4 is connected with a drain of the P-channel transistor Q3, a gate of the N-channel transistor Q2 is connected with a gate of the N-channel transistor Q4, a source of the N-channel transistor Q2 is connected with a source of the N-channel transistor Q4 and connected to the VDD circuit, a gate and a drain of the N-channel transistor Q2 are connected, and.
An output end of an error amplifier A1 on the low-pass error feedback circuit is connected to a circuit node between the grid of the N-channel transistor Q2 and the grid of the N-channel transistor Q4, a positive electrode end of the error amplifier A1 is connected with a capacitor C1 and a resistor R1, the other end of the capacitor C1 is grounded, and the other end of the resistor R1 is connected to a circuit node between the drain of the P-channel transistor Q3 and the drain of the N-channel transistor Q4.
The connections of the latter circuit are the same as the latter circuit of fig. 2.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (8)
1. A low-frequency communication front-end architecture comprises a frequency selection network and is characterized by also comprising a low-noise amplifier with an open-loop structure, wherein the low-noise amplifier is connected with the frequency selection network, the output end of the low-noise amplifier is electrically connected with a low-pass error feedback circuit, and the output direct current bias point of the low-noise amplifier is stabilized through the low-pass error feedback circuit so as to enlarge the output dynamic range of the low-noise amplifier;
the low frequency communication front end architecture further comprises:
the output buffer is electrically connected with the output end of the low-noise amplifier and is used for isolating the low-noise amplifier and a plurality of gain stage circuits of a post circuit so as to prevent the gain of the low-noise amplifier from being influenced by the post circuit;
a plurality of gain stage circuits connected in series, the first gain stage circuit being electrically connected to the output of the output buffer;
the output shaping circuit is electrically connected with the gain stage circuit at the tail end, and the output end of the output shaping circuit is a digital output signal;
the frequency selection network comprises an inductor L0 and a capacitor C0 which are connected in parallel, and the center frequency of the passband is as follows:
the inductor L0 and the capacitor C0 are connected in parallel and then are connected with the low noise amplifier;
the low noise amplifier comprises a P-channel transistor Q1, an N-channel transistor Q2, a P-channel transistor Q3, an N-channel transistor Q4 and a resistor R0;
after the inductor L0 and the capacitor C0 are connected in parallel, one end of the inductor L0 is connected with a source of an N-channel transistor Q2, the other end of the inductor L0 is connected with a source of an N-channel transistor Q4 and a VSS circuit, a gate of the N-channel transistor Q2 is connected with a gate of an N-channel transistor Q4, a resistor R0 is connected between a drain of the N-channel transistor Q2 and a drain of the P-channel transistor Q1, a drain of the N-channel transistor Q4 is connected with a drain of a P-channel transistor Q3, a gate of the P-channel transistor Q1 is connected with a gate of the P-channel transistor Q3, a source of the P-channel transistor Q1 and a source of the P-channel transistor Q3 are connected to a VDD circuit, a gate and a drain of the N-channel transistor Q2 are connected, and a gate and;
the low-pass error feedback circuit is electrically connected between a circuit node between the P-channel transistor Q1 and the gate of the P-channel transistor Q3 and a circuit node between the P-channel transistor Q3 and the drain of the N-channel transistor Q4, and the positive electrode of an amplifier A2 is also connected between the P-channel transistor Q3 and the drain of the N-channel transistor Q4;
and circuit nodes among the gain stage circuits are all electrically connected with an amplitude detector circuit for indicating the signal magnitude, and the amplitude detector circuit is a second amplifier.
2. The architecture of claim 1, wherein the low-pass error feedback circuit comprises an error amplifier a1, a capacitor C1 and a resistor R1, wherein one end of each of the resistor R1 and the capacitor C1 is connected to the positive terminal of the error amplifier a1, the other end of the resistor R1 is connected to a circuit node between the drain of the P-channel transistor Q3 and the drain of the N-channel transistor Q4, the other end of the capacitor C1 is grounded, the output terminal of the error amplifier a1 is connected to a circuit node between the gate of the P-channel transistor Q1 and the P-channel transistor Q3, and the negative terminal of the error amplifier a1 is grounded;
the resistor R1 and the capacitor C1 form a low-pass filter, the low-pass error feedback circuit and the P-channel transistor Q3 form a negative feedback circuit, and the low-noise amplifier outputs Vo1The direct current voltage and the reference voltage VrEquality, said low-pass error being inverseThe circuit formed by the feed circuit and the low noise amplifier is a bent frame type filter;
the output buffer is a gain amplifier A2, the anode of the amplifier A2 is connected with the output end of the low noise amplifier, and the output end of the amplifier A2 is connected with a plurality of gain stage circuits which are connected in series;
the gain stage circuit comprises a first resistor, a second resistor, a first capacitor, a second capacitor and a first amplifier, one end of the first resistor is connected with the output end of the amplifier A2, the other end of the first resistor is connected with the first capacitor and the second capacitor respectively, the other end of the first capacitor is connected with the negative pole of the first amplifier and one end of the second resistor respectively, and the other end of the second resistor is connected with the output end of the first amplifier, the other end of the second capacitor, the negative pole end of the amplitude detector circuit and one end of the resistor of the next gain stage circuit.
3. The architecture of claim 1, wherein the frequency-selective network comprises an inductor L0 and a capacitor C0 connected in parallel;
the low noise amplifier comprises a P-channel transistor Q1, an N-channel transistor Q2, a P-channel transistor Q3, an N-channel transistor Q4 and a resistor R0;
after the inductor L0 and the capacitor C0 are connected in parallel, one end of the inductor L0 is connected to the source of an N-channel transistor Q2 and the VSS circuit, the other end of the inductor L0 is connected to the source of an N-channel transistor Q4, the gate of the N-channel transistor Q2 is connected to the gate of an N-channel transistor Q4, a resistor R0 is connected between the drain of the N-channel transistor Q2 and the drain of the P-channel transistor Q1, the drain of the N-channel transistor Q4 is connected to the drain of a P-channel transistor Q3, the gate of the P-channel transistor Q1 is connected to the gate of the P-channel transistor Q3, the source of the P-channel transistor Q1 is connected to the source of the P-channel transistor Q3 and connected to the VDD circuit, the gate and the drain of the N-channel transistor Q2 are connected, and the gate.
4. The architecture of claim 1, wherein the frequency-selective network comprises an inductor L0 and a capacitor C0 connected in parallel;
the low noise amplifier comprises a P-channel transistor Q1, an N-channel transistor Q2, a P-channel transistor Q3, an N-channel transistor Q4 and a resistor R0;
after the inductor L0 and the capacitor C0 are connected in parallel, two ends of the inductor L0 are respectively connected to the gates of an N-channel transistor Q2 and an N-channel transistor Q4, the source of the N-channel transistor Q2 is connected to the source of the N-channel transistor Q4 and connected to a VSS circuit, a resistor R0 is connected between the drain of the N-channel transistor Q2 and the drain of the P-channel transistor Q1, the drain of the N-channel transistor Q4 is connected to the drain of a P-channel transistor Q3, the gate of the P-channel transistor Q1 is connected to the gate of the P-channel transistor Q3, the source of the P-channel transistor Q1 is connected to the source of the P-channel transistor Q3 and connected to the VDD circuit, the gate and the drain of the N-channel transistor Q2 are connected, and the gate of the P-channel transistor Q1 are.
5. The architecture of claim 1, wherein the frequency-selective network comprises an inductor L0 and a capacitor C0 connected in parallel;
the low noise amplifier comprises a P-channel transistor Q1, an N-channel transistor Q2, a P-channel transistor Q3, an N-channel transistor Q4, a resistor R10, a capacitor C10, a capacitor C11, a resistor R11 and a direct current power supply;
after the inductor L0 and the capacitor C0 are connected in parallel, one end of the inductor L0 is connected with a source electrode of an N-channel transistor Q2 and a VSS circuit, the other end of the inductor L0 is connected with a source electrode of an N-channel transistor Q4, a resistor R11 is connected between a grid electrode of the N-channel transistor Q2 and a grid electrode of an N-channel transistor Q4, a capacitor C11 is connected to a circuit node between the resistor R11 and the grid electrode of the N-channel transistor Q4, and the other end of the capacitor C11 is connected with the VSS circuit;
a diode is connected between the drain of the N-channel transistor Q2 and the drain of the P-channel transistor Q1, the positive electrode end of the diode is connected with the drain end of a P-channel transistor Q1, the drain of the N-channel transistor Q4 is connected with the drain of a P-channel transistor Q3, a resistor R10 is connected between the grid of the P-channel transistor Q1 and the grid of a P-channel transistor Q3, the source of the P-channel transistor Q1 is connected with the source of the P-channel transistor Q3 and connected to a VDD circuit, a capacitor C10 is connected to a circuit node between the resistor R10 and the grid of the P-channel transistor Q3, and the other end of the capacitor C10 is connected to the VDD circuit;
the gate and drain of the N-channel transistor Q2 are connected, and the gate and drain of the P-channel transistor Q1 are connected.
6. The architecture of claim 1, wherein the frequency-selective network comprises an inductor L0 and a capacitor C0 connected in parallel,
the inductor L0 and the capacitor C0 are connected in parallel and then are connected with the low noise amplifier;
the low noise amplifier comprises a P-channel transistor Q1, an N-channel transistor Q2, a P-channel transistor Q3, an N-channel transistor Q4, an N-channel transistor Q5 and a resistor R0;
after the inductor L0 and the capacitor C0 are connected in parallel, one end of the inductor L0 is connected with a source of an N-channel transistor Q2, the other end of the inductor L0 is connected with a source of an N-channel transistor Q4 and a VSS circuit, a gate of the N-channel transistor Q2 is connected with a gate of an N-channel transistor Q4, a resistor R0 is connected between a drain of the N-channel transistor Q2 and a drain of the P-channel transistor Q1, a drain of the N-channel transistor Q4 is connected with a drain of a P-channel transistor Q3, a gate of the P-channel transistor Q1 is connected with a gate of the P-channel transistor Q3, a source of the P-channel transistor Q1 is connected with a source of the P-channel transistor Q3 and connected to a VDD circuit, a gate and a drain of the N-channel transistor Q2 are connected, and;
the source electrode of the N-channel transistor Q5 is connected with a VSS circuit, the grid electrode of the N-channel transistor Q4 is connected with the drain electrode of the N-channel transistor Q4, the drain electrode of the N-channel transistor Q5 is connected with a load and a low-pass error feedback circuit, and the other end of the load is connected to a VDD circuit.
7. The architecture of claim 1, wherein the frequency-selective network comprises an inductor L0 and a capacitor C0 connected in parallel;
the low noise amplifier comprises a P-channel transistor Q1, an N-channel transistor Q2, a P-channel transistor Q3, an N-channel transistor Q4 and a resistor R0;
after the inductor L0 and the capacitor C0 are connected in parallel, one end of the inductor L0 is connected with a source of a P-channel transistor Q3 and a VSS circuit, the other end of the inductor L0 is connected with a source of a P-channel transistor Q1, a gate of the P-channel transistor Q1 is connected with a gate of a P-channel transistor Q3, a resistor R0 is connected between a drain of the P-channel transistor Q1 and a drain of the N-channel transistor Q2, a drain of the N-channel transistor Q4 is connected with a drain of the P-channel transistor Q3, a gate of the N-channel transistor Q2 is connected with a gate of the N-channel transistor Q4, a source of the N-channel transistor Q2 is connected with a source of the N-channel transistor Q4 and connected to the VDD circuit, a gate and a drain of the N-channel transistor Q2 are connected, and;
an output end of an error amplifier A1 on the low-pass error feedback circuit is connected to a circuit node between the grid of the N-channel transistor Q2 and the grid of the N-channel transistor Q4, a positive electrode end of the error amplifier A1 is connected with a capacitor C1 and a resistor R1, the other end of the capacitor C1 is grounded, and the other end of the resistor R1 is connected to a circuit node between the drain of the P-channel transistor Q3 and the drain of the N-channel transistor Q4.
8. A low frequency communication front end architecture according to any of claims 1-7, characterized in that the P-channel transistor Q1, N-channel transistor Q2, P-channel transistor Q3, N-channel transistor Q4 can be replaced by PNP transistor Q1, NPN transistor Q2, PNP transistor Q3, NPN transistor Q4, respectively.
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| CN1770627A (en) * | 2004-11-05 | 2006-05-10 | 中国科学院半导体研究所 | Automatic feedback control method for self-adaptive setover variable gain low noise amplifier |
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| CN102394571A (en) * | 2011-10-28 | 2012-03-28 | 电子科技大学 | In-chip integrated low noise amplifier |
| CN105375890A (en) * | 2014-08-20 | 2016-03-02 | 中芯国际集成电路制造(上海)有限公司 | Low-noise amplifier |
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| CN1770627A (en) * | 2004-11-05 | 2006-05-10 | 中国科学院半导体研究所 | Automatic feedback control method for self-adaptive setover variable gain low noise amplifier |
| CN101252341A (en) * | 2008-03-11 | 2008-08-27 | 东南大学 | Wideband low noise amplifier |
| CN102096079A (en) * | 2009-12-12 | 2011-06-15 | 杭州中科微电子有限公司 | Method for constructing radio frequency front end of multi-mode multi-band satellite navigation receiver and module thereof |
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