CN110737452A

CN110737452A - FPGA firmware online upgrading method and system

Info

Publication number: CN110737452A
Application number: CN201910937390.8A
Authority: CN
Inventors: 赵茵茵; 刘葵; 李秋生
Original assignee: Wuhu Qingneng Dechuang Electronic Technology Co Ltd; Qingneng Dechuang Electrical Technology (beijing) Co Ltd
Current assignee: Wuhu Qingneng Dechuang Electronic Technology Co Ltd; Qingneng Dechuang Electrical Technology (beijing) Co Ltd
Priority date: 2019-09-30
Filing date: 2019-09-30
Publication date: 2020-01-31

Abstract

The invention discloses an FPGA firmware online upgrading method and system, wherein the method comprises the steps of obtaining write configuration number through communication between an FPGA and a DSP, erasing an EPCS configuration chip, performing write operation on the configuration chip to obtain a firmware upgrading version number, sending a configuration completion signal to the DSP, obtaining an nCONFIG low level signal, enabling the FPGA to enter a configuration and initialization state, judging whether an INIT _ DONE signal is a high level signal, reestablishing communication between the FPGA firmware and the DSP if the INIT _ DONE signal is a high level signal, sending the firmware upgrading version number to the DSP, and judging whether the upgrading is successful or not by the DSP.

Description

FPGA firmware online upgrading method and system

Technical Field

The invention relates to the technical field of electronic information, in particular to an FPGA firmware online upgrading method and system.

Background

In a power electronic system, a control scheme of DSP + FPGA is usually adopted to upgrade FPGA firmware. The scheme combines the characteristics of rich FGPA programmable resources and parallel pipeline processing and the characteristic of stronger DSP computing capacity, and can reduce the hardware cost and improve the product performance.

At present, a method for upgrading FPGA firmware includes (1) online burning of FPGA firmware through a Nios II soft core, which is high in hardware cost and low in efficiency, (2) online upgrading of FPGA is realized by connecting a DSP to an FPGA through a parallel interface without using the Nios II soft core, and a TMDC completes conversion of a rpd format burning file according to a communication handshake protocol and communicates with the DSP through NET.

The existing FPGA firmware upgrading method can not realize the online upgrading of the FPGA firmware and automatically restart, and does not have the online configuration monitoring function, so that the DSP can not determine whether the FPGA is successfully upgraded, and the reliability is poor.

Disclosure of Invention

Based on this, it is necessary to provide methods and systems for upgrading FPGA firmware online, so as to implement online upgrading of FPGA firmware, automatically restart, and improve reliability of FPGA upgrading.

In order to achieve the purpose, the invention provides the following scheme:

FPGA firmware online upgrading method includes:

acquiring a programming file by the FPGA firmware; the FPGA firmware is formed by solidifying a JTAG interface, an active serial memory interface and a serial peripheral interface from a machine in the FPGA;

acquiring a command for writing configuration data; the configuration data writing command is a command generated by the DSP according to the read programming file;

according to the configuration data writing command, the active serial memory interface performs erasing operation on an EPCS configuration chip externally connected with the FPGA firmware to obtain an erasing state;

according to the erasing state, the active serial memory interface performs writing operation on the EPCS configuration chip to obtain an FPGA firmware upgrading version number, and sends a configuration completion signal to the DSP; the FPGA firmware is in communication connection with the DSP through the serial peripheral interface slave;

acquiring an nCONFIG signal; the nCONFIG signal is a control signal generated by the DSP and used for starting a configuration process;

when the nCONFIG signal is at a low level, the FPGA firmware enters a configuration state; the configuration state is a state that the FPGA firmware stops working;

judging whether the CONF _ DONE signal generated by the FPGA firmware is a high-level signal; the CONF _ DONE signal is a signal generated by the FPGA firmware after the configuration state is finished;

when the CONF _ DONE signal is at a high level, the FPGA firmware enters an initialization state; the initialization state is a state that all IO ports in the FPGA firmware are in a high impedance state;

generating an INIT _ DONE high level signal; the INIT _ DONE high level signal is a signal generated by the FPGA firmware after the initialization state is finished;

according to the INIT _ DONE high level signal, reestablishing the communication connection between the FPGA firmware and the DSP, and sending the FPGA firmware upgrade version number to the DSP;

obtaining upgrade feedback information; the upgrade feedback information is generated by the DSP according to the firmware upgrade version number;

judging whether the upgrade is successful according to the upgrade feedback information; if the upgrade is successful, ending; and if the upgrading fails, returning the command for acquiring the write configuration data.

Optionally, the writing operation of the active serial memory interface to the EPCS configuration chip is performed according to the erase state to obtain an FPGA firmware upgrade version number, and a configuration completion signal is sent to a DSP in communication connection with the FPGA firmware, and specifically includes:

judging whether the erasing state is successful or not;

if not, returning to the step of carrying out erasing operation on the EPCS configuration chip externally connected with the FPGA firmware according to the write configuration data command to obtain an erasing state;

if so, sending an erasing success command to a DSP in communication connection with the FPGA firmware;

and according to the successful erasing command, the active serial memory interface performs writing operation on the EPCS configuration chip to obtain the upgrading version number of the FPGA firmware and sends a configuration completion signal to a DSP which is in communication connection with the FPGA firmware.

Optionally, according to the erase success command, the active serial memory interface performs write operation on the EPCS configuration chip to obtain an FPGA firmware upgrade version number, and sends a configuration completion signal to a DSP in communication connection with the FPGA firmware, and specifically includes:

receiving a configuration data instruction of the nth frame sent by the DSP; the configuration data instruction is generated according to the configuration file of the FPGA firmware after the DSP receives the successful erasing command; n is more than or equal to 1;

writing the EPCS configuration chip according to the configuration data instruction of the nth frame to obtain the writing operation state of the nth frame;

judging whether the write operation state of the nth frame is successful;

if not, returning to the instruction for receiving the configuration data of the nth frame sent by the DSP;

if yes, comparing whether N is equal to N, wherein N represents a configuration data instruction of the last frames sent by the DSP, and N is not more than N, if N is less than N, making N equal to N +1 and returning to the step of receiving the configuration data instruction of the nth frame sent by the DSP, and if N is equal to N, completing configuration, obtaining an FPGA firmware upgrade version number, and sending a configuration completion signal to the DSP.

The invention also provides an FPGA firmware online upgrading system, which comprises:

the acquisition module is used for acquiring the programming file by adopting FPGA firmware, wherein the FPGA firmware is formed by solidifying a JTAG interface, an active serial memory interface and a serial peripheral interface from a machine in an FPGA;

the second acquisition module is used for acquiring a configuration data writing command; the configuration data writing command is a command generated by the DSP according to the read programming file;

the erasing module is used for erasing the EPCS configuration chip externally connected with the FPGA firmware by the active serial memory interface according to the configuration data writing command to obtain an erasing state;

the write operation module is used for performing write operation on the EPCS configuration chip by the active serial memory interface according to the erasing state to obtain an FPGA firmware upgrade version number and sending a configuration completion signal to the DSP; the FPGA firmware is in communication connection with the DSP through the serial peripheral interface slave;

the third acquisition module is used for acquiring the nCONFIG signal; the nCONFIG signal is a control signal generated by the DSP and used for starting a configuration process;

a configuration state entering module, configured to enter a configuration state by the FPGA firmware when the nCONFIG signal is at a low level; the configuration state is a state that the FPGA firmware stops working;

an judging module, configured to judge whether a CONF _ DONE signal generated by the FPGA firmware is a high-level signal, where the CONF _ DONE signal is a signal generated by the FPGA firmware after the configuration state is ended;

an initialization state entering module, configured to, when the CONF _ DONE signal is at a high level, enter an initialization state by the FPGA firmware; the initialization state is a state that all IO ports in the FPGA firmware are in a high impedance state;

the high level signal generating module is used for generating an INIT _ DONE high level signal; the INIT _ DONE high level signal is a signal generated by the FPGA firmware after the initialization state is finished;

the communication connection reestablishment module is used for reestablishing the communication connection between the FPGA firmware and the DSP according to the INIT _ DONE high level signal and sending the upgrading version number of the FPGA firmware to the DSP;

the upgrade feedback information acquisition module is used for acquiring upgrade feedback information; the upgrade feedback information is generated by the DSP according to the firmware upgrade version number;

the second judgment module is used for judging whether the upgrade is successful according to the upgrade feedback information; if the upgrade is successful, ending; and if the upgrading fails, returning the command for acquiring the write configuration data.

Optionally, the write operation module specifically includes:

the erasing judgment unit is used for judging whether the erasing state is successful in erasing operation; if not, returning to the erasing module; if so, sending an erasing success command to a DSP in communication connection with the FPGA firmware, and executing a write operation unit;

and the write operation unit is used for performing write operation on the EPCS configuration chip by the active serial memory interface according to the successful erasing command to obtain an FPGA firmware upgrade version number and sending a configuration completion signal to a DSP in communication connection with the FPGA firmware.

Optionally, the write operation unit specifically includes:

the instruction receiving subunit is used for receiving the configuration data instruction of the nth frame sent by the DSP; the configuration data instruction is generated after the DSP receives the successful erasing command and reads the configuration data of the FPGA firmware; n is more than or equal to 1;

the write operation subunit is used for performing write operation on the EPCS configuration chip according to the configuration data instruction of the nth frame to obtain a write operation state of the nth frame;

the judging subunit is used for judging whether the write operation state of the nth frame is successful; if not, returning to the instruction receiving subunit; if yes, executing a comparison subunit;

and the comparison subunit is used for comparing whether N is equal to N, wherein N represents a configuration data instruction of the last frames sent by the DSP, N is less than or equal to N, when N is less than N, N is equal to N +1 and returns to the instruction receiving subunit, and when N is equal to N, configuration is completed, an FPGA firmware upgrade version number is obtained, and a configuration completion signal is sent to the DSP.

Compared with the prior art, the invention has the beneficial effects that:

the invention provides FPGA firmware online upgrading methods and systems, wherein the method comprises the steps of obtaining write configuration numbers through communication between an FPGA and a DSP, erasing an EPCS configuration chip, performing write operation on the configuration chip to obtain a firmware upgrading version number, sending a configuration completion signal to the DSP, obtaining an nCONFIG low level signal, enabling the FPGA to enter a configuration state and an initialization state, judging whether an INIT _ DONE signal is a high level signal, reestablishing communication between the FPGA firmware and the DSP if the INIT _ DONE signal is the high level signal, sending the firmware upgrading version number to the DSP, and judging whether the upgrading is successful by the DSP.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive labor.

Fig. 1 is a flowchart of an on-line upgrade method for 1 FPGA firmware according to an embodiment of the present invention;

FIG. 2 is a timing diagram illustrating configuration of FPGA firmware according to embodiment 2 of the present invention;

fig. 3 is a schematic structural diagram of an on-line upgrade system for 3 kinds of FPGA firmware according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only partial embodiments of of the present invention, rather than all embodiments.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, a more detailed description is provided below in conjunction with the accompanying drawings and the detailed description.

Example 1:

fig. 1 is a flowchart of an implementation method of 1 FPGA firmware online upgrades in the present invention.

Referring to fig. 1, the method for upgrading the FPGA firmware on line of the present embodiment includes:

step S1: and acquiring a programming file by the FPGA firmware.

The FPGA firmware is formed by solidifying a JTAG interface, an active serial memory interface and a serial peripheral interface from a machine in the FPGA.

Step S2: and acquiring a write configuration data command.

The configuration data writing command is a command generated by the DSP according to the read programming file.

Step S3: and according to the configuration data writing command, the active serial memory interface performs erasing operation on an EPCS (electronic programmable logic controller) configuration chip externally connected with the FPGA firmware to obtain an erasing state.

Step S4: and according to the erasing state, the active serial memory interface performs writing operation on the EPCS configuration chip to obtain the upgrading version number of the FPGA firmware and sends a configuration completion signal to the DSP. And the FPGA firmware is in communication connection with the DSP through the serial peripheral interface slave computer.

The step S4 specifically includes:

1) judging whether the erasing state is successful or not; if not, returning to the step S3; and if so, sending an erasing success command to a DSP in communication connection with the FPGA firmware.

2) And according to the successful erasing command, the active serial memory interface performs writing operation on the EPCS configuration chip to obtain the upgrading version number of the FPGA firmware and sends a configuration completion signal to a DSP which is in communication connection with the FPGA firmware. The method specifically comprises the following steps:

21) receiving a configuration data instruction of the nth frame sent by the DSP; the configuration data instruction is generated after the DSP receives the successful erasing command and reads the configuration data of the FPGA firmware; n is more than or equal to 1.

22) And performing write operation on the EPCS configuration chip according to the configuration data instruction of the nth frame to obtain the write operation state of the nth frame.

23) And judging whether the write operation state of the nth frame is successful.

If the write operation state of the nth frame is write operation failure, returning to the step 21), if the write operation state is write operation success, comparing whether N is equal to N, wherein N represents the configuration data instruction of the last frames sent by the DSP, and N is less than or equal to N.

When N is less than N, making N equal to N +1, and returning to the step 21); and when N is equal to N, completing configuration to obtain the upgrading version number of the FPGA firmware, and sending a configuration completion signal to the DSP.

Step S5: acquiring the nCONFIG signal.

The nCONFIG signal is a control signal generated by the DSP to start a configuration process.

Step S6: and when the nCONFIG signal is at a low level, the FPGA firmware enters a configuration state.

The configuration state is a state in which the FPGA firmware stops working.

Step S7: and judging whether the CONF _ DONE signal generated by the FPGA firmware is a high-level signal.

The CONF _ DONE signal is a signal generated by the FPGA firmware after the configuration state ends. If the CONF _ DONE signal is at a high level, step S8 is executed.

Step S8: the FPGA firmware enters an initialization state.

The initialization state is a state in which all IO ports in the FPGA firmware are in a high impedance state.

Step S9: generating an INIT _ DONE high level signal.

The INIT _ DONE high level signal is a signal generated by the FPGA firmware after the initialization state is finished.

Step S10: according to the INIT _ DONE high level signal, the communication connection between the FPGA firmware and the DSP is reestablished, and the upgrading version number of the FPGA firmware is sent to the DSP.

Step S11: and obtaining upgrade feedback information.

The upgrade feedback information is generated by the DSP according to the firmware upgrade version number.

Step S12: and judging whether the upgrade is successful. Specifically, whether the upgrade is successful is judged according to the upgrade feedback information, and if the upgrade is successful, the process is ended; if the upgrade fails, the process returns to the step S2.

On the basis of a control architecture based on DSP + FPGA, the method of combining active serial configuration (active serial memory interface) and JTAG configuration (JTAG interface) of the FPGA is adopted to upgrade the FPGA firmware, so that the on-line upgrade of the FPGA firmware can be realized, the FPGA firmware is automatically restarted, the on-line configuration monitoring function is realized, and the upgrade failure can be avoided; saving logic resources and circuit hardware resources of the FPGA; JTAG design can also realize online debugging and factory firmware programming in the product development process; meanwhile, the embodiment can also support the selectable programming of various FPGA programs, and the applicability of the product can be improved under the condition of not modifying hardware and programs.

Example 2:

the FPGA firmware is formed by solidifying a JTAG interface, an Active Serial Memory Interface (ASMI) and a serial peripheral interface slave machine (SPI slave) in an FPGA, the FPGA firmware is in communication connection with the DSP through the serial peripheral interface slave machine, the FPGA firmware is externally connected with an EPCS configuration chip, and an upper computer is respectively connected with the FPGA firmware and the DSP.

The specific online upgrading process of the FPGA firmware comprises the following steps:

when the system is powered on at th time, the FPGA firmware is programmed through the JTAG interface to obtain a programming file, when the system is powered on again, the FPGA firmware reads the configuration data from the EPCS and caches the configuration data into the internal SRAM, and then the system can normally work and establishes SPI communication connection with the DSP.

And the upper computer reads the programming file and generates a command for upgrading the FPGA firmware. When a command requiring upgrading of the FPGA firmware is received from the upper computer, the DSP reads the FPGA configuration data from the memory (internal SRAM). And the DSP packetizes the read configuration data, adds check information and a control command to the configuration data, and then packs and sends the configuration data as a configuration data command to the FPGA.

The method comprises the steps that a DSP sends a write configuration data command to an FPGA through an SPI, the FPGA carries out erasing operation on an EPCS after receiving the command, if the erasing is successful, the FPGA returns an erasing successful state to the DSP, otherwise, the FPGA continues erasing operation and returns an erasing failed state, after the erasing is successful, the DSP sends frame configuration commands to the FPGA through the SPI, the configuration command data comprise the length and the verification of the configuration data, after the FPGA receives frame configuration commands, the FPGA carries out write operation on the EPCS according to a time sequence required by the EPCS and simultaneously returns a write back operation state, if the write operation state returned by the FPGA is failed, the DSP resends the configuration commands, after the write success state returned by the FPGA is received, the DSP starts sending a next frame configuration command until all the configuration data are written, and the FPGA obtains received firmware version information according to the analyzed configuration data.

During erasing and writing the EPCS, the FPGA monitors the ASMI for busy, illegal _ write, and illegal _ erase signals, returning the corresponding operating state to the DSP. Therefore, the DSP realizes the control of the FPGA configuration file process.

After all the configuration data are written, the FPGA sends a writing-finished state to the DSP; the DSP sends a low signal of nCONFIG. When nCONFIG is at low level, the FPGA enters a reset state, and the SPI connection between the FPGA and the DSP is disconnected accordingly. After nCONFIG low continues for 5uS, the DSP signals nCONFIG high. Then the FPGA initiates active configuration at this point.

And after the configuration is finished, the CONF _ DONE signal is changed into high level, the FPGA enters an initialization state, and all IO are in high impedance state. After initialization is complete, the functions of the FPGA design can then be implemented. When the IO function of the FPGA meets the design requirement, the INIT _ DONE signal is changed into high level, and the INIT _ DONE signal of the FPGA is output to the DSP. And when the DSP detects that the INIT _ DONE signal is changed into high level, the DSP restarts the SPI communication connection with the FPGA, and the system finishes the on-line upgrade of the FPGA and restarts the work.

After the SPI connection is reestablished, the FPGA sends updated version information to the DSP. And the DSP determines whether the FPGA firmware is successfully upgraded, and if not, the FPGA is reconfigured.

The Configuration timing of the FPGA is as shown in FIG. 2, which includes three processes of Reset, Configuration, and Initialization, referring to FIG. 2, MODE represents a detailed Configuration process of the FPGA, Reset represents Reset, Configuration represents Configuration, Initialization represents Initialization, and User-MODE represents User MODE, Reset is a process in which the device enters a Reset state when the nCONFIG signal is low, the device exits the Reset state when the nCONFIG signal is high, and releases the nSTATUS signal in preparation for accepting Configuration data and starting a Configuration phase in which the nSTATUS signal and CONF _ DONE remain low.

As optional embodiments, the DSP in this embodiment may be replaced with other controllers such as a CPLD, an ARM, and an MCU to control field upgrade of the FPGA.

The FPGA firmware online upgrading method can realize online upgrading of the FPGA firmware and automatic restarting, has an online configuration monitoring function, can determine whether the FPGA is successfully upgraded in real time by the DSP, improves the reliability of the FPGA firmware online upgrading, can be controlled by the DSP in the upgrading process of the FPGA firmware, improves the reliability of the firmware upgrading by steps, does not need the DSP to simulate JTAG time sequence to configure the FPGA, reduces the complexity of software design, saves hardware IO (input/output) resources, is simple in FPGA program design, saves logic resources and memory resources, can reduce the product volume, can update the FPGA firmware through an external communication interface, does not need to disassemble equipment or interfaces, and conveniently realizes the field upgrading of the FPGA firmware.

Example 3:

the embodiment also provides kinds of FPGA firmware online upgrade systems, and fig. 3 is a schematic structural diagram of 3 kinds of FPGA firmware online upgrade systems according to the embodiment of the present invention.

Referring to fig. 3, the FPGA firmware online upgrade system includes:

the th acquisition module 301 is configured to acquire the programming file by using FPGA firmware, where the FPGA firmware is formed by fixing a JTAG interface, an active serial memory interface, and a serial peripheral interface from a computer in an FPGA.

A second obtaining module 302, configured to obtain a command to write configuration data; the configuration data writing command is a command generated by the DSP according to the read programming file.

The erasing module 303 is configured to, according to the write configuration data command, perform an erasing operation on an EPCS configuration chip externally connected to the FPGA firmware by using the active serial memory interface to obtain an erasing state.

The write operation module 304 is configured to, according to the erase state, perform write operation on the EPCS configuration chip by the active serial memory interface to obtain an FPGA firmware upgrade version number, and send a configuration completion signal to the DSP; and the FPGA firmware is in communication connection with the DSP through the serial peripheral interface slave computer.

A third obtaining module 305, configured to obtain an nCONFIG signal; the nCONFIG signal is a control signal generated by the DSP to start a configuration process.

A configuration state entering module 306, configured to enter a configuration state by the FPGA firmware when the nCONFIG signal is at a low level; the configuration state is a state in which the FPGA firmware stops working.

A determining module 307, configured to determine whether a CONF _ DONE signal generated by the FPGA firmware is a high level signal, where the CONF _ DONE signal is a signal generated by the FPGA firmware after the configuration state is ended.

An initialization state entering module 308, configured to, when the CONF _ DONE signal is at a high level, enter an initialization state by the FPGA firmware; the initialization state is a state in which all IO ports in the FPGA firmware are in a high impedance state.

A high level signal generating module 309, configured to generate an INIT _ DONE high level signal; the INIT _ DONE high level signal is a signal generated by the FPGA firmware after the initialization state is finished.

And the communication connection reestablishment module 310 is configured to reestablish the communication connection between the FPGA firmware and the DSP according to the INIT _ DONE high level signal, and send the upgrade version number of the FPGA firmware to the DSP.

An upgrade feedback information obtaining module 311, configured to obtain upgrade feedback information; the upgrade feedback information is generated by the DSP according to the firmware upgrade version number.

A second judging module 312, configured to judge whether the upgrade is successful according to the upgrade feedback information; if the upgrade is successful, ending; and if the upgrading fails, returning the command for acquiring the write configuration data.

As optional embodiments, the write operation module 304 specifically includes:

the erasing judgment unit is used for judging whether the erasing state is successful in erasing operation; if not, returning to the erasing module 303; and if so, sending an erasing success command to a DSP in communication connection with the FPGA firmware, and executing a write operation unit.

As optional embodiments, the write operation unit specifically includes:

the instruction receiving subunit is used for receiving the configuration data instruction of the nth frame sent by the DSP; the configuration data instruction is generated after the DSP receives the successful erasing command and reads the configuration data of the FPGA firmware; n is more than or equal to 1.

And the write operation subunit is used for performing write operation on the EPCS configuration chip according to the configuration data instruction of the nth frame to obtain the write operation state of the nth frame.

The judging subunit is used for judging whether the write operation state of the nth frame is successful; if not, returning to the instruction receiving subunit; if so, the comparison subunit is executed.

The FPGA firmware online upgrading system can realize online upgrading of the FPGA firmware and automatically restart the FPGA firmware; the system has an online configuration monitoring function, and the DSP can determine whether the FPGA is successfully upgraded in real time, so that the reliability of the FPGA firmware online upgrade is improved; the FPGA firmware is updated through the external communication interface, and equipment or an interface does not need to be disassembled, so that the field upgrade of the FPGA firmware is conveniently realized; the control of the FPGA configuration process is realized in a mode of communicating with the DSP, and the FPGA can be reconfigured without powering on the system again; the EPCS storage space required by the FPGA firmware is small, extra hardware design is not needed, the product volume is reduced, and the product cost is saved; the FPGA firmware upgrading system simultaneously meets the requirements of on-site online real-time firmware upgrading and online debugging in the research and development stage.

In the present specification, the embodiments are described in a progressive manner, and the same and similar parts among the embodiments may be referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.

The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core idea of the present invention, and to those skilled in the art with variations in the specific embodiments and applications of the invention.

Claims

1, FPGA firmware online upgrade method, characterized by comprising:

2. The on-line upgrade method for FPGA firmware as claimed in claim 1, wherein the writing operation of the EPCS configuration chip by the active serial memory interface according to the erase state to obtain an FPGA firmware upgrade version number and sending a configuration completion signal to a DSP communicatively connected to the FPGA firmware includes:

judging whether the erasing state is successful or not;

3. The on-line upgrade method for FPGA firmware as claimed in claim 2, wherein the step of writing the EPCS configuration chip by the active serial memory interface according to the erase success command to obtain an FPGA firmware upgrade version number and sending a configuration completion signal to a DSP communicatively connected to the FPGA firmware includes:

judging whether the write operation state of the nth frame is successful;

4, FPGA firmware online upgrade system, characterized by, including:

5. The kinds of FPGA firmware online upgrade system of claim 4, wherein the write operation module specifically comprises:

6. The kinds of FPGA firmware online upgrade system of claim 5, wherein the write operation unit specifically comprises: