CN110727401B - Memory access system - Google Patents

Memory access system Download PDF

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Publication number
CN110727401B
CN110727401B CN201910846714.7A CN201910846714A CN110727401B CN 110727401 B CN110727401 B CN 110727401B CN 201910846714 A CN201910846714 A CN 201910846714A CN 110727401 B CN110727401 B CN 110727401B
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memory
data
path
channel
control
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CN110727401A (en
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高剑刚
石嵩
吕晖
宁永波
严忻恺
吴铁彬
刘骁
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Wuxi Jiangnan Computing Technology Institute
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device

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  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

A memory access system, computer system structure and processor micro-structure design technical field. The system comprises a storage controller and a storage; the memory is a 128-bit memory formed by two groups of memory particles, and each group of memory particles is 64 bits; the memory controller comprises a user interface, a first control path CCH0, a second control path CCH1, a first data path DCH0, and a second data path DCH 1; the user interface is used for receiving the upper layer memory access request and distributing the memory access request to the first control channel CCH0, the second control channel CCH1, the first data channel DCH0 and the second data channel DCH1, and then is responsible for collecting and returning the response; in single channel mode, the first control path CCH0 or the second control path CCH1 is used to manage the first data path DCH0 and the second data path DCH1 simultaneously; in the dual channel mode, the first control path CCH0 and the second control path CCH1 manage the first data path DCH0 and the second data path DCH1, respectively. The invention can be flexibly configured to support high-reliability application scenes and high-bandwidth application scenes.

Description

Memory access system
Technical Field
The invention belongs to the technical field of computer system structures and processor microstructure design, and particularly relates to a memory access system.
Background
Memory controllers are an important component of computer systems. At present, the mainstream memory used in the high performance computing field is still the DDR (double Data rate) series memory, mainly the new generation of DDR4 memory. DDR series memories are usually spliced into modules with data bit width of 64 bits, such as UDIMM and RDIMM for use (if checking is considered, 64+8=72 bits, and if no special description is given, the subsequent bit width refers to only the data bit width, not to the total bit width of check bits on the tape). The traditional 64-bit memory controller technology only controls 1 memory channel with 64-bit data width, and is responsible for converting the memory access request of the upper layer into a command meeting DDR4 specification, and performing check code generation and error detection and correction functions of data, wherein the granularity of one-time memory access is 512 bits, namely 64B.
Conventional 64-bit memory controllers do not meet the processor demands well for high performance computing. On the one hand, because the memory granules used by the data center are up to millions and the memory access pressure is large, in order to improve the MTBF of the system operation, the design of the data memory access is required to have stronger robustness. Data verification requires the use of stronger codes, which require larger data granularity, such as ChipKill codes, which can correct errors of a whole grain, and the required data granularity is 512+64 (512-bit data + 64-bit verification), which is impossible for a 64-bit memory controller. On the other hand, in the high-performance computing field, the granularity of data available to the processor core is larger, such as issuing more than 128B access requests, while if a 64-bit memory controller is used, multiple DDR4 access implementations are required, which may result in larger access delay.
For this reason, the conventional method has difficulty in realizing highly reliable data check encoding.
The invention patent application CN01135091.1 discloses a method for implementing a dual-channel shared memory, and specifically discloses setting the clock frequency of the shared memory to be twice the system clock frequency of the logic IC or ASIC chip connected to the shared memory, setting the switching control signal of the shared memory to be a switch selection signal with the same frequency and phase as the system clock of the logic IC or ASIC chip connected to the shared memory, and making a single-port memory equivalent to a dual-port memory, so that two different modules inside the logic IC or ASIC chip can respectively obtain an independent memory access interface. This method does not solve the above problems.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a memory access system which can be flexibly configured to support a high-reliability application scene and a high-bandwidth application scene.
The invention is realized by the following technical scheme:
the invention provides a memory access system, which comprises a memory controller and a memory; the memory is a 128-bit memory formed by two groups of memory particles, and each group of memory particles is 64 bits; the memory controller comprises a user interface, a first control path CCH0, a second control path CCH1, a first data path DCH0, and a second data path DCH 1; the user interface is used for receiving an upper layer memory access request and distributing the memory access request to the first control channel CCH0, the second control channel CCH1, the first data channel DCH0 and the second data channel DCH1, and then is responsible for collecting and returning responses; in single channel mode, the first control path CCH0 or the second control path CCH1 is used to manage a first data path DCH0 and a second data path DCH1 simultaneously; in dual channel mode, the first control path CCH0 and the second control path CCH1 manage the first data path DCH0 and second data path DCH1, respectively.
The invention supports use of either a single 128-bit channel (referred to as a single channel mode) or 2 independent 64-bit channels (referred to as a dual channel mode).
Preferably, the user interface distributes the upper layer access request to rules of the control path:
in single channel mode, upper layer access requests are fixedly distributed to the first control path CCH0 or the second control path CCH 1;
in the dual channel mode, upper layer access requests are distributed to the first control path CCH0 and the second control path CCH1 according to address mapping rules.
Preferably, the user interface has a processing rule for the case where the upper layer access request is greater than 64B:
splitting an upper layer access request into a plurality of sub-requests, wherein each sub-request is 64B, and distributing the sub-requests to a control path;
and collecting response data of a plurality of sub-requests and returning the response data to the upper layer.
Preferably, the memory is a DDR series memory.
Preferably, the burst length of the storage granules is 8.
Preferably, the check rule of the data path is as follows:
in a single channel mode, generating 64-bit check data by adopting check coding in each beat, wherein the 64-bit check data is used for correcting errors of one storage particle;
in the dual-channel mode, 32-bit check data is generated by adopting check coding for one channel and 32-bit check data is generated by adopting check coding for the other channel.
Preferably, the verification rule of the data path in the dual channel mode further includes: before check coding, 8-bit data transferred by a memory grain at one beat is taken as one symbol.
Preferably, the verification rule of the data path in the dual channel mode further includes: before check coding, 8-beat data of one burst of each pin of the memory granule is taken as a symbol.
Preferably, the verification coding adopts ChipKil advanced coding.
Preferably, two groups of memory granules are spliced into a 128-bit memory; alternatively, two sets of memory particles are arranged separately to form a 128-bit memory.
The invention has the following beneficial effects:
the memory access system can effectively improve the usability, performance and reliability of DDR series memory controllers, and can be suitable for different application scenes such as high-reliability application scenes and high-bandwidth application scenes. The method is characterized in that a single-channel mode is configured for a high-reliability scene, powerful error correction capability can be realized, a double-channel mode is configured for a high-bandwidth application scene, small-granularity access and storage bandwidth efficiency can be effectively improved, and data errors of different modes can be corrected.
Drawings
FIG. 1 is a block diagram of a memory access system according to the present invention.
Detailed Description
The following are specific embodiments of the present invention and are further described with reference to the drawings, but the present invention is not limited to these embodiments.
Referring to fig. 1, an access system of the present invention includes a memory controller and a memory. The memory is a 128-bit memory (16-bit check bits are calculated, the total bit width is 144 bits), and each group of memory particles is 64 bits. In one embodiment, two sets of memory particles are spliced to form a 128-bit memory; in another embodiment, two sets of memory particles are arranged separately to form a 128-bit memory. The memory is a DDR series memory, such as DDR3, DDR4 memory.
The memory controller comprises a user interface, a first control path CCH0, a second control path CCH1, a first data path DCH0, and a second data path DCH 1. The user interface is used for receiving and distributing the upper layer memory access request to the first control path CCH0, the second control path CCH1, the first data path DCH0 and the second data path DCH1, and then is responsible for collecting and returning the response. The first control path CCH0 and the second control path CCH1 are responsible for scheduling of requests, protocol management and memory command generation. The first data path DCH0 and the second data path DCH1 are responsible for conversion and verification functions of data.
In particular, the first control path CCH0 and the second control path CCH1, and the first data path DCH0 and the second data path DCH1 are decoupled to facilitate multiplexing of different modes. The connection relationship between the first control path CCH0 and the second control path CCH1, and the first data path DCH0 and the second data path DCH1 is configurable. In particular, in single channel mode, the first control path CCH0 or the second control path CCH1 is used to manage the first data path DCH0 and the second data path DCH1 simultaneously. In this case, the first control path CCH0 or the second control path CCH1 needs to observe the state of the first data path DCH0 and the second data path DCH1 simultaneously, i.e. the data flow of the first data path DCH0 and the second data path DCH1 are synchronized. In the dual channel mode, the first control path CCH0 and the second control path CCH1 manage the first data path DCH0 and the second data path DCH1, respectively, independently of each other.
The user interface needs to shield the difference of different modes to the upper layer part, namely the channel mode is transparent to the upper layer memory access request. To this end, the rule for the user interface to distribute the upper layer access request to the control path is designed as follows: in single channel mode, upper layer access requests are fixedly distributed to the first control path CCH0 or the second control path CCH 1; in the dual channel mode, upper layer access requests are distributed to the first control path CCH0 and the second control path CCH1 according to address mapping rules. Taking the dual-channel mode as an example, different address ranges are allocated to the first control channel CCH0 or the second control channel CCH1 in advance, and when the address of the upper layer access request is within the address range of the first control channel CCH0 or the second control channel CCH1, the upper layer access request is distributed to the corresponding control channel.
In order to maintain the transparency of the upper-layer memory access request, in a dual-channel mode, a user interface splits a large-granularity memory access request and merges response data. Specifically, the user interface processes the rule when the upper layer access request is greater than 64B: splitting an upper layer access request into a plurality of sub-requests, wherein each sub-request is 64B, and distributing the sub-requests to a control path; and collecting response data of a plurality of sub-requests and returning the response data to the upper layer. For example, when the access request is a 128B read request and a 128B write request, the split into 2 sub-request processes of 64B is needed, and the read response data of 2 sub-requests needs to be collected when the read response is returned. The invention is not limited to the upper layer access request being 128B, and for larger upper layer access requests, the larger upper layer access requests can be split into a plurality of 64B sub-requests to be processed respectively.
The clock frequency ratio of the memory controller to the memory die, such as DDR4 die, is designed to be 1:2, with a memory burst length of 8. Checking rule of data path: in a single channel mode, generating 64-bit check data by adopting check coding in each beat, wherein the 64-bit check data is used for correcting errors of one storage particle; in the dual-channel mode, 32-bit check data is generated by adopting check coding for one channel and 32-bit check data is generated by adopting check coding for the other channel. For example, in the single channel mode, 512-bit data can be read or written in a memory controller per cycle, and in the dual channel mode, 256-bit data can be read/written in one channel (DCH 0 or DCH 1) per cycle. By adopting 512+64 ChipKil advanced coding (the coding can correct 4 8-bit symbol errors), 64-bit check data can be generated in each beat under a single-channel mode, and the data errors of 1 particle can be corrected without considering a data arrangement mode. For the dual channel mode, 2 beats of data are needed to generate 64 bits of data, which cannot correct 1 whole grain error (because 64 bits of data are needed to access one grain at a time, and encoding can correct only 32 bits), and the arrangement mode of the data needs to be considered.
The verification rule of the data path in the dual-channel mode further comprises: the data is arranged before check encoding. The arrangement mode comprises transverse arrangement and longitudinal arrangement. The transverse arrangement is as follows: the 8-bit data transferred one beat of the memory grain is taken as one symbol. The longitudinal arrangement is as follows: the 8 beat data of one burst per pin of the memory grain is taken as one symbol. And finally, carrying out check coding on all data, generating check data and carrying out error correction. This configurable approach can accommodate different error scenarios.
The invention provides a 128-bit memory controller architecture with multiplexing of single-channel and double-channel modes, a decoupling of a control channel and a data channel, a request splitting and merging mechanism and a data arrangement mode for generating check codes, which can effectively improve the access bandwidth efficiency of small granularity and correct data errors of different modes.
It will be appreciated by persons skilled in the art that the embodiments of the invention described above and shown in the drawings are given by way of example only and are not limiting of the invention. The objects of the present invention have been fully and effectively accomplished. The functional and structural principles of the present invention have been shown and described in the examples, and any variations or modifications of the embodiments of the present invention may be made without departing from the principles.

Claims (4)

1. An access system comprises a memory controller and a memory; the memory is a 128-bit memory formed by two groups of memory particles, and each group of memory particles is 64 bits; the memory controller comprises a user interface, a first control path CCH0, a second control path CCH1, a first data path DCH0, and a second data path DCH 1; the user interface is used for receiving an upper layer memory access request and distributing the memory access request to the first control channel CCH0, the second control channel CCH1, the first data channel DCH0 and the second data channel DCH1, and then is responsible for collecting and returning responses; in single channel mode, the first control path CCH0 or the second control path CCH1 is used to manage a first data path DCH0 and a second data path DCH1 simultaneously; in dual channel mode, the first control path CCH0 and the second control path CCH1 manage the first data path DCH0 and second data path DCH1, respectively;
wherein the user interface distributes the upper layer access request to rules of the control path: in single channel mode, upper layer access requests are fixedly distributed to the first control path CCH0 or the second control path CCH 1; in the dual-channel mode, an upper layer access request is distributed to a first control channel CCH0 and a second control channel CCH1 according to an address mapping rule; the user interface processes the rule when the request for upper layer access is greater than 64B: splitting an upper layer access request into a plurality of sub-requests, wherein each sub-request is 64B, and distributing the sub-requests to a control path; the response data of a plurality of sub-requests are collected and then returned to the upper layer;
checking rule of data path: the burst length of the storage granule is 8; in a single channel mode, generating 64-bit check data by adopting check coding in each beat, wherein the 64-bit check data is used for correcting errors of one storage particle; in a dual-channel mode, one channel adopts check coding to generate 32-bit check data, and the other channel adopts check coding to generate 32-bit check data; the verification rule of the data path in the dual-channel mode further comprises: before check coding, data is transversely or longitudinally arranged, and transverse arrangement is as follows: taking 8-bit data transmitted by a memory particle under one beat as a symbol, and longitudinally arranging: the 8 beat data of one burst per pin of the memory grain is taken as one symbol.
2. The memory access system as claimed in claim 1, wherein said memory is a DDR series memory.
3. The memory access system of claim 1, wherein the check code is a ChipKill advanced code.
4. The memory access system as claimed in claim 1, wherein two groups of memory granules are spliced into a 128-bit memory; alternatively, two sets of memory particles are arranged separately to form a 128-bit memory.
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