CN110706733A

CN110706733A - DRAM memory row disturbance error solution method

Info

Publication number: CN110706733A
Application number: CN201910744955.0A
Authority: CN
Inventors: 章铁飞; 朱继祥
Original assignee: Zhejiang Gongshang University
Current assignee: Zhejiang Gongshang University
Priority date: 2019-08-13
Filing date: 2019-08-13
Publication date: 2020-01-17

Abstract

A DRAM memory row disturbance error solution method comprises the following steps: s1, each DRAM memory row adopts a two-bit latest access timer to track the latest passive activation information; s2, when some memory line has read-write access, it generates active activation command to its adjacent line according to probability N; s3, after the active activation command is determined to be generated, determining whether to execute the active activation operation according to the latest access timer information of the memory row; the invention has the advantages that: on the premise of negligible storage cost, the active activation command can be accurately sent to the victim memory row, meanwhile, unnecessary active activation commands are avoided, and adverse effects on performance are minimized.

Description

DRAM memory row disturbance error solution method

Technical Field

The invention provides a solution based on memory row passive activation information, aiming at the problem of row disturbance error of a DRAM memory in the existing computer.

Background

DRAM memory is widely used for the main memory of computers. Each memory cell of a DRAM memory contains a capacitor, where data is stored primarily as a charge. A large number of memory cells form a two-dimensional memory array, with the horizontal memory cells forming rows and the vertical memory cells being columns. The DRAM memory reads and writes data in units of rows, and each time the data is read and written, the row in which the target data is located needs to be activated. When a data row (row) in the DRAM is frequently activated by reading and writing, the memory cells of the data rows adjacent to the row above and below the row decrease the threshold voltage due to the coupling effect, the leakage current increases, and the charges in the memory cell capacitors are rapidly lost, resulting in the loss of stored data. This phenomenon of memory row data loss due to frequent activation of adjacent rows is called row disturb error.

The main reason for the row disturbance error is that the charge loss of the row memory cell is accelerated, so one solution is to perform a refresh operation on the row memory cell in time, supplement the charge, and protect the data. A common default data refresh operation period for DRAM memories is 64 milliseconds. The row causing the other rows to have data errors due to row disturbance is called a victim row, and the row having the row disturbance error is called a victim row. If the number of activation times of the victim row exceeds a certain threshold in the default refresh period, row disturbance errors occur to the data of the victim row, and the victim row cannot be protected by the default refresh operation in time. Therefore, once the number of activations of the victim row approaches a certain threshold, an active activation operation is required to protect the data of the victim row.

The active activation operation is equivalent to the refresh operation at the circuit level. The active refresh operation corresponds to a passive refresh operation, which occurs mainly when a memory row is read or written or a default refresh operation is performed. The passive activation operation is equivalent to the active activation operation in protecting the line data against disturbance errors. If a memory row has recently undergone a passive active operation, there is no need to initiate an active refresh operation to protect the data. The traditional method for solving the line disturbance error depends on active activation operation, and the data protection effect of passive activation operation is not considered, so that unnecessary active activation operation is excessive, and adverse effect on performance is brought.

Disclosure of Invention

The present invention overcomes the above-mentioned drawbacks of the prior art and proposes a method for solving the disturbance error of DRAM rows in combination with the memory row passive activation information. The contents and features of the present invention include the following:

s1, each DRAM memory line adopts two-bit recent access timer to track its recent passive activation

Information;

s2, when some memory line has read-write access, it generates active activation command to its adjacent line according to probability N;

s3, after the active activation command is determined to be generated, determining the latest access timer information according to the memory row

Whether to perform an active activation operation;

wherein the step of S1 is specifically as follows: each memory row is provided with a two-bit latest access timer, when the memory row is subjected to passive activation operation (operation such as reading and writing, default refreshing and the like), the corresponding latest access timer is initialized to 11 and is periodically updated according to the sequence of 11, 10, 01 and 00 until the latest access timer is changed into 00; the method comprises the steps that a threshold value of the frequent activation times of adjacent rows with disturbance errors of a memory row is set to be R, and the time T required for activating R times determines the update period of a latest access timer; the update period of the two-bit last access timer is T/3, so the period T is required for updating from 11 to 00.

Wherein the step of S2 is specifically as follows: each time data access occurs, a random number generator in the memory controller generates a random number r between [0, N), and the value of the probability N equivalent to the random number r is between [0, rN); if r is less than or equal to nN, the event with the probability of N is generated, namely an active activation command for an adjacent row is generated; otherwise, no proactive activation command is generated.

Wherein the step of S3 is specifically as follows: after the active activation command is generated, checking the latest access timer value of the memory row to be activated, and if the value is 00, sending the active activation command to the DRAM; otherwise, the proactive activation command cancels.

The invention has the advantages that: on the premise of negligible storage cost, the active activation command can be accurately sent to the victim memory row, meanwhile, unnecessary active activation commands are avoided, and adverse effects on performance are minimized.

Drawings

FIG. 1 is a schematic diagram of a DRAM row disturb error problem described by the method of the present invention.

Fig. 2 is the update process of the last access timer of the method of the present invention.

Fig. 3 is a main flow diagram of the method of the present invention.

Detailed Description

The technical scheme of the method is further explained by combining the attached drawings and the embodiment.

Fig. 1 is a diagram illustrating a row disturbance error problem of a DRAM, in which memory cells in the DRAM form a two-dimensional array, and an impaired row (aggressor row) causes disturbance to two victim rows (victims rows) adjacent to each other due to frequent accesses, so that a row disturbance error occurs in the victim row. R represents the lower limit of the number of times the victim row is activated for data access when a row disturbance error occurs in the victim row. The period T is the time it takes to activate R times the offending row. The final period T may be selected as the minimum of the currently acquired periods T, since the same activation times take different times for different offending rows of different applications. The period T must be less than the default data refresh period, otherwise, the default data refresh operation protects the data against row disturbance errors. If the time period is less than the period T, the victim row does not have the current disturbance error; when the time period is longer than the period T, the victim row may be subjected to the current disturbance error, and the necessary protection is required.

Each memory row has a two-bit most recent access timer for indicating whether the current memory row has recently been passively activated. FIG. 2 is a two-bit most recent access timer update procedure, at time t₁When the memory row is passively activated (because of operations such as reading and writing, default refreshing and the like), the corresponding latest timer is set to be 11, and the value of the timer is decreased in a descending order every T/3 until 00. According to the value of the timer, whether the memory row has been activated in the latest T period can be judged. If the value of the timer is 00, the memory row is not activated in the latest T period; otherwise, it is.

If the value of the last access timer is still in the process of decrementing (less than 00), but the memory line is passively activated, the value of the last access timer is reset to 11 and then decremented at the original default T/3 interval. At this point, the value of the timer cannot indicate that the memory line has not been activated for the past period of time TOperation, only the past (2/3T, T) period, no active operation has occurred with the memory row. Since the timing at which the passive activation occurs is not predictable ahead of time, once it occurs during the descending count down of the timer, it will cause the final 00 value of the timer to occur ahead of time. In FIG. 2, time t₂A passive activation occurs, the timer is reset to 11, at time t₄The timer is set to 00. If at time t₂The timer is set to 11 and no passive activation occurs, the timer until time t₅Is set to 00. Time t₄And time t₅The difference between these is the characterization error (error) introduced by the passive activation operation. The maximum value for the characterization error is T/3.

The existence of the characterization error enables the value T characterized by the latest access timer to be shorter than the real value, namely the harmful row is considered to have R activation operations in the condition of being shorter than the time period T, and the active activation operation is initiated in advance. Therefore, the characterization error causes excessive protection of the victim row, and the final period T can be extended appropriately to offset the effect of the characterization error.

Fig. 3 is a main flow chart of the present invention, first generating an active activation command with a probability N. When a memory row [ i ] has read and write access, a random number r between 0 and n is generated and the values of r and nN are compared. If r is less than nN, it indicates that an event with a probability of N occurs, and the first condition for initiating an active activation command to the victim row [ i-1] and row [ i +1] is satisfied. The second condition is to check the values of the last access timer (RAC) of the victim rows row [ i +1] and row [ i-1], and if the value is 00, send an active activate command to the memory; if the value is not 00, it indicates that the victim is still within the period T, protected by the last passive activate operation, so no active activate command needs to be sent.

The generation of the active refresh command in a probabilistic manner can avoid the storage cost of recording the access times of each memory row, and has the disadvantage that the missed diagnosis rate may occur, that is, the active activate command should be generated without actually being generated. And the probability value N is reasonably selected, so that the missed diagnosis rate can be controlled. The relationship between the probability N and the missed diagnosis rate P is as follows: 1- (1-e)^N*R)^k. Where k represents the number of accesses to a memory line within the normal operating life, as positiveThe normal 10-year working time is 250 hundred million, R is 32000 times, and the missed diagnosis rate can be controlled to be 4.0 multiplied by 10 by only setting the value of the probability N to be 0.2 percent^-18To a negligible extent.

The most recent access timer for each memory row requires only two bits of storage space. Considering an 8Gb DRAM memory and 8Kb memory row, all the last access timers occupy only 2M of memory space and are constructed in groups, each with a size of 512 bits. Since the most recently accessed timer for a memory row is frequently accessed, in order to increase the access speed, the timer is provided in the memory controller. Meanwhile, the extended memory controller adds a random number generator such that a random number between [0, n) is generated every time there is a data access, and accesses the latest timer group to determine whether to send an active activation command to the DRAM memory.

The embodiments described in this specification are merely illustrative of implementations of the inventive concept and the scope of the present invention should not be considered limited to the specific forms set forth in the embodiments but rather by the equivalents thereof as may occur to those skilled in the art upon consideration of the present inventive concept.

Claims

1. A DRAM memory row disturbance error solution method comprises the following steps:

s1, each DRAM memory row adopts a two-bit latest access timer to track the latest passive activation information;

s3, after the active activation command is determined to be generated, determining whether to execute the active activation operation according to the latest access timer information of the memory row;

wherein the step of S1 is specifically as follows: each memory row is provided with a two-bit latest access timer, when the memory row is subjected to passive activation operation, the corresponding latest access timer is initialized to 11 and is periodically updated according to the sequence of 11, 10, 01 and 00 until the latest access timer is finally 00; the method comprises the steps that a threshold value of the frequent activation times of adjacent rows with disturbance errors of a memory row is set to be R, and the time T required for activating R times determines the update period of a latest access timer; the update period of the two-bit latest access timer is T/3, so the period T is needed from 11 to 00;

wherein the step of S2 is specifically as follows: each time data access occurs, a random number generator in the memory controller generates a random number r between [0, N), and the value of the probability N equivalent to the random number r is between [0, rN); if r is less than or equal to nN, the event with the probability of N is generated, namely an active activation command for an adjacent row is generated; otherwise, not generating an active activation command;