CN110688086A - Reconfigurable integer-floating point adder - Google Patents
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Abstract
The invention discloses a reconfigurable integer-floating point adder, which comprises: the enabling control module is used for controlling and switching the operation mode of the reconfigurable integer-floating point adder: integer mode or floating point mode; the integer-floating point conversion module is used for carrying out homogenization pretreatment on input integer data or floating point data; the shift order matching module is used for carrying out shift judgment and shift order matching operation on the data preprocessed by the integer-floating point conversion module in a floating point operation mode; the reconfigurable summation module is used for finishing summation operation of the processed integer or floating point data to obtain a primary summation result; and the pilot '0' count shifter is used for normalizing the preliminary summation result of the summation in the floating-point operation mode and outputting a final result. When the operation requirement of simultaneously processing various types of data is met, the method has better universality and improves the flexibility of hardware allocation, thereby reducing the layout area, reducing the power consumption and reducing the hardware cost.
Description
Technical Field
The invention belongs to the field of digital signal processing, and particularly relates to a reconfigurable integer-floating point adder.
Background
Convolutional neural networks have been at the heart of research as a typical multi-layer neural network for a number of computationally intensive applications. In the research and design of a deep learning chip, accurate description of a model is often completed by cooperating various types of data and algorithms, and an arithmetic logic unit is often required to deal with the challenge of rapidly processing various types of data.
In general, in the field of digital signal processing, operations such as convolution and the like are largely used for multiply-add operations, that is, the result of the multiply operation is fused with another operand to obtain a final result, so that the execution delay of the whole multiply-add operation is saved. The performance of multiply-add calculations is often determined by the speed at which the multiply and add operations are performed, so in general purpose signal processors, the adder has a significant impact on the performance of the chip.
In recent years, with the rapid development of electronic technology, the complexity and integration of processors are higher and higher, and adders are a very basic and critical existence on microprocessors and programmable logic devices. In different fields of digital signal processing, the requirements for adders are different; the adders can be classified into fixed point adders and floating point adders, depending on the type of data used for the operation. The fixed point adder needs less computing resources, but has lower precision; floating-point adders require a lot of computational resources but have high precision, and they have advantages and disadvantages of their applications. However, the conventional adder generally only supports a single fixed-point addition or floating-point addition operation.
Disclosure of Invention
The invention aims to provide a reconfigurable integer-floating point adder, which reduces the resource utilization of the floating point adder on the basis of continuously optimizing the performance of the fixed point adder.
In order to achieve the purpose, the invention adopts the following technical scheme:
a reconfigurable integer-floating point adder comprising: the system comprises an enabling control module, an integer-floating point conversion module, a shifting order matching module, a reconfigurable summation module and a pilot '0' counting shifter;
the integer-floating point conversion module, the shifting order matching module and the reconfigurable summation module are sequentially connected with a pilot '0' counting shifter; the enabling control module is connected with the shift order matching module and the pilot '0' counting shifter;
the enabling control module is used for controlling and switching the operation mode of the reconfigurable integer-floating point adder: integer mode or floating point mode;
the integer-floating point conversion module is used for carrying out homogenization pretreatment on input integer data or floating point data;
the shift order matching module is used for carrying out shift judgment and shift order matching operation on the data preprocessed by the integer-floating point conversion module in a floating point operation mode;
the reconfigurable summation module is used for finishing summation operation of the processed integer or floating point data to obtain a primary summation result;
and the pilot '0' count shifter is used for normalizing the preliminary summation result of the summation in the floating-point operation mode and outputting a final result.
Furthermore, the integer-floating point conversion module comprises 2 32-bit parallel shift registers respectively connected with the two input ends.
Furthermore, the shift order matching module comprises a shift judger and a shift order matching device, both of which are connected with the enable control module, wherein the shift judger is connected with the output of the integer-floating point conversion module, and the shift order matching device is connected with the output of the shift judger and the output of the integer-floating point conversion module.
Further, the shift judger comprises 1 8-bit comparator, 1 8-bit two-input adder and 1 8-bit parallel shift register; the 8-bit comparator is connected with the high 8-bit output of the 2 32-bit parallel shift registers of the integer-floating point conversion module; the 8-bit two-input adder is connected with the high 8-bit output of the 2 32-bit parallel shift registers of the integer-floating point conversion module and the output of the 8-bit comparator; the 8-bit parallel shift register is connected with the output of the 8-bit comparator, the output of the 8-bit two-input adder and the high 8-bit output of the 2 32-bit parallel shift registers of the integer-floating point conversion module.
Further, the shift pair stage comprises 2 24-bit parallel shift registers, and the 2 24-bit parallel shift registers are respectively connected with the output of the shift judger and the lower 24-bit output of the 2 32-bit parallel shift registers of the integer-floating point conversion module.
Furthermore, the reconfigurable summation module comprises 4 8-bit two-input adders, the 4 8-bit two-input adders are cascaded, and the 4 8-bit two-input adders are respectively connected in series with the shift judger and the shift step-checking device of the shift step-checking module.
Further, the leading '0' module comprises 26 multi-input NOR gates, 1 23-bit parallel shift register and 1 8-bit two-input adder; the 26 multi-input NOR gates are connected in series-parallel mixed mode and are respectively connected with the 23-bit parallel shift register and the 8-bit two-input adder in series; the data output is realized by a 23-bit parallel shift register and an 8-bit two-input adder respectively.
Further, when the addend is input from the outside and the enable control signal ctrl is 1, the reconfigurable integer-floating point adder performs integer operation: the pilot '0' counting shifter processes the integer number of the data; the enabling control signal ctrl is 0, the reconfigurable integer-floating point adder performs floating point operation, and the leading "0" count shifter performs floating point number processing on data.
Further, when the enable control signal ctrl is 1, the input 32-bit integer numbers a and b to be processed are respectively divided into 4 parts, each part has 8 bits, and the parts are respectively used as the input of 4 8-bit integer adders of the integer-floating point conversion module: a [7:0] and b [7:0] are input into a low 8-bit integer adder, and a [15:8] and b [15:8] are input into a next low 8-bit integer adder; a [31] a [22:16] and b [31] b [22:16] are used as input data of next higher 8 bits and input into a next higher 8-bit integer adder; a [30:23] and b [30:23] are used as the input of the high 8 bits and input into the shaping adder of the high 8 bits for subsequent operation; the four 8-bit integer adders are sequentially cascaded, carry is carried from the low-order 8-bit adder to the high-order 8-bit adder, and the highest 8-bit adder outputs the highest carry Cout of the whole 32-bit addition operation outwards; splicing operation results of the 4 8-bit adders into 32-bit intermediate summation results; after the sign bit is placed in front of the highest bit through shift processing, a 32-bit integer preliminary summation result is obtained; and then the integer number processing of a pilot '0' counting shifter is carried out, and the final 32-bit integer addition summation result is directly output.
Further, when the enable control signal ctrl is 1, the input 32-bit to-be-processed single-precision floating point numbers a and b are respectively divided into 4 parts, each part has 8 bits, and the 8 bits are respectively used as the input of 4 8-bit integer adders; a [7:0] and b [7:0] are input into a low 8-bit integer adder, and a [15:8] and b [15:8] are input into a next low 8-bit integer adder; a [31] a [22:16] and b [31] b [22:16] are used as input data of next higher 8 bits and input to the next higher 8-bit integer adder, and a [30:23] and b [30:23] are used as input of higher 8 bits and input to the 8-bit integer adder for subsequent operation;
the logic for the floating-point mode of operation is as follows: firstly, a shift judger judges the exponent number of an input single-precision floating point number, compares the sizes of the two exponent numbers and obtains the difference value of the two exponent numbers; then, the small order is compared with the large order, and the difference value is input to a shift order comparator of the mantissa operation unit part for carrying out shift operation; then, carrying out corresponding operation on the single-precision floating point number to be processed after the order matching and the shifting are finished by 4 8-bit addition sub-parts respectively to obtain a 32-bit intermediate operation result of the single-precision floating point number; then, the post-positioned sign position is preposed and input into a pilot '0' counting shifter; and processing the floating point number by a pilot '0' counting shifter to finally obtain a normalized 32-bit single-precision floating point number addition and summation result.
The integer-floating point conversion module is used for carrying out transposition arrangement of data bits according to the switching of the operation mode so as to enable the transposition arrangement to be matched with the operation resource distribution of 4 8-bit reshaping adders;
the summation module and the cascade module comprise 32-bit integer adders which are formed by cascading 4 8-bit integer adders and can be reconstructed into 32-bit single-precision floating point adders to carry out integer summation operation on input data, calculate the result and carry condition of each bit, carry out carry transmission among the cascaded 8-bit adders, and carry out output register processing on the most significant carry for subsequent operation;
the shift judger judges the order code of two input floating point numbers under the condition that the enable end gives a floating point operation mode signal to obtain the number of bits needing to be shifted due to order matching;
the shift order matching device is used for carrying out order matching shift operation on the tail code of the input floating point number in the floating point operation mode;
leading '0' counting shifter, tail code processing module of operation result in floating point operation mode to determine normalized shift digit number and shift.
Furthermore, in the floating point operation mode controlled by the enable controller, the input 32-bit single-precision floating point number is divided into 4 parts of 8 bits, and corresponding operation and processing are performed respectively. Since the 32-bit single-precision floating-point number is composed of 1-bit sign bit, 8-bit exponent bit, and 23-bit mantissa bit from high to low, when split, the digits are sequentially rearranged, the 8-bit exponent bit serves as the upper 8-bit part (sign bit shift backward), the upper 7 bits of the 1-bit sign bit and mantissa are concatenated to serve as the next upper 8-bit part, and the remaining 16 bits of the mantissa serve as the next lower 8-bit part and the lower 8-bit part, respectively. The four parts are respectively input into the 4 8-bit arithmetic units for processing. Further, the high 8-bit part firstly performs comparison operation and difference operation of the order codes, and the difference value is used as a control signal to be fed into the last 3 parts, so as to facilitate the order shifting of the last 3 parts; then, the 8-bit arithmetic units of the last 3 parts perform the shift-first and sum-then operations (the exponent bits of the next higher 8-bit part do not participate in the shift). Then, a 32-bit preliminary summation result is generated, and sign bit resetting processing is carried out on the preliminary summation result, so that the sign bit is placed back to the 32-bit highest bit to obtain an actual summation result. Subsequently, the actual summation result is subjected to a leading "0" count shift process. In addition, under the shaping operation mode controlled by the enable controller, the high 8-bit part is changed to carry out summation operation, and the last 3 parts are changed to only carry out summation operation; then, after the actual summation result enters a pilot '0' counting shifter, the final result is directly output without shifting; the rest of the operation flow is the same as the floating point operation mode.
Compared with the prior art, the invention has the following beneficial effects: the invention realizes the design of the 32-bit reconfigurable integer-floating point adder which can be used for integer operation and floating point operation simultaneously based on the reconfigurable thought. When the arithmetic requirement of simultaneously processing a plurality of types of data is met, the method has better universality compared with the conventional addition arithmetic unit. In addition, the processing of 32-bit data is realized in a cascade mode of 4 8 bit units, and the flexibility of hardware distribution can be improved on the basis of ensuring the operation performance, so that the layout area is reduced, the power consumption is reduced, and the hardware cost is reduced.
The invention can be used in a larger-scale reconfigurable algorithm chain (such as a reconfigurable convolver and a reconfigurable processing unit), and realizes more accurate and more efficient resource multiplexing under the condition of flexible and complex computing requirements of an artificial intelligent chip on computing resources.
With the increasing fire of reconfigurable technology, the invention reduces the resource utilization of the floating-point adder on the basis of continuously optimizing the performance of the fixed-point adder; the universality is enhanced while the requirements of higher speed and smaller area are pursued, so that the requirements of the adder in various situations are met.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic diagram of the overall structure of a 32-bit reconfigurable integer-floating point adder.
FIG. 2 is a schematic diagram of an integer-floating point conversion module of a reconfigurable integer-floating point adder.
FIG. 3 is a schematic diagram of a 32-bit reconfigurable integer-floating point adder shift pair order module.
FIG. 4 is a schematic diagram of a 32-bit reconfigurable integer-floating point adder reconfigurable summation module.
FIG. 5 is a schematic diagram of a leading "0" count shifter.
Detailed Description
The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
The following detailed description is exemplary in nature and is intended to provide further details of the invention. Unless otherwise defined, all technical terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the invention.
Referring to fig. 1, the present invention provides a reconfigurable integer-floating point adder, which includes an enable control module, an integer-floating point conversion module, a shift pair module, a reconfigurable summation module, and a leading "0" count shifter.
The enabling control module is used for controlling and switching the operation mode of the reconfigurable integer-floating point adder: integer mode or floating point mode; the enabling control module is connected with the displacement judging device, the displacement order matching module and the pilot '0' counting shifter.
The integer-floating point conversion module is used for preprocessing the input integer data or floating point data to be homogenized so as to reconstruct the operation of the summation module;
the shift order matching module is used for carrying out shift judgment and shift order matching operation on the preprocessed data in a floating point operation mode;
the reconfigurable summation module is used for finishing summation operation of the processed integer or floating point data;
and the pilot '0' module is used for normalizing the summed initial result in the floating-point operation mode and outputting a final result.
The integer-floating point conversion module comprises 2 32-bit parallel shift registers, wherein the 2 32-bit parallel shift registers are respectively connected with two input ends A/B and are simultaneously connected with 4 8-bit integer adders of the reconfigurable summation module.
The shift order matching module comprises a shift judger and a shift order matching device, wherein the shift judger comprises a plurality of comparators, the shift order matching device comprises a plurality of shift registers, the comparators and the shift registers are connected in series with the output of the integer-floating point conversion module and are respectively connected with the enabling control module, the shift judger and the shift order matching device are both connected with the enabling control module, the shift judger is connected with the output of the integer-floating point conversion module, and the shift order matching device is connected with the output of the shift judger and the output of the integer-floating point conversion module.
The shift judger comprises 1 8-bit comparator, 1 8-bit two-input adder and 1 8-bit parallel shift register; the 8-bit comparator is connected with the high 8-bit output of the 2 32-bit parallel shift registers of the integer-floating point conversion module; the 8-bit two-input adder is connected with the high 8-bit output of the 2 32-bit parallel shift registers of the integer-floating point conversion module and the output of the 8-bit comparator; the 8-bit parallel shift register is connected with the output of the 8-bit comparator, the output of the 8-bit two-input adder and the high 8-bit output of the 2 32-bit parallel shift registers of the integer-floating point conversion module.
The shift pair stage device comprises 2 24-bit parallel shift registers, and the 2 24-bit parallel shift registers are respectively connected with the output of the shift judger and the lower 24-bit output of the 2 32-bit parallel shift registers of the integer-floating point conversion module.
The reconfigurable summation module comprises 4 8-bit two-input adders, the 4 8-bit two-input adders are cascaded, and the 4 8-bit two-input adders are respectively connected in series with a shift judger and a shift step-checking device of the shift step-checking module.
The pilot '0' module comprises a plurality of multi-input NOR gates, an adder and a shift register, wherein the plurality of multi-input NOR gates are connected in series-parallel mixed connection, connected in series with the adder and the shift register and connected in series with the output of the reconfigurable summation module. Specifically, the leader "0" module comprises 26 multi-input NOR gates, 1 23-bit parallel shift register and 1 8-bit two-input adder; the 26 multi-input NOR gates are connected in series-parallel mixed mode and are respectively connected with the 23-bit parallel shift register and the 8-bit two-input adder in series; the data output is realized by a 23-bit parallel shift register and an 8-bit two-input adder respectively.
The enabling configuration information and the data to be processed are input from the outside, and the enabling control information determines the path selection of data operation, integer addition operation or single-precision floating point addition operation. Finally, the input data passes through the corresponding operation path to complete the corresponding addition operation.
As shown in fig. 4, the 32-bit reconfigurable integer-floating-point adder is formed by cascading 4 8-bit integer adders. Under the control of an enabling control signal (ctrl), the reconfigurable adder completes operation path selection; when the ctrl signal input is 1, the reconfigurable integer-floating point adder selects the integer operation mode, and when the ctrl signal input is 0, the reconfigurable integer-floating point adder selects the floating point operation mode.
As shown in fig. 1, 2, and 3, the addend is input from the outside, and is divided into two cases.
In the first method, an enable control signal ctrl is 1, a reconfigurable integer-floating point adder performs integer operation, and a pilot '0' counting shifter performs integer processing on data. The input 32-bit integer numbers a and b to be processed are divided into 4 parts, each part has 8 bits, and the 8 bits are used as the input of 4 8-bit integer adders. For example, a [7:0] and b [7:0] are input to the lower 8-bit integer adder, and a [15:8] and b [15:8] are input to the next lower 8-bit integer adder. It should be noted that, as shown in fig. 2, in consideration of the multiplexing performance of the entire reconfigurable integer-floating point adder structure, the input 32-bit integer number is sequentially divided only at the lower 16 bits, and at the upper 16 bits, the operation is performed by using a processing scheme with the sign bit set at the rear, that is, a [31] a [22:16] and b [31] b [22:16] are input as input data of the next higher 8 bits, and are input to the next higher 8-bit integer adder, and a [30:23] and b [30:23] are input as input of the higher 8 bits, and are input to the higher 8-bit integer adder for subsequent operation. The four 8-bit integer adders are cascaded in sequence, carry from the low-order 8-bit adder to the high-order 8-bit adder (as shown in fig. 4), and the highest 8-bit adder outputs the highest carry Cout of the whole 32-bit addition operation (as shown in fig. 4). The operation results of the 4 8-bit adders are spliced into a 32-bit intermediate summation result (due to the post-position of the sign bit); after the sign bit is placed in front of the highest bit through shift processing, a 32-bit integer preliminary summation result is obtained; and then the integer number processing (no shift) of the leading '0' counting shifter is carried out, and the final 32-bit integer addition summation result is directly output (as shown in figure 5).
And secondly, when the enable control signal ctrl is 0, the reconfigurable integer-floating point adder performs floating point operation, and the pilot '0' counting shifter performs floating point number processing on data. The input 32-bit single-precision floating point numbers a and b to be processed are divided into 4 parts, each part is 8 bits, and the parts are respectively used as the input of 4 8-bit integer adders. For example, a [7:0] and b [7:0] are input to the lower 8-bit integer adder, and a [15:8] and b [15:8] are input to the next lower 8-bit integer adder. In the same manner as in the integer arithmetic mode, in consideration of the reusability of the entire reconfigurable integer-floating point adder structure, as shown in fig. 2, it should be noted that the input 32-bit single-precision floating point number is sequentially divided only at the lower 16 bits, and the arithmetic is performed in the same way by using a processing scheme in which the sign bit is set at the upper 16 bits, that is, a [31] a [22:16] and b [31] b [22:16] are input as input data of the next higher 8 bits to the next higher 8-bit integer adder, and a [30:23] and b [30:23] are input as input data of the higher 8 bits to the higher 8-bit integer adder for subsequent arithmetic.
Because the basic principle of single-precision floating-point operation refers to that digits are equal, and mantissa digits can be added, the operation needs to judge the sizes of two floating-point exponent digits, calculate the difference value, perform log-rank on the exponent digits according to the difference value, and shift the mantissa digits, wherein the shifted digits are the difference value of the exponent digits. As shown in fig. 3, the principle of the logarithmic shift is "small-to-large order", i.e. the exponent bit a with smaller exponent bit is aligned with the exponent bit of the exponent bit b with larger exponent bit, and since the exponent bit of a is enlarged, the mantissa bit needs to be shifted right to ensure that the overall value of a is not changed. The sign bits of a and b determine whether the mantissa bits are added or subtracted.
Unlike the sequential cascade of integer operation modes, the logic of the division of the floating-point operation mode is as follows: firstly, a shift judger judges the exponent number of an input single-precision floating point number, compares the sizes of the two exponent numbers and obtains the difference value of the two exponent numbers; then, inputting the difference value to a shift order-matching device of the mantissa operation unit part for carrying out shift operation; then, 4 8-bit addition sub-parts respectively perform corresponding operation on the single-precision floating point number to be processed after the order matching and the shifting are completed, and a 32-bit intermediate operation result of the single-precision floating point number is obtained (as shown in FIG. 4); then, the post-positioned sign position is preposed and input into a pilot '0' counting shifter (as shown in figure 4); and (4) processing the floating point number by a pilot '0' counting shifter (shifting output), and finally obtaining a normalized 32-bit single-precision floating point number addition and summation result (shown in figure 5).
The embodiment is based on the reconfigurable idea, and realizes the design of the 32-bit integer-floating point reconfigurable adder. The flexible switching of the operation modes under the premise of ensuring the operation performance under the condition of different operation resources and different operation requirements is realized. Compared with the existing reconfigurable adder, the reconfigurable integer-floating point adder disclosed by the embodiment has better data and hardware allocation flexibility.
It will be appreciated by those skilled in the art that the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The embodiments disclosed above are therefore to be considered in all respects as illustrative and not restrictive. All changes which come within the scope of or equivalence to the invention are intended to be embraced therein.
Claims (10)
1. A reconfigurable integer-floating point adder, comprising: the system comprises an enabling control module, an integer-floating point conversion module, a shifting order matching module, a reconfigurable summation module and a pilot '0' counting shifter;
the integer-floating point conversion module, the shifting order matching module and the reconfigurable summation module are sequentially connected with a pilot '0' counting shifter; the enabling control module is connected with the shift order matching module and the pilot '0' counting shifter;
the enabling control module is used for controlling and switching the operation mode of the reconfigurable integer-floating point adder: integer mode or floating point mode;
the integer-floating point conversion module is used for carrying out homogenization pretreatment on input integer data or floating point data;
the shift order matching module is used for carrying out shift judgment and shift order matching operation on the data preprocessed by the integer-floating point conversion module in a floating point operation mode;
the reconfigurable summation module is used for finishing summation operation of the processed integer or floating point data to obtain a primary summation result;
and the pilot '0' count shifter is used for normalizing the preliminary summation result of the summation in the floating-point operation mode and outputting a final result.
2. A reconfigurable integer-floating point adder according to claim 1, wherein the integer-floating point conversion module comprises 2 32-bit parallel shift registers, each coupled to two inputs.
3. The reconfigurable integer-floating point adder according to claim 1, wherein the shift register module comprises a shift determiner and a shift register, both of which are connected to the enable control module, wherein the shift determiner is connected to the output of the integer-floating point conversion module, and the shift register is connected to the output of the shift determiner and the output of the integer-floating point conversion module.
4. A reconfigurable integer-floating point adder according to claim 3, wherein the shift judger comprises 1 8 bit comparator, 1 8 bit two input adder and 1 8 bit parallel shift register; the 8-bit comparator is connected with the high 8-bit output of the 2 32-bit parallel shift registers of the integer-floating point conversion module; the 8-bit two-input adder is connected with the high 8-bit output of the 2 32-bit parallel shift registers of the integer-floating point conversion module and the output of the 8-bit comparator; the 8-bit parallel shift register is connected with the output of the 8-bit comparator, the output of the 8-bit two-input adder and the high 8-bit output of the 2 32-bit parallel shift registers of the integer-floating point conversion module.
5. A reconfigurable integer-floating point adder according to claim 3, wherein the shift pair stage comprises 2 24-bit parallel shift registers, and the 2 24-bit parallel shift registers are respectively connected to the shift determiner output and the lower 24-bit outputs of the 2 32-bit parallel shift registers of the integer-floating point conversion block.
6. The reconfigurable integer-floating point adder according to claim 3, wherein the reconfigurable summing module comprises 4 8-bit two-input adders, the 4 8-bit two-input adders are cascaded, and the 4 8-bit two-input adders are respectively connected in series to the shift judger and the shift pair stage of the shift pair stage module.
7. A reconfigurable integer-floating point adder according to claim 3, wherein the leading "0" block comprises 26 multiple-input nor gates, 1 23-bit parallel shift register, and 1 8-bit two-input adder; the 26 multi-input NOR gates are connected in series-parallel mixed mode and are respectively connected with the 23-bit parallel shift register and the 8-bit two-input adder in series; the data output is realized by a 23-bit parallel shift register and an 8-bit two-input adder respectively.
8. The reconfigurable integer-floating point adder according to claim 1, wherein when the enable control signal ctrl is 1 after the addend is input from outside, the reconfigurable integer-floating point adder performs an integer operation: the pilot '0' counting shifter processes the integer number of the data; the enabling control signal ctrl is 0, the reconfigurable integer-floating point adder performs floating point operation, and the leading "0" count shifter performs floating point number processing on data.
9. A reconfigurable integer-floating point adder according to claim 8, wherein when the enable control signal ctrl is 1, the input 32-bit integer numbers a and b to be processed are each divided into 4 parts, each part having 8 bits, and the parts are respectively used as the input of 4 8-bit integer adders of the integer-floating point conversion module: a [7:0] and b [7:0] are input into a low 8-bit integer adder, and a [15:8] and b [15:8] are input into a next low 8-bit integer adder; a [31] a [22:16] and b [31] b [22:16] are used as input data of next higher 8 bits and input into a next higher 8-bit integer adder; a [30:23] and b [30:23] are used as the input of the high 8 bits and input into the shaping adder of the high 8 bits for subsequent operation; the four 8-bit integer adders are sequentially cascaded, carry is carried from the low-order 8-bit adder to the high-order 8-bit adder, and the highest 8-bit adder outputs the highest carry Cout of the whole 32-bit addition operation outwards; splicing operation results of the 4 8-bit adders into 32-bit intermediate summation results; after the sign bit is placed in front of the highest bit through shift processing, a 32-bit integer preliminary summation result is obtained; and then the integer number processing of a pilot '0' counting shifter is carried out, and the final 32-bit integer addition summation result is directly output.
10. A reconfigurable integer-floating point adder according to claim 8, wherein when the enable control signal ctrl is 1, the input 32-bit single-precision floating point number a, b to be processed is divided into 4 parts, each part having 8 bits, and each part is used as the input of 4 8-bit integer adders; a [7:0] and b [7:0] are input into a low 8-bit integer adder, and a [15:8] and b [15:8] are input into a next low 8-bit integer adder; a [31] a [22:16] and b [31] b [22:16] are used as input data of next higher 8 bits and input to the next higher 8-bit integer adder, and a [30:23] and b [30:23] are used as input of higher 8 bits and input to the 8-bit integer adder for subsequent operation;
the logic for the floating-point mode of operation is as follows: firstly, a shift judger judges the exponent number of an input single-precision floating point number, compares the sizes of the two exponent numbers and obtains the difference value of the two exponent numbers; then, the small order is compared with the large order, and the difference value is input to a shift order comparator of the mantissa operation unit part for carrying out shift operation; then, carrying out corresponding operation on the single-precision floating point number to be processed after the order matching and the shifting are finished by 4 8-bit addition sub-parts respectively to obtain a 32-bit intermediate operation result of the single-precision floating point number; then, the post-positioned sign position is preposed and input into a pilot '0' counting shifter; and processing the floating point number by a pilot '0' counting shifter to finally obtain a normalized 32-bit single-precision floating point number addition and summation result.
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