CN110676158B - Zero-bubble Ge/Si heterogeneous hybrid integration method for realizing lattice blocking - Google Patents
Zero-bubble Ge/Si heterogeneous hybrid integration method for realizing lattice blocking Download PDFInfo
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Abstract
The invention discloses a zero-bubble Ge/Si heterogeneous mixed integration method capable of realizing lattice blocking, which is characterized in that a Si and Ge double-laminated structure of an amorphous structure is introduced into a Ge/Si bonding interface, on one hand, the high-strength Ge/Si bonding without an oxidation layer is realized through annealing and crystallization of a-Ge, on the other hand, lattice mismatch between single crystal Si and single crystal Ge is blocked by using a-Si, a mismatch dislocation source is thoroughly shielded, and the discharge of bonding interface by-products and the thorough blocking of crystal lattices are realized through a-Si of a loose structure, so that the Ge/Si bonding interface without interface bubbles, oxidation layers and penetrating dislocation is prepared.
Description
Technical Field
The invention relates to a novel zero-bubble Ge/Si heterogeneous hybrid integration method capable of realizing lattice blocking, in particular to a method for realizing high-strength Ge/Si bonding of a non-oxidation layer by annealing and crystallization of a-Ge and realizing discharge of a bonding interface by-product and complete blocking of a lattice by a loose-structure a-Si by utilizing an a-Ge/a-Si double-laminated semiconductor interlayer bonding technology so as to prepare a Ge/Si bonding interface without interface bubbles, an oxidation layer and threading dislocation.
Background
Due to 4.2% of lattice mismatch between Si and Ge materials, Threading Dislocation (TD) is introduced into the Ge thin film by heteroepitaxy of the Ge thin film on the Si base, and the Threading Dislocation Density (TDD) is as high as 107-109 cm-2（Huang, S., et al. (2012). Depth-dependent etch pit density in Ge epilayer on Si substrate with a self-patterned Ge coalescence island template. Thin Solid Films, 520(6), 2307-2310；Shah, V. A., et al. (2011). Effect of layer thickness on structural quality of Ge epilayers grown directangle on Si (001), Thin Solid Films, 519(22), 7911-7917; luan, H.C., et al (1999). High-quality Ge epilayers on Si with low threading-localization strategies Applied physics letters, 75(19), 2909-. TD formation is caused by too long a threading of dislocation lines formed by lattice mismatch into the film surface, and in principle one TD may be generated by one misfit dislocation. Therefore, to control TDD in epitaxial Ge films, it is necessary to control the nucleation, propagation, and interaction of dislocations.
At present, researchers have proposed many improved Ge/Si epitaxy methods, which mainly include: (1) low-high temperature two-step growth method (Liu, Z., et al. (2017). 48 GHz high-performance Ge-on-SOI photodetector with zero-bias 40 Gbps growth by selective epitaxial growth. Journal of light Technology, 35(24), 5306-; (2) SiGe buffer layer growth (Currie, M. T., et al. (1998). Controlling the threading positioning defects in Ge on Si used graded SiGe layers and chemical-mechanical poling Applied Physics Letters, 72(14), 1718-; (3) Ge/SiGe multi-quantum well isolation (Chen, c., et al. (2012), Epitaxial growth of germanium on silicon for light emittings. International Journal of Photoenergy, 2012, 1-8); (4) selective epitaxy (Li, Q., Han, et al. (2003) Selective growth of Ge on Si (100) through vias of SiO2 nano-patterned using source molecular beam epitaxy. Applied Physics Letters, 83(24), 5032-5034.). Although TDD of the top Ge film can be reduced to nearly 10 by these improved epitaxial methods6 cm-2Magnitude order, but each method has its limitations, the distribution of TDD in Ge thin films prepared by low-high temperature two-step growth method and Ge/SiGe multiple quantum well isolation method is not uniform, and TDD is higher the closer to the epitaxial interface. To release 4.2% of lattice mismatch, the thickness of the relaxed SiGe buffer layer needs to reach 10 μm, so this method cannot be applied to the fabrication of high frequency devices. Although the selective area epitaxy method can prepare a Ge film without TD, the mesa size of the selective area epitaxy method must be in the nanometer level, otherwise the limiting effect on TD cannot be realized, and therefore the method cannot be widely applied.
In recent years, researchers have turned their eyes to low temperature Ge/Si heterogeneous bonding (Byun, K. Y., et al (2012), Overview of low temperature hydrolytic Ge to Si direct bonding for heterologous integration. Microelectronics Reavailability, 52(2), 325. 330; Gity, F., et al (2012), chromatography of germanium/silicon p-n junction structured by low temperature thermal bonding and layer expansion Applied Physics Letters, 100(9), 092102; Byun, K. Y., product (2011) of J. application of radiation, 75. J. 3, J. 11, J. P. I. J. P. I. P. J. I. Y., K. Y., P. J. III. J. P. 3. P. J. III. P. J. 3. P. J. P. I. J. I. P. 3. J. P. I. J. P. J. III. P. J. I. P. J. P. J. 3. P. I. P. J. P. 3. A. P. A. B. A. B. A. B. A. B. A. B. A. B. A. The low-temperature Ge/Si heterogeneous bonding has the following advantages: (1) the Ge/Si bonding can be performed below 300 ℃, which is half lower than the 600 ℃ growth temperature of epitaxial Ge; (2) low temperature Ge/Si bonding enables further reduction of Threading Dislocations (TD), mainly due to limited nucleation and propagation of misfit dislocations at low temperatures; (3) the low-temperature Ge/Si bonding can maintain the crystal quality and the photoelectric characteristic of Ge to the maximum extent. Byun et al (Byun, K. Y., et al (2012), Overview of low temperature hydraulic Ge to Si direct bonding for electroluminescence integration, Microelectronics Reavailability, 52(2), 325-330) and Gity et al (Gity, F., et al (2012), Characterisation of germanium/silicon p-n junction modulated by low temperature thermal bonding and layer extension, Applied Physics Letters, 100(9), 092102) studied low temperature Ge/Si bonding using a plasma activation technology system, achieved bonding temperatures below 300 ℃, and no TD/Si bonding was observed at the Ge/Si interface. Although the method can realize the preparation of the Ge film with low TDD, as the intermediate layer is not arranged between Ge/Si, Ge and Si are in direct contact in the bonding process, lattice mismatch between Ge/Si is difficult to completely eliminate, and nucleation of mismatch dislocation is difficult to avoid, secondly, bubbles formed by hydrophilic reaction at the bonding interface of the bonding sheet prepared by the method cannot be effectively eliminated all the time, and most importantly, an oxide layer with the thickness of about 2-3 nm exists at the bonding interface, and the existence of the oxide layer limits the electrical transmission of carriers at a Ge/Si heterogeneous interface, thereby causing the deterioration of device performance. For all Ge/Si bonding techniques (Byun, K.Y., et al (2012), Overview of low temperature hydrolytic Ge to Si direct bonding for luminescence integration. Microelectronics Reavailability, 52(2), 325- & 330; Gity, F., et al (2012), propagation of germanium/silicon p-n junction modulated by low temperature catalytic bonding and layer extension Applied Physics Letters, 100, 092102; Byun, K.Y., et al (2011), comparative bonding of Ge-Si bonding, K.Y., et al (2011), J.P.E. diffusion of silicon carbide, P.E. (3545, J.S. diffusion) of Ge-Si bonding, P.E. diffusion, P.S. diffusion, S. No. 13, P.S. diffusion, P. diffusion, P.S. 13, P.S. diffusion, P. diffusion, P.S. diffusion, P. diffusion, P.S. diffusion, S. diffusion, S, h. (2010) crystalline properties of Ge/Si heterojunction doped by wet bonding. Journal of electronic materials, 39(8), 1248 and 1255), it is impossible to avoid the formation of bonding interface oxide layer and to perform overall control of interface bubbles, interface oxide layer and TDD. Therefore, how to thoroughly block the source of lattice mismatch and eliminate Ge/Si bonding interface bubbles and an interface oxide layer is a key problem to be solved urgently when the low-temperature Ge/Si bonding technology is applied to the field of photoelectrons.
According to the invention, a Si and Ge double-laminated structure with an amorphous structure is introduced into a Ge/Si bonding interface, high-strength Ge/Si bonding without an oxide layer is realized through crystallization of a-Ge, the a-Si is used for effectively isolating two single crystals of Ge and Si, the source of lattice mismatch is blocked, formation of TD is avoided, and bubbles formed by hydrophilic reaction of the bonding interface can be absorbed and discharged out of a bonding sheet due to the loose material structure of the Si with the amorphous structure, so that the purpose of eliminating interface bubbles is achieved.
Disclosure of Invention
The invention provides a zero-bubble Ge/Si heterogeneous hybrid integration method for realizing lattice blocking, aiming at the problems that TDD (time division duplex) in an epitaxial Si-based Ge film is high, lattice mismatch of a Ge/Si heterogeneous bonding interface is difficult to block, and bubbles and an oxide layer are difficult to eliminate.
In order to achieve the purpose, the invention adopts the following technical scheme:
a zero-bubble Ge/Si heterogeneous hybrid integration method for realizing lattice blocking comprises the following steps:
1) respectively and sequentially ultrasonically cleaning a Si sheet and a Ge sheet for 10-15 min by using acetone, ethanol and deionized water to remove particles and organic matters adsorbed on the surface of a substrate;
2) firstly using H with the volume ratio of 4:1 for the cleaned Si piece in the step 1)2SO4/H2O2Boiling the solution for 10-15 min, washing with deionized water for 10-15 times, and then using HF/H with the volume ratio of 1:202Soaking in the O solution for 2-4 min, and washing with deionized water for 10-15 times;
3) firstly using NH with the volume ratio of 1:1:4 for the Si piece treated in the step 2)4OH/H2O2/H2Boiling the O solution for 10-15 min, washing with deionized water for 10-15 times, and then using HF/H with the volume ratio of 1:202Soaking in the O solution for 2-4 min, and washing with deionized water for 10-15 times;
4) firstly, the Si piece treated in the step 3) is treated by HCl/H with the volume ratio of 1:1:42O2/H2Boiling the O solution for 10-15 min, washing with deionized water for 10-15 times, and then using HF/H with the volume ratio of 1:202Soaking in the O solution for 2-4 min, and washing with deionized water for 10-15 times;
5) spin-drying the Si wafer subjected to surface treatment in the step 4) by using a glue spreader, and putting the Si wafer into a magnetron sputtering system until the background vacuum degree of a sputtering chamber is less than 1 multiplied by 10-4When Pa is needed, Ar gas with the purity of 5N is filled into the sputtering chamber, so that the pressure in the sputtering chamber is 0.4 Pa;
6) sputtering a layer of a-Si film on the surface of a Si sheet at room temperature, and regulating the speed of sputtering the a-Si film by controlling the magnetron sputtering target position current and the sample holder rotating speed;
7) regulating Ar gas flow to make the pressure in the sputtering chamber be 0.5 Pa, and continuously sputtering a layer of a-Ge film on the a-Si film to be used as a bonding layer;
8) taking out the Si sheet sputtered with the a-Ge film in the step 7), and carrying out manual chemical mechanical polishing on the a-Ge film;
9) respectively and sequentially ultrasonically cleaning the Si wafer polished in the step 8) for 10-15 min by using acetone, ethanol and deionized water, and washing the Si wafer by using the deionized water for 10-15 times to remove particles adsorbed on the surface of the polycrystalline Ge;
10) respectively using HF/H with the volume ratio of 1:20 for the Si sheet cleaned in the step 9) and the Ge sheet cleaned in the step 1)2Soaking in the O solution for 2-4 min, and washing with deionized water for 10-15 times;
11) drying the Ge sheet and the Si sheet processed in the step 10) by a glue spreader, and then attaching the Ge sheet and one side of the Si sheet a-Ge film together;
12) and (3) placing the Ge/Si laminating sheet obtained in the step (11) into an annealing furnace, and carrying out low-temperature thermal annealing at 300 ℃ for 20 h to realize high-strength bonding of Ge/Si.
The invention has the remarkable advantages that:
the invention innovatively provides an a-Ge/a-Si double-laminated bonding interlayer structure to realize the discharge of Ge/Si bonding interface byproducts, the decomposition of an oxide layer and the complete blocking of crystal lattices, and the laminated structure can fully exert the respective advantages of a-Si and a-Ge to comprehensively control bonding interface bubbles, the oxide layer and dislocation. Lattice mismatch between single crystal Si and single crystal Ge can be blocked by the aid of the a-Si, a mismatch dislocation source can be thoroughly shielded, bubbles on a bonding interface can be thoroughly absorbed and transferred by the loose structure of the a-Si, a Ge/Si bonding interface with zero bubbles is obtained, and decomposition of an oxide layer on the bonding interface can be realized by means of low-temperature crystallization characteristics of the a-Ge, so that a bonding interface without the oxide layer is obtained.
Drawings
FIG. 1 is an ultrasonic microscopic examination of the Ge/Si bonding interface obtained in example 1;
FIG. 2 is a TEM image of the Ge/Si bonding interface obtained in example 1;
FIG. 3 is an ultrasonic microscopic examination of the Ge/Si bonding interface obtained in example 2.
Detailed Description
In order to make the present invention more comprehensible, the technical solutions of the present invention are further described below with reference to specific embodiments, but the present invention is not limited thereto.
The used equipment is a TRP-450 composite film sputtering deposition system, and two direct current target positions and a radio frequency target position are arranged in a growth chamber. The target materials used are 5N (more than 99.999 percent) high-purity Ge circular target material and 5N (more than 99.999 percent) high-purity Si circular target material. The Si substrate material used was an N-type single-crystal Si wafer having a crystal orientation of (100) and a single-side polished resistivity of 0.001. omega. cm, and the Ge substrate material used was an N-type single-crystal Ge wafer having a crystal orientation of (100) and a single-side polished resistivity of more than 50. omega. cm.
Example 1
Treatment of Si and Ge base materials
1) Selecting a Si and Ge substrate with a crystal orientation of (100), and respectively and sequentially ultrasonically cleaning the Si and Ge substrate for 10-15 min by using acetone, ethanol and deionized water to remove particles and organic matters attached to the surface of the substrate;
2) firstly, the Si piece cleaned by organic ultrasonic is mixed with H2SO4:H2O2Boiling a solution of =4:1 (v/v) for 10-15 min, washing with deionized water for 10-15 times, and then adding HF: H2Soaking the mixture in a solution with O =1:20 (v/v) for 2-4 mim, and washing the mixture with deionized water for 10-15 times;
3) then, the Si piece is mixed with NH4OH:H2O2:H2Boiling the solution with O =1:1:4 (v/v/v) for 10-15 min, washing the solution with deionized water for 10-15 times, and then adding HF: H2Soaking in a solution with O =1:20 (v/v) for 2-4 min, and washing with deionized water for 10-15 times;
4) finally, the Si piece is prepared by using HCl and H2O2:H2Boiling the solution with O =1:1:4 (v/v/v) for 10-15 min, washing the solution with deionized water for 10-15 times, and then adding HF: H2Soaking in a solution with O =1:20 (v/v) for 2-4 min, and washing with deionized water for 10-15 times;
two, preparation of a-Si and a-Ge double stack and Ge/Si bonding
1) Spin-drying cleaned Si wafer at 4000rpm for 30 s with a coater, placing into a sputtering deposition system, and maintaining the vacuum degree of the sputtering chamber at the background of less than 1 × 10-4When Pa is needed, filling Ar gas with the purity of 5N into the sputtering chamber, keeping the pressure in the sputtering chamber at 0.4 Pa by filling gas with the flow of 4.2 sccm, and simultaneously turning on a direct-current sputtering power supply;
2) at room temperature, adjusting the current of a direct current sputtering power supply to be 0.3A, the voltage to be 600V and the rotating speed of a sample holder to be 10 rpm, sputtering a layer of a-Si film with the thickness of 5 nm on a Si substrate, wherein the deposition rate is 12.14 nm/min;
3) after the a-Si is sputtered, regulating the flow of Ar to 6.5 sccm, keeping the pressure in a vacuum chamber at 0.5 Pa, regulating the current of a direct-current sputtering power supply to be 0.3A, the voltage to be 406V, the rotating speed of a sample holder to be 10 rpm, sputtering a layer of a-Ge film with the thickness of 35 nm on the a-Si, and depositing at the speed of 23 nm/min;
4) taking out the Si sheet after the a-Ge film is sputtered, adhering the back of the Si sheet to a grinding table on a heating plate at the temperature of 70 ℃ by adopting paraffin, and then taking down the grinding table from the heating plate until the paraffin is solidified so that the Si sheet is tightly adhered to the grinding table;
5) the mixture ratio is compol-80: H2Polishing the a-Ge film on the surface of the Si sheet for 2 min on a polyurethane polishing pad by using a polishing solution with O =1:3 (v/v);
6) sequentially ultrasonically cleaning the polished Si wafer for 10-15 min by acetone, ethanol and deionized water respectively, and washing for 10-15 times by the deionized water to remove particles adsorbed on the surface of a-Ge;
7) the cleaned Ge sheet and Si sheet are prepared according to the proportion of HF to H2Soaking in a solution with O =1:20 (v/v) for 2 min, and washing with deionized water for 10-15 times;
8) spin-drying the washed Ge sheet and the washed Si sheet by using a glue spreader, then pasting the Ge sheet and one side of the Si sheet a-Ge film together, and applying certain pressure by using fingers to extrude interface bubbles and ensure that the pasting strength of a pasting sample is higher;
9) putting the attached sample into a tubular annealing furnace, and annealing at 300 ℃ for 20 h to realize high-strength Ge/Si bonding; the heating and cooling rate is 0.5 ℃/min.
The annealed bonded sample was subjected to an ultrasonic microscope test and a TEM test, and the results are shown in fig. 1 and fig. 2, respectively. As can be seen from fig. 1, few small bubbles formed by the hydrophilic reaction of the interface were observed at the bonding interface except for some large bubbles formed by surface particles and edge tweezer contamination. As can be seen from FIG. 2, the middle 5 nm a-Si separates Ge and Si single crystals, no TD is found in the Ge layer, and the bonded Ge layer prepared therefrom has TDD less than 105 cm-2And no oxide layer was observed at the bonding interface.
Example 2
Treatment of Si and Ge base materials
1) Selecting a Si and Ge substrate with a crystal orientation of (100), and respectively and sequentially ultrasonically cleaning the Si and Ge substrate for 10-15 min by using acetone, ethanol and deionized water to remove particles and organic matters attached to the surface of the substrate;
2) firstly, the Si piece cleaned by organic ultrasonic is mixed with H2SO4:H2O2Boiling the solution with the ratio of 4:1 (v/v) for 10-15 min, washing the solution with deionized water for 10-15 times, and then using HF H2Soaking the mixture in a solution with O =1:20 (v/v) for 2-4 mim, and washing the mixture with deionized water for 10-15 times;
3) then, the Si piece is mixed with NH4OH:H2O2:H2Boiling the solution with O =1:1:4 (v/v/v) for 10-15 min, washing the solution with deionized water for 10-15 times, and then adding HF: H2Soaking in a solution with O =1:20 (v/v) for 2-4 min, and washing with deionized water for 10-15 times;
4) finally, the Si piece is prepared by using HCl and H2O2:H2Boiling the solution with O =1:1:4 (v/v/v) for 10-15 min, washing with deionized water for 10-15 times, and then adding HF: H2Soaking in a solution with O =1:20 (v/v) for 2-4 min, and washing with deionized water for 10-15 times;
two, preparation of a-Si and a-Ge double stack and Ge/Si bonding
1) Spin-drying the cleaned Si wafer at 4000rpm for 30 s by a glue spreader, putting the cleaned Si wafer into a sputtering deposition system, and keeping the background vacuum degree of a sputtering chamber to be less than 1 × 10-4When Pa is in it, it splashesAr gas with the purity of 5N is filled in the sputtering chamber, the pressure in the sputtering chamber is kept at 0.4 Pa by introducing gas with the flow of 4.2 sccm, and meanwhile, a direct-current sputtering power supply is started;
2) at room temperature, adjusting the current of a direct current sputtering power supply to be 0.3A, the voltage to be 600V and the rotating speed of a sample holder to be 10 rpm, sputtering a layer of a-Si film with the thickness of 30 nm on a Si substrate, wherein the deposition rate is 12.14 nm/min;
3) after the a-Si is sputtered, adjusting the flow of Ar to 6.5 sccm, keeping the pressure in a vacuum chamber at 0.5 Pa, adjusting the current of a direct-current sputtering power supply to 0.3A, the voltage to 406V, the rotating speed of a sample holder to 10 rpm, and sputtering a layer of a-Ge film with the thickness of 35 nm on the a-Si at the deposition rate of 23 nm/min;
4) taking out the Si sheet after the a-Ge film is sputtered, adhering the back of the Si sheet to a grinding table on a heating plate at the temperature of 70 ℃ by adopting paraffin, and then taking down the grinding table from the heating plate until the paraffin is solidified, so that the Si sheet is tightly adhered to the grinding table;
5) the mixture ratio is compol-80: H2Polishing the a-Ge film on the surface of the Si sheet for 2 min on a polyurethane polishing pad by using a polishing solution with O =1:3 (v/v);
6) ultrasonically cleaning the polished Si wafer for 10-15 min by adopting acetone, ethanol and deionized water respectively in sequence, and washing for 10-15 times by using the deionized water to remove adsorbed particles on the surface of a-Ge;
7) the cleaned Ge sheet and Si sheet are prepared according to the proportion of HF to H2Soaking in a solution with O =1:20 (v/v) for 2 min, and washing with deionized water for 10-15 times;
8) spin-drying the washed Ge sheet and the washed Si sheet by using a glue spreader, then pasting the Ge sheet and one side of the Si sheet a-Ge film together, and applying certain pressure by using fingers to extrude interface bubbles and ensure that the pasting strength of a pasting sample is higher;
9) putting the attached sample into a tubular annealing furnace, and annealing at 300 ℃ for 20 h to realize high-strength Ge/Si bonding; the heating and cooling rate is 0.5 ℃/min.
The annealed bonded sample was subjected to ultrasonic microscope test, and the result is shown in fig. 3. As can be seen from the figure, few small bubbles formed by the hydrophilic reaction of the interface were observed at the bonding interface except for some large bubbles formed by surface particles and edge tweezer contamination.
The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the claims of the present invention should be covered by the present invention.
Claims (4)
1. A zero-bubble Ge/Si heterogeneous hybrid integration method for realizing lattice blocking is characterized in that: the method comprises the following steps:
1) spin-drying the surface-treated Si wafer with a coater, placing into a magnetron sputtering system until the background vacuum degree of the sputtering chamber is less than 1 × 10-4When Pa is needed, Ar gas with the purity of 5N is filled into the sputtering chamber, so that the pressure in the sputtering chamber is 0.4 Pa;
2) sputtering a layer of a-Si film on the surface of a Si sheet at room temperature;
3) regulating the flow rate of Ar to ensure that the pressure in the sputtering chamber is 0.5 Pa, and continuously sputtering a layer of a-Ge film on the a-Si film;
4) taking out the Si sheet sputtered with the a-Ge film in the step 3), and performing manual chemical mechanical polishing on the a-Ge film;
5) ultrasonically cleaning the Si wafer polished in the step 4) for 10-15 min by adopting acetone, ethanol and deionized water respectively in sequence, and washing the Si wafer by using the deionized water for 10-15 times to remove particles adsorbed on the surface of the a-Ge film;
6) respectively using HF/H with the volume ratio of 1:20 for the Si sheet cleaned in the step 5) and the Ge sheet subjected to surface treatment2Soaking in the O solution for 2-4 min, and washing with deionized water for 10-15 times;
7) spin-drying the Ge sheet and the Si sheet processed in the step 6) by a glue spreader, and then attaching the Ge sheet and one side of the Si sheet a-Ge film together;
8) and (3) placing the Ge/Si laminating sheet obtained in the step (7) into an annealing furnace, and carrying out low-temperature thermal annealing at 300 ℃ for 20 hours to realize high-strength bonding of Ge/Si.
2. The method of claim 1 for realizing lattice-blocking zero-bubble Ge/Si heterogeneous hybrid integration, wherein: the surface treatment method of the Si sheet in the step 1) comprises the following steps:
a) respectively and sequentially ultrasonically cleaning the Si wafer for 10-15 min by using acetone, ethanol and deionized water to remove particles and organic matters adsorbed on the surface of the substrate;
b) firstly using H with the volume ratio of 4:1 to the cleaned Si piece in the step a)2SO4/H2O2Boiling the solution for 10-15 min, washing with deionized water for 10-15 times, and then using HF/H with the volume ratio of 1:202Soaking in the O solution for 2-4 min, and washing with deionized water for 10-15 times;
c) firstly using NH with the volume ratio of 1:1:4 to the Si piece treated in the step b)4OH/H2O2/H2Boiling the O solution for 10-15 min, washing with deionized water for 10-15 times, and then using HF/H with the volume ratio of 1:202Soaking in the O solution for 2-4 min, and washing with deionized water for 10-15 times;
d) firstly, the Si piece treated in the step c) is treated by HCl/H with the volume ratio of 1:1:42O2/H2Boiling the O solution for 10-15 min, washing with deionized water for 10-15 times, and then using HF/H with the volume ratio of 1:202Soaking in the O solution for 2-4 min, and washing with deionized water for 10-15 times.
3. The method of claim 1 for realizing lattice-blocking zero-bubble Ge/Si heterogeneous hybrid integration, wherein: the manual chemical mechanical polishing in the step 4) adopts a compound-80/H with the volume ratio of 1:32And using the O solution as a polishing solution.
4. The zero-bubble Ge/Si heterogeneous hybrid integration method for realizing lattice blocking according to claim 1, characterized in that: and 6) respectively and sequentially carrying out ultrasonic cleaning for 10-15 min by using acetone, ethanol and deionized water to remove the particles and organic matters adsorbed on the surface of the substrate.
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| US6515335B1 (en) * | 2002-01-04 | 2003-02-04 | International Business Machines Corporation | Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same |
| CN108447819A (en) * | 2018-04-18 | 2018-08-24 | 厦门大学 | Germanium bonding method on a kind of no interfacial bubbles insulating layer |
| CN108573878A (en) * | 2018-04-18 | 2018-09-25 | 厦门大学 | Non-oxidation layer Semiconductors At Low Temperatures bonding method |
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| US7247534B2 (en) * | 2003-11-19 | 2007-07-24 | International Business Machines Corporation | Silicon device on Si:C-OI and SGOI and method of manufacture |
| US7235812B2 (en) * | 2004-09-13 | 2007-06-26 | International Business Machines Corporation | Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques |
| CN102779902A (en) * | 2012-08-08 | 2012-11-14 | 天津蓝天太阳科技有限公司 | Preparation method of Ge/Si substrate slice for GaAs solar cell |
| CN104867814B (en) * | 2015-04-24 | 2017-09-22 | 厦门大学 | The method that Ge film bondings prepare germanium on insulating barrier |
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| US6515335B1 (en) * | 2002-01-04 | 2003-02-04 | International Business Machines Corporation | Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same |
| CN108447819A (en) * | 2018-04-18 | 2018-08-24 | 厦门大学 | Germanium bonding method on a kind of no interfacial bubbles insulating layer |
| CN108573878A (en) * | 2018-04-18 | 2018-09-25 | 厦门大学 | Non-oxidation layer Semiconductors At Low Temperatures bonding method |
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