CN110660792B - Method for generating filling pattern of FDSOI standard cell and layout method - Google Patents
Method for generating filling pattern of FDSOI standard cell and layout method Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 claims abstract description 7
- 239000000945 filler Substances 0.000 claims description 66
- 238000003780 insertion Methods 0.000 claims description 7
- 230000037431 insertion Effects 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 16
- 239000000758 substrate Substances 0.000 description 12
- 238000005468 ion implantation Methods 0.000 description 6
- 239000002184 metal Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 230000003071 parasitic effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
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- 239000002699 waste material Substances 0.000 description 2
- 238000012938 design process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
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Abstract
The application discloses a method for generating a filling graph of an FDSOI standard unit and a layout method, wherein the method comprises the following steps: acquiring parameters of FDSOI standard cells in a standard cell library; determining parameters of a filling unit according to the parameters of the FDSOI standard unit; and generating a filling pattern of the FDSOI standard cell according to the parameters of the filling cell. According to the method and the device, the parameters of the filling unit are determined according to the parameters of the FDSOI standard unit, the filling graph of the FDSOI standard unit is generated according to the parameters of the filling unit, and the parameters of the filling unit are determined based on the parameters of the FDSOI standard unit, so that the splicing problem among different types of FDSOI devices can be solved, the different types of FDSOI devices can be prepared on the same wafer, and the production cost is reduced.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a method for generating a filling pattern of an FDSOI standard unit and a layout method.
Background
The standard cell library comprises a version library, a symbol library, a circuit logic library and the like, comprises combinational logic, sequential logic, functional units and special type units, and is a basic part in the back end design process of the integrated circuit chip. The standard cells pre-designed in the standard cell library can be used for automatic logic synthesis and layout wiring, and the design efficiency can be greatly improved.
The Fully Depleted Silicon On Insulator (FDSOI) structure is a semiconductor structure in which transistors are disposed On Silicon On Insulator (SOI), and due to the fact that an insulating substance is added between the transistors, parasitic capacitance between the transistors is greatly reduced, so that parasitic capacitance of a device is reduced, and leakage current is reduced. Illustratively, as shown in fig. 1, an FDSOI structure formed by a P-type Metal Oxide Semiconductor (PMOS) transistor defining an N-type (Negative) substrate and an NMOS transistor defining a P-type substrate is an RVT device 100; as shown in fig. 2, the FDSOI structure formed by PMOS of P-type substrate and NMOS of N-type substrate is defined as LVT device 200; as shown in fig. 3, the FDSOI structure formed by PMOS and NMOS of the N-type substrate is defined as an SNW device 300; as shown in fig. 4, the FDSOI structure of PMOS and NMOS formation defining a P-type substrate is an SPW device 400. In fig. 1 to 4, 101 denotes a metal layer (Tap), 102 denotes a Gate (Gate), 103 denotes a Shallow Trench Isolation (STI) structure, and 104 denotes an insulating layer (Box).
As shown in fig. 5, in the RVT device and the LVT device, since the substrate doping types of the two devices are opposite, when they are adjacent, a singular point 501 is generated at the centerline position, which causes a problem of splicing.
In view of the above problems, different types of devices (e.g., RVT devices and LVT devices) are usually subjected to partition layout in the related art, but a great waste of area is caused.
Disclosure of Invention
The application provides a method for generating a filling pattern of an FDSOI standard unit and a layout method, which can solve the problem of area waste caused by the partitioned layout of different types of devices in an FDSOI layout structure provided in the related technology.
In one aspect, the embodiment of the present application provides a method for generating a fill pattern of an FDSOI standard cell, where the method is applied to semiconductor manufacturing, and the method includes:
acquiring parameters of FDSOI standard cells in a standard cell library;
determining parameters of a filling unit according to the parameters of the FDSOI standard unit;
and generating a filling graph of the FDSOI standard unit according to the parameters of the filling unit.
Optionally, the parameter of the FDSOI standard cell includes a height of the FDSOI standard cell, and the parameter of the filler cell includes a height of the filler cell;
the determining the parameters of the filling unit according to the parameters of the FDSOI standard unit comprises the following steps:
and determining the height of the filling unit as the height of the FDSOI standard unit.
Optionally, the parameter of the FDSOI standard cell includes an N-type well edge of the FDSOI standard cell, and the parameter of the filler cell includes an N-type well region of the filler cell;
the determining the parameters of the filling unit according to the parameters of the FDSOI standard unit comprises the following steps:
and determining the N-type well region of the filling unit according to the N-type well edge line of the FDSOI standard unit.
Optionally, the parameters of the FDSOI standard cell include a well identification layer edge line, and the parameters of the filler cell include an N-type well inversion region and a P-type well inversion region of the filler cell;
the determining the parameters of the filling unit according to the parameters of the FDSOI standard unit comprises the following steps:
and determining an N-type well inverting region and a P-type well inverting region of the filling unit according to the boundary line of the well identification layer.
Optionally, the parameter of the FDSOI standard cell includes a horizontal routing pitch of the FDSOI standard cell, and the parameter of the filler cell includes a lateral minimum routing track pitch dimension of the filler cell;
the determining the parameters of the filling unit according to the parameters of the FDSOI standard unit comprises the following steps:
and determining the transverse minimum wiring track interval size of the filling unit as the horizontal wiring interval of the FDSOI standard unit.
Optionally, the parameter of the FDSOI standard cell includes a vertical wiring pitch of the FDSOI standard cell, and the parameter of the filler cell includes a vertical minimum wiring track pitch dimension of the filler cell;
the determining the parameters of the filling unit according to the parameters of the FDSOI standard unit comprises the following steps:
and determining the vertical minimum wiring track interval size of the filling unit as the vertical wiring interval of the FDSOI standard unit.
In another aspect, the present application provides a layout method for an FDSOI standard cell library, including:
determining an insertion position where the filling unit needs to be inserted;
determining filling units to be inserted according to FDSOI standard units on two sides of the insertion position, wherein the filling units are generated according to any one of the methods;
and inserting the filling unit to be inserted into the inserting position to generate a layout of an FDSOI standard unit library so as to realize the layout splicing of the FDSOI standard unit.
The technical scheme at least comprises the following advantages:
the parameters of the filling unit are determined according to the parameters of the FDSOI standard unit, the filling unit of the FDSOI standard unit is generated according to the parameters of the filling unit, and the parameters of the filling unit are determined based on the parameters of the FDSOI standard unit, so that the splicing problem among different types of FDSOI devices can be solved, the different types of FDSOI devices can be prepared on the same wafer, and the production cost is reduced.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic diagram of a RVT device structure;
FIG. 2 is a schematic diagram of a LVT device;
FIG. 3 is a schematic structural diagram of an SNW device;
FIG. 4 is a schematic structural diagram of an SPW device;
FIG. 5 is a layout schematic of the stitching of an RVT device and an LVT device;
FIG. 6 is a flowchart of a method for generating a fill pattern for FDSOI standard cells according to an exemplary embodiment of the present application;
FIG. 7 is a flowchart of a layout method for FDSOI standard cell library according to an exemplary embodiment of the present application;
fig. 8 is a schematic layout diagram of a filler cell inserted into an LVT device and an RVT device generated based on the method for generating a filler pattern of an FDSOI standard cell provided in the embodiment of the present application;
fig. 9 is a schematic layout diagram of a filler cell inserted into an LVT device and an RVT device generated based on the method for generating a filler pattern of an FDSOI standard cell provided in the embodiment of the present application;
fig. 10 shows a layout diagram of a filler cell inserted into an SNW device and an RVT device generated based on a method for generating a filler pattern of a standard cell provided in an embodiment of the present application;
fig. 11 is a schematic layout diagram of a filler cell inserted into an SNW device and an LVT device, which is generated based on the method for generating a filler pattern of an FDSOI standard cell provided in the embodiment of the present application;
fig. 12 is a schematic layout diagram of a filler cell inserted into an SPW device and an RVT device, which is generated based on the method for generating a filler pattern of an FDSOI standard cell provided in the embodiment of the present application;
fig. 13 shows a schematic layout diagram of a filler cell inserted into an SPW device and an LVT device, which is generated based on the method for generating a filler pattern of an FDSOI standard cell provided in the embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
In the present application, the direction of the height of the FDSOI standard cell is defined as a Z-axis, the vertical direction of the layout is defined as a Y-axis, and the horizontal direction of the layout is defined as an X-axis.
Example 1:
fig. 6 is a method for generating a fill pattern of an FDSOI standard cell according to an exemplary embodiment of the present application, where the method is applied to semiconductor manufacturing, and the method includes:
The parameters of the FDSOI standard unit comprise at least one of the height of the FDSOI standard unit, an N-type Well (Well) side line, a Well-Reverse side line, a horizontal wiring interval and a vertical wiring interval; the FDSOI standard cell includes at least two of a RVT device, a LVT device, a SNW device, and a SPW device.
In step 602, parameters of the filler unit are determined according to the parameters of the FDSOI standard unit.
Wherein, the filling unit is a structure arranged between FDSOI standard units; the parameters of the filling unit comprise at least one of the height of the filling unit, an N-type well region, an N-type well inversion region, a P-type well inversion region, a transverse minimum wiring track spacing size and a vertical minimum wiring track spacing size.
In summary, in the embodiment, the parameters of the filling unit are determined according to the parameters of the FDSOI standard unit, and the filling unit of the FDSOI standard unit is automatically generated according to the parameters of the filling unit, and the parameters of the filling unit are determined based on the parameters of the FDSOI standard unit, so that the problem of splicing different types of FDSOI devices can be solved, the different types of FDSOI devices can be prepared on the same wafer, and the production cost is reduced.
Example 2:
referring to example 1, example 2 differs from example 1 in that: for the "determining parameters of the filler cells according to the parameters of the FDSOI standard cells" in step 602, it includes: the height of the filler cell is determined as the height of the FDSOI standard cell.
That is, in the present embodiment, the filler cell height is the same as the relative height of all FDSOI standard cells in the standard cell library, and the relative height is the height from the origin.
Example 3:
referring to example 1 or example 2, example 3 differs from examples 1 and 2 in that: for the "determining parameters of the filler cells according to the parameters of the FDSOI standard cells" in step 602, the method may further include: and determining the N-type well region of the filling unit according to the N-type well edge line of the FDSOI standard unit.
Example 4:
with reference to any one of embodiments 1 to 3, embodiment 4 differs from the above embodiments in that: for the "determining parameters of the filler cells according to the parameters of the FDSOI standard cells" in step 602, the method may further include: and determining an N-type well inversion region and a P-type well inversion region of the filling unit according to the boundary line of the well identification layer of the FDSOI standard unit.
Intersection regions of the well identification layer, the N-type well and the P-type well are respectively inverted, and the intersection regions behind the current plate are respectively a P-type well region and an N-type well region.
Example 5:
with reference to any one of embodiments 1 to 4, embodiment 5 differs from the above embodiments in that: for the "determining parameters of the filler cells according to the parameters of the FDSOI standard cells" in step 602, the method may further include: and determining the transverse minimum wiring track interval size of the filling unit as the horizontal wiring interval of the FDSOI standard unit. That is, the minimum lateral wiring track pitch dimension of the filler cell is equal to the horizontal wiring pitch of the FDSOI standard cell.
Example 6: with reference to any one of embodiments 1 to 5, embodiment 6 differs from the above embodiments in that: for the "determining parameters of the filler cells according to the parameters of the FDSOI standard cells" in step 602, the method may further include: and determining the vertical minimum wiring track interval size of the filling unit as the vertical wiring interval of the FDSOI standard unit. That is, the vertical minimum wiring track pitch dimension of the filler cell is equal to the vertical wiring pitch of the FDSOI standard cell.
Example 7:
referring to fig. 7, a flowchart of a layout method of an FDSOI standard cell library according to an exemplary embodiment of the present application is shown, where the method includes:
in step 701, an insertion position where a filler unit needs to be inserted is determined.
And 703, inserting a filling unit to be inserted into the insertion position to generate a layout of the FDSOI standard unit library so as to realize layout splicing of the FDSOI standard unit.
In the present embodiment, the generated filler cells include various types, for example, a filler cell inserted between the RVT device and the LVT device, a filler cell inserted between the SNW device and the RVT device, a filler cell inserted between the SNW device and the LVT device, a filler cell inserted between the SPW device and the RVT device, and a filler cell inserted between the SPW device and the LVT device.
For example, in this embodiment, first, a position where a filler unit needs to be inserted is determined in at least two types of FDSOI standard cells, then, the type of the filler unit needs to be inserted is determined according to the types of the FDSOI standard cells on both sides of the position, and then, the filler unit needs to be inserted is inserted into the position, so that a layout containing different types of FDSOI structures is generated.
Fig. 8 is a schematic layout diagram of a filler unit inserted into an LVT device and an RVT device generated by the method for generating a filler unit of an FDSOI standard cell, as shown in fig. 8, a right half of the layout of the filler unit in this embodiment is covered by a well identification layer, so that a P-well/N-well and an SDP area/SDN area may be arranged oppositely. That is, the left region is above the midline is the N-well and P + ion implantation regions, and below the midline is the P-well and N + ion implantation regions, and thus can be normally adjacent to RVT devices; the right region is provided with a P-type well and an N + ion implantation region above the central line, and the N-type well and the P + ion implantation region below the central line can be normally adjacent to the LVT device; the middle part is completely provided with an N-type well and a P + ion implantation area which are connected with the N-type well and the P + ion implantation area on the left part and the right part. The design rule limitation in the graph means that the unit layouts can be checked through the design rule after automatic splicing according to the minimum design rule and one-half minimum rule provided by a wafer factory. The structure can be applied to the condition that the devices on the left side and the right side have stable substrate voltage.
Fig. 9 shows a schematic layout diagram of another filling unit inserted into the LVT device and the RVT device generated by the layout generation method based on the FDSOI structure, as shown in fig. 9, based on the structure of the filling unit shown in fig. 8, according to basic parameters of layout design and design rules provided by a wafer factory, on the premise of meeting design rules of an active region, drawing a maximum allowable active region in a blank region of the basic structure, then according to the design rules of the contact holes, uniformly drawing the contact holes on the active region, and connecting the contact holes to a substrate voltage source by using metal to achieve the effect that the substrate voltage source is connected to the substrate. Compared with the structure provided in the embodiment of fig. 8, the structure provided in this embodiment has an increased area, and can effectively avoid the situation that the inserted device has no substrate potential.
Fig. 10 is a schematic layout diagram of a filler cell inserted into an SNW device and an RVT device generated based on the above-described method for generating a filler cell of an FDSOI standard cell; FIG. 11 is a schematic layout diagram of a filler cell inserted into an SNW device and an LVT device generated by the method for generating the filler cell of the FDSOI standard cell; FIG. 12 is a schematic layout diagram of a filler cell inserted into an SPW device and an RVT device generated based on the above-mentioned FDSOI standard cell filler cell generation method; fig. 13 is a schematic layout diagram of a filler cell inserted into an SPW device and an LVT device generated by the above-described method for generating a filler cell of an FDSOI standard cell.
In the above embodiments, VPW (Voltage of P-well) is the top metal region of the P-well, and VNW (Voltage of N-well) is the top metal region of the N-well.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (6)
1. A method for generating a filling pattern of an FDSOI standard cell, which is applied to semiconductor manufacture, and comprises the following steps:
acquiring parameters of FDSOI standard cells in a standard cell library;
determining parameters of a filling unit according to the parameters of the FDSOI standard unit;
generating a filling graph of the FDSOI standard unit according to the parameters of the filling unit;
wherein, the parameters of the FDSOI standard cell include a well identification layer edge line, the parameters of the filler cell include an N-type well inversion region and a P-type well inversion region of the filler cell, and the determining the parameters of the filler cell according to the parameters of the FDSOI standard cell includes:
and determining an N-type well inverting region and a P-type well inverting region of the filling unit according to the boundary line of the well identification layer.
2. The method of claim 1, wherein the parameters of the FDSOI standard cell comprise a height of the FDSOI standard cell and the parameters of the filler cell comprise a height of the filler cell;
the determining the parameters of the filling unit according to the parameters of the FDSOI standard unit comprises the following steps:
and determining the height of the filling unit as the height of the FDSOI standard unit.
3. The method of claim 1, wherein the parameters of the FDSOI standard cell comprise an N-well edge of the FDSOI standard cell, and the parameters of the filler cell comprise an N-well region of the filler cell;
the determining the parameters of the filling unit according to the parameters of the FDSOI standard unit comprises the following steps:
and determining the N-type well region of the filling unit according to the N-type well edge line of the FDSOI standard unit.
4. The method of claim 1, wherein the parameters of the FDSOI standard cell comprise a horizontal routing pitch of the FDSOI standard cell, and the parameters of the filler cell comprise a lateral minimum routing track spacing dimension of the filler cell;
the determining the parameters of the filling unit according to the parameters of the FDSOI standard unit comprises the following steps:
and determining the transverse minimum wiring track interval size of the filling unit as the horizontal wiring interval of the FDSOI standard unit.
5. The method of claim 1, wherein the parameters of the FDSOI standard cell comprise a vertical routing pitch of the FDSOI standard cell, and the parameters of the filler cell comprise a vertical minimum routing track spacing dimension of the filler cell;
the determining the parameters of the filling unit according to the parameters of the FDSOI standard unit comprises the following steps:
and determining the vertical minimum wiring track interval size of the filling unit as the vertical wiring interval of the FDSOI standard unit.
6. A layout method of an FDSOI standard cell library is characterized by comprising the following steps:
determining an insertion position where the filling unit needs to be inserted;
determining a filler cell to be inserted according to FDSOI standard cells on both sides of the insertion position, the filler cell being generated according to the method of any one of claims 1 to 5;
and inserting the filling unit to be inserted into the inserting position to generate a layout of an FDSOI standard unit library so as to realize the layout splicing of the FDSOI standard unit.
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| CN112380809B (en) * | 2020-11-16 | 2021-08-03 | 成都海光微电子技术有限公司 | Standard unit, physical rule verification method, device and equipment of standard unit library |
| CN112966458B (en) * | 2021-04-07 | 2022-07-26 | 北京华大九天科技股份有限公司 | Graphic processing method, electronic device, server, and storage medium |
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