CN110658596A

CN110658596A - Method for communication

Info

Publication number: CN110658596A
Application number: CN201910573098.2A
Authority: CN
Inventors: 郭丰维; 周淳朴; 陈焕能; 卓联洲
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2018-06-29
Filing date: 2019-06-28
Publication date: 2020-01-07

Abstract

A system and method for communicating with high coupling efficiency using efficient fiber-to-chip grating couplers is disclosed. In one embodiment, a method for communication includes: transmitting an optical signal between a semiconductor photonic die located on a substrate and an array of optical fibers attached to the substrate with at least one corresponding grating coupler on the semiconductor photonic die, wherein the at least one grating coupler each comprises a plurality of coupling gratings, a waveguide, a cladding layer, a first reflective layer, and a second reflective layer, wherein the plurality of coupling gratings each comprise at least one step in a first lateral direction and extend in a second lateral direction, wherein the first lateral direction and the second lateral direction are parallel to a surface of the substrate and perpendicular to each other in a grating plane, wherein the first reflective layer is configured such that the plurality of coupling gratings are disposed between the first reflective layer and the cladding layer, wherein the second reflective layer is configured such that the cladding layer is disposed between the second reflective layer and the waveguide.

Description

Method for communication

Technical Field

The embodiment of the invention relates to a method for communication.

Background

Optical gratings (optical gratings) are often used to enable communication between a light source and other components, such as a photodetector. For example, an optical grating may be used to redirect light from an optical fiber into an optical detector. Light coupled from one end of the optical grating that traverses the optical grating by reflecting from the inner surface at a shallow angle may be redirected such that the light strikes the inner surface at a more acute angle than the critical angle of incidence, allowing the redirected light to escape from the other end of the optical grating. After escaping, light may impinge (imping) on the detector. The detected light may then be used for various purposes, such as for receiving encoded communication signals transmitted through an optical grating. Unfortunately, this process, as well as the reverse process of redirecting light from an on-chip light source to an optical fiber using an optical grating, may exhibit poor coupling efficiency, where most of the redirected light does not reach the detector. There is a need to develop a method and apparatus for efficient optical coupling using an optical grating.

Disclosure of Invention

Embodiments of the present invention provide a method for communication that includes transmitting an optical signal between a semiconductor photonics die located on a substrate and an array of optical fibers attached to the substrate with at least one corresponding grating coupler on the semiconductor photonics die. Wherein each of the at least one grating coupler includes a plurality of coupling gratings, a waveguide, a cladding layer, a first reflective layer, and a second reflective layer. Wherein each of the plurality of coupling gratings comprises at least one step in a first lateral direction and extends in a second lateral direction. Wherein the first lateral direction and the second lateral direction are parallel to the surface of the substrate and perpendicular to each other in the grating plane. The first reflective layer is configured such that a plurality of coupling gratings is disposed between the first reflective layer and the cladding layer. Wherein the second reflective layer is configured such that the cladding layer is disposed between the second reflective layer and the waveguide.

Drawings

Various aspects of the disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that the various features are not drawn to scale. In fact, the dimensions and geometries of the various features may be arbitrarily increased or reduced for clarity of illustration.

Fig. 1 illustrates an exemplary block diagram of a device according to some embodiments of the present disclosure.

Fig. 2A illustrates a top view of an exemplary fiber-to-chip grating coupler, according to some embodiments of the present disclosure.

Fig. 2B illustrates a cross-sectional view of an exemplary grating coupler taken along the radial direction (a-a') shown in fig. 2A, according to some embodiments of the present disclosure.

FIG. 2C illustrates a cross-sectional view of an exemplary fiber-to-chip grating coupler taken along the direction B-B' shown in FIG. 2A, according to some embodiments of the present disclosure.

Fig. 3 illustrates a graph showing simulated Coupling Efficiency (CE) as a function of wavelength (λ) for the optical field from the grating coupler to the optical fiber illustrated in fig. 2A-2C, according to some embodiments of the present disclosure.

Fig. 4 illustrates a graph showing simulated Coupling Efficiency (CE) as a function of wavelength (λ) for the optical field from the fiber to the grating coupler illustrated in fig. 2A-2C, according to some embodiments of the present disclosure.

Fig. 5 illustrates a cross-sectional view of an exemplary fiber-to-chip grating coupler in a radial direction, according to some embodiments of the present disclosure.

Fig. 6 illustrates a cross-sectional view of an exemplary fiber-to-chip grating coupler in a radial direction, according to some embodiments of the present disclosure.

Fig. 7 illustrates a cross-sectional view of an exemplary fiber-to-chip grating coupler in a radial direction, according to some embodiments of the present disclosure.

Fig. 8 illustrates a cross-sectional view of an exemplary fiber-to-chip grating coupler in a radial direction, according to some embodiments of the present disclosure.

Fig. 9 illustrates a cross-sectional view of an exemplary fiber-to-chip grating coupler in a radial direction, according to some embodiments of the present disclosure.

FIG. 10 illustrates a cross-sectional view of an exemplary fiber-to-chip grating coupler taken along the direction B-B' shown in FIG. 2A, according to some embodiments of the present disclosure.

FIG. 11A shows a cross-sectional view of a portion of an exemplary grating in a fiber-to-chip grating coupler, taken along the direction B-B' shown in FIG. 2A, according to some embodiments of the present disclosure.

FIG. 11B shows a cross-sectional view of a portion of an exemplary grating in a fiber-to-chip grating coupler, taken along the direction B-B' shown in FIG. 2A, according to some embodiments of the present disclosure.

FIG. 11C illustrates a cross-sectional view of a portion of an exemplary grating in a fiber-to-chip grating coupler, taken along the direction B-B' shown in FIG. 2A, according to some embodiments of the present disclosure.

Figure 12 illustrates a flow diagram of a method of forming a grating coupler according to some embodiments of the present disclosure.

Fig. 13A-13F illustrate cross-sectional views of a grating coupler at various stages of a fabrication process according to some embodiments of the present disclosure.

[ description of symbols ]

100: a device;

102: electronic die/die;

104: light source die/die;

106: photonic die/die;

108: an optical fiber array;

110: an intermediary;

112: bonding by wire bonding;

114: a Printed Circuit Board (PCB) substrate;

116: through Silicon Vias (TSVs);

118. 1000, 1100: a fiber-to-chip grating coupler;

200. 500, 600, 800, 900: fiber-to-chip grating coupler/grating coupler;

202: a grating area;

204: periodic grating/L-shaped grating/sixth grating;

204A: a first grating;

204B: a second grating;

204C: a third grating;

204D: a fourth grating;

204E: a fifth grating;

204F: a sixth grating;

206. 212, 1010, 1012: a length;

208: an edge;

210: a waveguide/waveguide region;

214: a radius of curvature;

216: arc length/length;

220: an incident light field;

222. 258: an angle;

224: silicon substrate/semiconductor substrate/substrate;

226: silicon oxide layer/first dielectric layer/dielectric layer;

228: a silicon layer;

230. 232, 274, 606, 706, 710: thickness;

234. 502: step height/thickness;

236: trench depth/step height;

238. 604: trench depth/pillar height;

240. 242, 507: the width of the groove;

244. 508: pillar width/width;

246. 1102, 1112: fully etching the groove;

248. 1104, 1104A, 1104B: shallow etching the groove/shallow groove;

250. 514, 1106, 1116: a column;

252: an optical fiber;

254: an axis;

256: a y-axis;

260: core diameter;

262: a distance;

270: radiation field/light field;

272: cladding layer/silicon oxide cladding layer/second dielectric layer;

290: bottom reflective layer/first metal layer;

292: top reflective layer/second metal layer;

300. 400: a graph;

302. 402, a step of: simulated Coupling Efficiency (CE);

304. 404: wavelength (λ)/center wavelength;

306. 406: a bandwidth;

504: depth of the trench;

506: arc length/trench width;

510: deeply etching the groove;

512. 1114: shallow etching the groove;

602: a coating layer;

608: a width;

610: a first block/block;

612: a second block;

700: fiber-to-chip grating coupler/grating coupler;

702: a second cladding layer;

704: a first cladding layer;

802-A: the width of the first full-etched groove;

802-B: the width of the second fully etched groove;

802-C: the width of the third fully etched groove;

802-D: fourth, the width of the groove is fully etched;

802-E: the fifth is the width of the fully etched groove;

802-F: sixthly, fully etching the width of the groove;

804-A: a first shallow etch trench width;

804-B: a second shallow etch trench width;

804-C: a third shallow etch trench width;

804-D: a fourth shallow etch trench width;

804-E: a fifth shallow etch trench width;

804-F: a sixth shallow etch trench width;

806-A: a first pillar width;

806-B: a second column width;

806-C: a third pillar width;

806-D: a fourth column width;

806-E: a fifth column width;

806-F: a sixth column width;

808. 810: step height;

902-A, 902-B, 902-C: an L-shaped grating;

904-A, 904-B, 904-C: a rectangular grating;

910-A, 910-B, 910-C, 914-A, 914-B, 914-C: fully etching the width of the groove;

912-A, 912-B, 912-C, 916-A, 916-B, 916-C: the width of the column;

1002: a first step;

1002-A: slab/first slab;

1002-B: slab/second slab;

1004: a second step;

1004-A, 1004-B: a slab;

1006. 1008: a gap;

1020: a first length/length;

1022: a second length/length;

1024: a third length/length;

1026: a fourth length/length;

1110: fiber to chip grating coupling;

1118: an inclination angle;

1200: a method;

1202. 1204, 1206, 1210, 1208, 1212: operating;

1300: a grating coupler;

A-A ', B-B': a radial direction;

r: back reflection;

y, Z: and (4) direction.

Detailed Description

The following disclosure sets forth various exemplary embodiments for implementing different features of the inventive subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, it will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or one or more intervening elements may be present.

The coupling efficiency is the ratio of power coupled from a waveguide mode to a fiber mode (or from a light mode to a waveguide mode), and CE ═ 1-R) η can be utilized_dη_ovIs calculated, wherein eta_dIs directivity, eta_ovIs the optical field overlap and R is the back reflection. Directivity eta_dA portion of the power diffracted upwards is measured. Optical field overlap η_ovThe integral of overlap (overlap integral) between the diffraction field profile and the Gaussian fiber mode (Gaussian fiber mode) is measured, and the back reflection R measures the fraction of the power reflected back into the input port. Therefore, to improve coupling efficiency, directivity can be improved, overlap can be increased and a small refractive index contrast (reciprocal contrast) can be used to reduce back reflection. The present disclosure provides various embodiments of efficient fiber-to-chip grating couplers with high coupling efficiency.

Fig. 1 illustrates an exemplary block diagram of a device 100 according to some embodiments of the present disclosure. It should be noted that device 100 is merely an example and is not intended to limit the present disclosure. It is therefore to be understood that additional functional blocks may be provided in the device 100 shown in fig. 1 or may be coupled to the device 100 shown in fig. 1, and that some other functional blocks may only be briefly described herein.

Referring to fig. 1, device 100 includes an electronic die 102, a light source die 104, a photonics die 106, an interposer 110, and a Printed Circuit Board (PCB) substrate 114. Electronic die 102, light source die 104, and photonics die 106 are coupled together through input/output interfaces (not shown) on interposer 110. In some embodiments, interposer 110 is fabricated using silicon. In some embodiments, interposer 110 includes at least one of: interconnect lines, Through Silicon Vias (TSVs), and contact pads. In some embodiments, interposer 110 integrates all components including electronic die 102, light source die 104, and photonics die 106. In some embodiments, each of the dies 102/104/106 is coupled to the interposer 110 using a flip chip (controlled collapsed die chip connection, C4) interconnection method. In some embodiments, high density solder micro-bumps are used to couple die 102/104/106 to interposer 110. In addition, interposer 110 is coupled to PCB substrate 114 by wire bonds 112 or Through Silicon Vias (TSVs) 116 using solder balls. The TSVs 116 may include conductive paths that extend vertically through the interposer 110 and provide electrical connections between the electronic die 102 and the PCB substrate 114. In some embodiments, PCB substrate 114 may include support structures for device 100, and may include both insulating materials to isolate the device and conductive materials to provide electrical contact for active devices on photonic die 106 and circuits/devices on electronic die 102 via interposer 110. Additionally, the PCB substrate 114 may provide a thermal conduction path to carry away heat generated by devices and circuitry in the electronic die 102 and the light source die 104.

In some embodiments, the electronic die 102 includes circuitry (not shown) including amplifiers, control circuitry, digital processing circuitry, and the like. The electronic die 102 also includes at least one electronic circuit (not shown) that provides the required electronic functions of the device 100 as well as driver circuitry for controlling elements in the light source die 104 or photonics die 106.

In some embodiments, the light source die 104 includes a plurality of components (not shown), such as at least one light emitting element (e.g., a laser or a light emitting diode), a transmission element, a modulation element, a signal processing element, a switching circuit, an amplifier, an input/output coupler, and a light sensing/detection circuit. In some embodiments, each of the at least one light-emitting element in the light source die 104 may include a solid inorganic semiconductor material, an organic semiconductor material, or a combination of inorganic/organic hybrid semiconductor materials to generate light. In some embodiments, light source die 104 is located on photonics die 106.

In some embodiments, the photonics die 106 includes an optical fiber array 108, an optical interface, and a plurality of fiber-to-chip grating couplers 118. In some embodiments, the plurality of fiber-to-chip grating couplers 118 are configured to couple the photonics die 106 with the fiber array 108. In some embodiments, fiber array 108 includes a plurality of optical fibers and each of the plurality of optical fibers may be a single-mode (single-mode) or a multi-mode (multi-mode) optical fiber. In some embodiments, the fiber array 108 may be epoxied on the photonics die 106.

In some embodiments, photonic die 106 also includes components (not shown) such as laser drivers, digital control circuitry, photodetectors, waveguides, small form factor pluggable (SFP) transceivers, High-speed phase modulators (HSPMs), calibration circuitry, distributed Mach-Zehnder interferometers (MZIs), grating couplers, light sources (i.e., lasers), and so forth. Each of the plurality of fiber-to-chip grating couplers 118 is capable of coupling an optical signal between the fiber array 108 and a corresponding photodetector on the light source die 104 or the photonic die 106. The plurality of fiber-to-chip grating couplers 118 each include a plurality of gratings and waveguides whose design reduces refractive index contrast to reduce back reflection losses, providing improved coupling efficiency between fibers on corresponding waveguides, discussed in detail below in various embodiments of the present disclosure.

During operation, optical signals received from a remote server affixed to one end of the fiber array 108 may be coupled to corresponding photodetectors on the photonic die 106 through fiber-to-chip grating couplers 118 affixed to the other end of the fiber array 108. Alternatively, the optical signals received from the light source die 104 may be coupled to the fiber array 108 through a fiber-to-chip grating coupler 118, which may be further transmitted to a remote server.

Fig. 2A illustrates a top view of an exemplary fiber-to-chip grating coupler 200 according to some embodiments of the present disclosure. In some embodiments, a fiber-to-chip grating coupler (hereinafter "grating coupler") 200 includes a grating region 202 and a waveguide 210. The grating region 202 includes a plurality of periodic gratings 204. In the illustrated embodiment, the curve is an edge 208 of the plurality of gratings 204 in the grating coupler 200. In some embodiments, each grating 204 in a grating period has 3 edges 208 (i.e., 19 black curves for 6 gratings 204 in the grating region 202). Of course, this is merely an example and is not intended to be limiting. Any number of edges 208 in each grating 204 and any number of gratings 204 in the grating coupler 200 may be used and are within the scope of the present invention, which is discussed in further detail below (fig. 10).

In the illustrated embodiment, the grating coupler 200 scatters an incident light field 220 received from the waveguide 210 in a radial direction in a direction perpendicular to the grating 204, and the refractive index contrast between the waveguide 210 and the grating region 202 enhances the scattering from the grating 204. The plurality of periodic gratings 204 in the grating region 202 produce an exponentially decaying intensity distribution (exponentially decaying intensity profile) in the propagation direction along the radial direction at a given angle 222 with respect to one end of the grating coupler 200. The exponentially decaying intensity profile determines the position of the optical fibers (not shown) in the fiber array 108 atop the grating coupler 200 to efficiently couple the optical field from the chip to the optical fibers. In some embodiments, the number of periodic gratings 204 may be determined according to the shape, geometry, and material of the gratings and the desired operating wavelength range, which is discussed in detail below.

Referring to fig. 2A, grating region 202 and waveguide 210 include

lengths

206 and 212, respectively, in the radial direction. In some embodiments, the plurality of gratings 204 each include a radius of curvature 214 according to their position relative to the center "O" and an arc length 216. In some embodiments, each of the plurality of gratings 204 in the grating coupler 200 has no curvature, i.e., the gratings are straight and have the same length 216.

Fig. 2B illustrates a cross-sectional view of the exemplary grating coupler 200 taken along the radial direction (a-a') shown in fig. 2A, according to some embodiments of the present disclosure. In the illustrated embodiment, the grating coupler 200 fabricated on the silicon substrate 224 comprises a multi-layer structure including a bottom reflective layer 290, a silicon oxide layer 226, a silicon layer 228, and a top reflective layer 292.

In the illustrated embodiment, a silicon oxide layer 226 is fabricated on the silicon substrate 224 using chemical vapor deposition, physical vapor deposition, or the like. In some embodiments, silicon oxide layer 226 has a thickness of 500 nanometers to 3000 nanometers. In some embodiments, this layer may be made of other types of dielectric materials (e.g., Si) depending on the application₃N₄、SiO₂(e.g., quartz and glass), Al₂O₃And H₂O) instead.

In some embodiments, silicon layer 228 is deposited on silicon oxide layer 226 using chemical vapor deposition. In some embodiments, the silicon layer 228 is 270 nanometers thick. In some other embodiments, the thickness of the silicon layer 228 is in the range of 250 nanometers to 350 nanometers, depending on the application.

In some embodiments, the bottom reflective layer 290 includes at least one of: al, Cu, Ni, and combinations thereof. In some embodiments, the thickness of the bottom reflective layer 290 is in the range of 0.1 microns to 10 microns. In some embodiments, the top reflective layer 292 includes at least one of: al, Cu, Ni, and combinations thereof. In some embodiments, the thickness of the top reflective layer 292 is in the range of 0.1 microns to 10 microns. In some embodiments, the top reflective layer 292 covers only the waveguides 210. In some embodiments, the top reflective layer 292 is equal to or greater than 20 × 20 microns.

In some embodiments, the waveguide 210 comprises the same material used in the plurality of gratings 204. In some other embodiments, the waveguide 210 comprises a second material different from the material used in the plurality of gratings 204.

In the illustrated embodiment, low back reflection and high directivity are achieved using the plurality of gratings 204 that each include a double etched step L-shaped sidewall profile. In some embodiments, the sidewalls of each step are perpendicular to the substrate surface (i.e., the top surface of silicon oxide layer 226). In the illustrated embodiment, each of the plurality of gratings 204 includes a fully etched trench 246, a lightly etched trench 248, and a pillar 250 in the silicon layer 228. In some embodiments, the full etch trench 246 has a trench width 240 and a trench depth 238. In some embodiments, the trench depth 238 of the full etch trench 246 is equal to the thickness 232 of the silicon layer 228. In some embodiments, trench width 240 and depth 238 are equal to 50 nanometers and 270 nanometers. In some other embodiments, the trench width 240 of the fully etched trench 246 is in the range of 70 nanometers to 270 nanometers, depending on the application at which the wavelength of operation is different. In some embodiments, shallow etch trenches 248 have trench width 242 and trench depth 236. In some embodiments, trench depth 236 and trench width 242 are equal to 130 nanometers and 230 nanometers. In some other embodiments, the trench depth 236 and the trench width 242 of the shallow trench 248 are in the range of 70 to 270 nanometers and 100 to 200 nanometers, depending on the application at which the wavelength of operation is different. In some embodiments, the pillars 250 have a pillar height 238 and a pillar width 244. In some embodiments, both pillar height 238 and pillar width 244 are equal to 270 nanometers. In some other embodiments, the pillar height 238 and the pillar width 244 of the pillar 250 are in the range of 180 nanometers to 400 nanometers and in the range of 170 nanometers to 370 nanometers. In the illustrated embodiment, the shallow etch trenches 248 are located between the fully etched trenches 246 and the pillars 250 in one cycle 212. In some embodiments, in the radial direction, the grating region 202 has a length 206 and the waveguide 210 has a length 212.

In some embodiments, the grating coupler 200 is further covered by a cladding layer 272. In some embodiments, the cladding layer 272 comprises silicon oxide and has a thickness 274 from the top surface of the cladding layer 272 to the top surface of the underlying unpatterned silicon layer 228. In some embodiments, the cladding layer 272 has a thickness of 2 microns. In some embodiments, the thickness 274 of the cladding layer 272 may be in the range of 0.6 microns to 3 microns, depending on the application. In some embodiments, cladding layer 272 may comprise other types of dielectric materials, including polysilicon and silicon nitride, depending on the application. In some other embodiments, cladding layer 272 includes multiple layers having gradient indices (i.e., layers in cladding layer 272 have increasing refractive indices). In some embodiments, the thicknesses of the multiple layers may be adjusted individually depending on the application. It should be noted that this is merely an example, and that the optimized thickness of the cladding layer 272 is a function of the effective index (i.e., material properties) of the cladding layer in combination with the underlying gradient structure. Thus, any thickness of cladding layer 272 may be used to achieve optimized coupling efficiency at the desired wavelength, and such any thickness of cladding layer 272 is within the scope of the present disclosure.

In some embodiments, the radiated optical field 270 from the grating coupler 200 with an electric field orthogonal to the plane of incidence (i.e., transverse electric TE polarization) is collected by an optical fiber 252 having a core diameter 260. In some embodiments, the core of the optical fiber 252 is located a distance 262 from the center of its core to the top surface of the cladding 272. In some embodiments, the optical fiber 252 receives the optical field 270 at an angle 258 (between the axis 254 of the optical fiber 252 and a y-axis 256 that is perpendicular to the surface of the substrate). In some embodiments, angle 258 is 13.3 degrees. In some other embodiments, the angle 258 of the optical fiber 252 may be configured to be in the range of 5 degrees to 15 degrees, depending on the structural/geometric/material properties of the grating coupler 200 and cladding 272. In some embodiments, the optical fiber 252 may be a single mode optical fiber or a multimode optical fiber.

FIG. 2C illustrates a cross-sectional view of the exemplary fiber-to-chip grating coupler 200 taken along the direction B-B' shown in FIG. 2A, according to some embodiments of the present disclosure. The cross-sectional view shows that the L-shaped grating 204 in the silicon layer 228 in fig. 2B is continuous over the entire length 216. In the embodiment shown, the L-shaped grating 204 includes 2 etched steps, and each of the two steps has a

step height

234 and 236, respectively. In some embodiments, thickness 232 of silicon layer 228 is equal to the sum of

step heights

234 and 236. In some embodiments, the thickness 232 of the silicon layer 228 is 270 nanometers. In some other embodiments, the thickness 232 of the silicon layer may be in the range of 180 nanometers to 400 nanometers.

Fig. 3 illustrates a graph 300, the graph 300 illustrating simulated Coupling Efficiency (CE)302 as a function of wavelength (λ)304 for the optical field from grating coupler 200 to the optical fiber illustrated in fig. 2A-2C, according to some embodiments of the present disclosure. The grating coupler 200 used in the simulation was fabricated on a Semiconductor On Insulator (SOI) wafer with a thickness 230 of the silicon oxide layer 226 of 2 microns and a thickness 232 of the silicon layer 228 of 270 nanometers. The grating coupler 200 includes a waveguide region 210, the waveguide region 210 having a length 212 of 25 microns and an angle 222 of 45 degrees. Grating coupler 200 also includes grating region 202, grating region 202 having a length 206 of 100 microns. Grating 204 in grating region 202 has a period of 550 nanometers. Each of the gratings 204 includes a fully etched trench 246, a lightly etched trench 248, and a post 250. The fully etched trench 246 has a first trench depth of 270 nanometers and a first trench width of 50 nanometers; the shallow etch trench 248 has a second trench depth of 130 nm and a second trench width of 230 nm; and pillars 250 have a pillar height of 270 nanometers and a pillar width of 270 nanometers. The grating 204 is covered by a silicon oxide cladding layer 272 with a thickness 274 of 2 μm. The grating coupler 200 receives an optical field 270 from an optical fiber 252 located 10 microns from the top surface of the silica coated layer 272. In addition, an optical fiber 252 is positioned above the sixth grating 204 from the waveguide region 210. An incident optical field of TE polarization at a single wavelength and 1310 nm is provided to the waveguide 210. The wavelength dependent refractive index of materials (including air, silicon oxide) was obtained from SOI, CMOS metallic materials and used in simulations. In addition, in the simulation, a top reflective layer using a material (e.g., Cu) having a thickness of 1 micrometer and a bottom reflective layer using a material (e.g., Cu) having a thickness of 1 micrometer were used. When the optical field travels from the grating coupler 200 to the fiber, the simulated coupling efficiency 302 is-1.33 dB (73.6%) at the center wavelength 304 of 1310 nanometers and the bandwidth 306 of the grating coupler 200 is 50 nanometers.

Fig. 4 illustrates a graph 400, the graph 400 illustrating simulated Coupling Efficiency (CE)402 as a function of wavelength (λ)404 for the optical field from the fiber to grating coupler 200 illustrated in fig. 2A through 2C, according to some embodiments of the present disclosure. The grating coupler 200 used in the simulation was fabricated on an SOI wafer with a thickness 230 of the silicon oxide layer 226 of 2 microns and a thickness 232 of the silicon layer 228 of 270 nanometers. The grating coupler 200 includes a waveguide region 210, the waveguide region 210 having a length 212 of 25 microns and an angle 222 of 45 degrees. Grating coupler 200 also includes grating region 202, grating region 202 having a length 206 of 100 microns. Grating 204 in grating region 202 has a period of 550 nanometers. Each of the gratings 204 includes a fully etched trench 246, a lightly etched trench 248, and a post 250. The fully etched trench 246 has a first trench depth of 270 nanometers and a first trench width of 50 nanometers; the shallow etch trench 248 has a second trench depth of 130 nm and a second trench width of 230 nm; and pillars 250 have a pillar height of 270 nanometers and a pillar width of 270 nanometers. The grating 204 is covered by a silicon oxide cladding layer 272 with a thickness 274 of 2 μm. The grating coupler 200 receives an optical field 270 from an optical fiber 252 located 10 microns from the top surface of the silica coated layer 272. In addition, an optical fiber 252 is positioned above the sixth grating 204 from the waveguide region 210. An incident optical field of TE polarization at a single wavelength and 1310 nm is provided to the waveguide 210. The wavelength dependent refractive index of materials (including air, silicon oxide) was obtained from SOI, CMOS metallic materials and used in simulations. In addition, in the simulation, a top reflective layer using a material (e.g., Cu) having a thickness of 1 micrometer and a bottom reflective layer using a material (e.g., Cu) having a thickness of 1 micrometer were used. When the optical field travels from the fiber to the grating coupler 200, the simulated coupling efficiency 402 is-1 dB (79.4%) at the center wavelength 404 of 1280 nanometers and the bandwidth 406 is 145 nanometers.

Fig. 5 illustrates a cross-sectional view of an exemplary fiber-to-chip grating coupler 500 in a radial direction, according to some embodiments of the present disclosure. Of course, this is merely an example and is not intended to be limiting. Any number of gratings 204 in grating coupler 500 may be used and are within the scope of the present invention. In the illustrated embodiment, the plurality of gratings 204 in the fiber-to-chip grating coupler 500 are identical in cross-sectional view and may have different arc lengths 506, as shown in FIG. 2A. In the embodiment shown, each of the plurality of gratings 204 includes an etched-back trench 510, a shallow trench 512, and a post 514. In some embodiments, the deep etched trench 510 has a trench depth 504 and a trench width 506. In some embodiments, the trench depth 504 is less than the thickness 234 of the silicon layer 228. In some embodiments, the thickness 234 of the silicon layer 228 is 270 nanometers.

Fig. 6 illustrates a cross-sectional view of an exemplary fiber-to-chip grating coupler 600 in a radial direction, according to some embodiments of the present disclosure. Of course, this is merely an example and is not intended to be limiting. Any number of gratings 204 in grating coupler 600 may be used and are within the scope of the present invention. In the illustrated embodiment, the plurality of gratings 204 in the fiber-to-chip grating coupler 600 are identical in cross-sectional view and may have different arc lengths 206, as shown in fig. 2A. In the illustrated embodiment, each of the plurality of gratings 204 includes a fully etched trench 246, a lightly etched trench 248, and a post 250. In some embodiments, each of the plurality of gratings 204 includes a first block 610 and a second block 612, wherein the first block 610 is etched in the silicon layer 228 and the second block 612 is etched in the coating layer 602 on top of the silicon layer 228. In some embodiments, the coating layer 602 includes at least one material different from the silicon layer 228. In some embodiments, the coating layer 602 has a thickness 606. In some embodiments, the first block 610 has a width 608 and the second block 612 has a width 244. In some embodiments, the size and material properties of the block 610 are used to further reduce reflections.

Fig. 7 illustrates a cross-sectional view of an exemplary fiber-to-chip grating coupler 700 in a radial direction, according to some embodiments of the present disclosure. Of course, this is merely an example and is not intended to be limiting. Any number of gratings 204 in grating coupler 700 may be used and are within the scope of the present invention. In the illustrated embodiment, the plurality of gratings 204 in the fiber-to-chip grating coupler 700 are identical in cross-sectional view and may have different arc lengths 206, as shown in fig. 2A. In the illustrated embodiment, each of the plurality of gratings 204 includes a fully etched trench 246, a lightly etched trench 248, and a post 250. The fully etched trench 246 and the lightly etched trench 248 are filled with a first cladding layer 704. In some embodiments, first cladding layer 704 has a top surface that is coplanar with a top surface of silicon layer 228 after chemical-mechanical polishing (CMP). In some other embodiments, the top surface of the first cladding layer 704 may be at a higher or lower level than the surface of the silicon layer 228. In the illustrated embodiment, a second cladding layer 702 is deposited on the top surface of silicon layer 228 and first cladding layer 704. The second cladding layer has a thickness 710 from its top surface to the top surface of silicon layer 228. In some embodiments, first cladding layer 704 comprises a different material than the material in second cladding layer 702.

Fig. 8 illustrates a cross-sectional view of an exemplary fiber-to-chip grating coupler 800 in a radial direction, according to some embodiments of the present disclosure. Of course, this is merely an example and is not intended to be limiting. Any number of gratings 204 in grating coupler 800 may be used and are within the scope of the present invention. In the illustrated embodiment, each of the plurality of gratings 204 includes a fully etched trench 246, a lightly etched trench 248, and a post 250. In the illustrated embodiment, the plurality of gratings 204 in the fiber-to-chip grating coupler 800 are different sizes and may also have different arc lengths 206, as shown in FIG. 2A. In the illustrated embodiment, the multiple gratings 204 have the same step heights 808 and 810. For example, in the illustrated embodiment, the first grating 204A includes a first fully etched trench having a first fully etched trench width 802-A, a first shallow etched trench having a first shallow etched trench width 804-A, and a first pillar having a first pillar width 806-A; the second grating 204B includes a second fully etched trench having a second fully etched trench width 802-B, a second shallow etched trench having a second shallow etched trench width 804-B, and a second column having a second column width 806-B; the third grating 204C includes a third fully etched trench having a third fully etched trench width 802-C, a third shallow etched trench having a third shallow etched trench width 804-C, and a third pillar having a third pillar width 806-C; the fourth grating 204D includes a fourth fully etched trench having a fourth fully etched trench width 802-D, a fourth shallow etched trench having a fourth shallow etched trench width 804-D, and a fourth pillar having a fourth pillar width 806-D; the fifth grating 204E includes a fifth fully etched trench having a fifth fully etched trench width 802-E, a fifth shallow etched trench having a fifth shallow etched trench width 804-E, and a fifth pillar having a fifth pillar width 806-E; and the sixth grating 204F includes a sixth fully etched trench having a sixth fully etched trench width 802-F, a sixth shallow etched trench having a sixth shallow etched trench width 804-F, and a sixth pillar having a sixth pillar width 806-F.

In the illustrated embodiment, the sixth pillar width is greater than the fifth pillar width; the fifth column width is greater than the fourth column width; the fourth column width is greater than the third column width; the width of the third column is larger than that of the second column; and the second column width is greater than the first column width. In addition, the width of the sixth shallow etching groove is larger than that of the fifth shallow etching groove; the width of the fifth shallow etching groove is larger than that of the fourth shallow etching groove; the width of the fourth shallow etching groove is larger than that of the third shallow etching groove; the width of the third shallow etching groove is larger than that of the second shallow etching groove; and the width of the second shallow etching groove is larger than that of the first shallow etching groove. In addition, the width of the sixth fully etched groove is larger than that of the fifth fully etched groove; the width of the fifth full-etched groove is larger than that of the fourth full-etched groove; the width of the fourth fully etched groove is larger than that of the third fully etched groove; the width of the third fully etched groove is larger than that of the second fully etched groove; and the width of the second fully etched trench is greater than the width of the first fully etched trench. In the illustrated embodiment, the full etch trench depth, shallow etch trench depth, and post height of the 6 gratings 204 (i.e., 204A, 204B, 204C, 204D, 204E, and 204F) are constant. It should be noted that this is merely an example and is not intended to be limiting. Any combination of gratings with different geometric dimensions (i.e., depth and width) in any order may be used in conjunction with material properties and wavelength ranges to achieve desired performance (e.g., center wavelength, coupling efficiency, bandwidth, etc.), which are within the scope of the present invention.

Fig. 9 illustrates a cross-sectional view of an exemplary fiber-to-chip grating coupler 900 in a radial direction, according to some embodiments of the present disclosure. Of course, this is merely an example and is not intended to be limiting. Any number of gratings 204 in grating coupler 900 may be used and are within the scope of the present invention. In the embodiment shown, there are 3L-shaped gratings 902 (i.e., 902-A, 902-B, and 902-C) with two etched steps as discussed in detail in FIG. 2B, and 3 rectangular gratings 804 (i.e., 904-A, 904-B, and 904-C). In some embodiments, the 3 rectangular gratings 904 include fully etched trenches 906 and posts 908. Each of the fully etched trenches 906 has a fully etched trench width 914 and each of the pillars 908 has a pillar width 916. In some embodiments, the full etched trench width 914 is equal to the full etched trench width 910 of the L-shaped grating 902 and the pillar width 916 is equal to the pillar width 912 of the L-shaped grating 902. It should be noted that this is merely an example and is not intended to be limiting. Any combination of gratings having different shapes and geometries may be used to tune the coupling performance (e.g., center wavelength, bandwidth, coupling efficiency, etc.), and any combination of such gratings is within the scope of the present invention.

FIG. 10 illustrates a cross-sectional view of an exemplary fiber-to-chip grating coupler 1000 taken along the direction B-B' shown in FIG. 2A, according to some embodiments of the present disclosure. In the embodiment shown, the L-shaped grating 204 includes 2 etched steps (i.e., a first step 1002 and a second step 1004), and each of the two steps has a

step height

step heights

234 and 236. In some embodiments, the thickness 232 of the silicon layer 228 is 270 nanometers. In the illustrated embodiment, the first step 1002 having the step height 234 is discontinuous in the B-B' direction and includes 2 slabs (slab) 1002-A/1002-B. The first slab 1002-a of the first step 1002 has a first length 1020 and the second slab 1002-B of the first step 1002 has a second length 1022. Similarly, the second step 1004 having a step height 236 is discontinuous in the B-B' direction and includes 2 slabs 1004-A/1004-B. The first slab 1004-B of the second step 1004 has a third length 1024 and the second slab 1004-B of the second step 1004 has a fourth length 1026. In the illustrated embodiment, first length 1020, second length 1022, third length 1024, and fourth length 1026 are different. In the embodiment shown, the two slabs in the first and second steps are separated by

respective gaps

1006 and 1008. In some embodiments, the 4 lengths 1020/1022/1024/1026 may have the same length. It should be noted that this is merely an example and is not intended to be limiting. It is within the scope of the present disclosure that each of the 2 steps may comprise any number of slabs at any location on the grating, and that the plurality of slabs in the grating may comprise different lengths.

FIG. 11A shows a cross-sectional view of a portion of an exemplary grating 204 in a fiber-to-chip grating coupler 1100, taken along the direction B-B' shown in FIG. 2A, according to some embodiments of the present disclosure. In the embodiment shown, each of the gratings comprises 3 steps, including a fully etched

trench

1102, 2 shallow etched trenches 1104 (i.e., 1104A and 1104B), and a post 1106. In the illustrated embodiment, the depth of shallow etch trenches 1104A is greater than the depth of shallow etch trenches 1104B. In addition, the two

shallow etch trenches

1104A and 1104B are located between the fully etched trench 1102 and the post 1106. It should be noted that this is merely an example and is not intended to be limiting. Any number of steps having dimensions (i.e., width and height) may be used depending on the material properties and desired operating wavelength and are within the scope of the present invention.

FIG. 11B shows a cross-sectional view of a portion of an exemplary grating 204 in the fiber-to-chip grating coupler 1100, taken along the direction B-B' shown in FIG. 2A, according to some embodiments of the present disclosure. In the illustrated embodiment, each of the gratings 204 includes a fully etched

trench

1102, 2 shallow etched

trenches

1104A and 1104B, and a post 1106. In the illustrated embodiment, the depth of shallow etch trenches 1104A is greater than the depth of shallow etch trenches 1104B. Additionally, a post 1106 is located between the two shallow etch trenches 1104A/1104B. It should be noted that this is merely an example and is not intended to be limiting. Any number of steps having dimensions (i.e., width and height) may be used depending on the material properties and desired operating wavelength and are within the scope of the present invention. In addition, any order of combination of trenches and pillars having different geometries is within the scope of the present invention.

FIG. 11C illustrates a cross-sectional view of a portion of an exemplary grating 204 in a fiber-to-chip grating coupler 1110 taken along the direction B-B' shown in FIG. 2A, according to some embodiments of the present disclosure. In the embodiment shown, each of the gratings is a 2-step sloped grating having fully etched trenches 1112, shallow etched trenches 1114, and pillars 1116, wherein the fully etched trenches 1112, shallow etched trenches 1114, and pillars 1116 each include sidewalls having an angle of inclination 1118 with respect to the surface of the underlying silicon oxide layer. It should be noted that this is merely an example and is not intended to be limiting. Any number of steps having dimensions (i.e., width, height, and tilt angle) may be used depending on the material properties and desired operating wavelength and are within the scope of the present invention. In addition, any order of combination of trenches and pillars having different geometries is within the scope of the present invention.

It should be noted that two or more methods may be combined to further tailor the coupling performance used in the exemplary grating structures shown in fig. 2A-2C and fig. 5-11C. For example, a fiber-to-chip grating coupler includes multiple gratings, and the multiple gratings may include different geometric dimensions and/or configure the number of steps with a sub-period. By way of further example, a fiber-to-chip grating coupler may comprise a plurality of multi-layered gratings, wherein each of the plurality of multi-layered gratings comprises a plurality of steps, wherein each of the plurality of steps comprises a different material. For another example, a fiber-to-chip grating coupler may comprise a plurality of gratings, and each of the plurality of gratings comprises a plurality of slabs, wherein a length of the each of the plurality of slabs is equal to a grating period. By way of further example, the fiber-to-chip grating coupler may include a plurality of tilted gratings having a plurality of steps, wherein the plurality of slab gratings are filled with a plurality of cladding layers.

Figure 12 illustrates a flow diagram of a method 1200 of forming the grating coupler 200 according to some embodiments of the present disclosure. It should be noted that the method 1200 is merely an example and is not intended to limit the present disclosure. Accordingly, it should be understood that additional operations may be provided before, during, and after the method 1200 shown in fig. 12, and that some other operations may only be briefly described herein. In some embodiments, the operations of the method 1200 may be associated with cross-sectional views of the semiconductor device at various stages of fabrication as shown in fig. 13A-13F, respectively, which will be discussed in further detail below.

Referring now to fig. 12, method 1200 begins with operation 1202, in which a first metal layer 290 is deposited on a semiconductor substrate 224, according to some embodiments. In some embodiments, the first metal layer 290 acts as a bottom reflective layer 290 to reflect transmitted light from the grating back into the grating. In some embodiments, semiconductor substrate 224 is a silicon substrate. Alternatively, the semiconductor substrate 224 may comprise other elemental semiconductor materials, such as, for example, germanium. The semiconductor substrate 224 may also include compound semiconductors such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. The semiconductor substrate 224 may comprise an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In some embodiments, first metal layer 290 includes at least one of: al, Cu, Ni, and combinations thereof. In some embodiments, the thickness of first metal layer 290 is in the range of 0.1 microns to 10 microns. In some embodiments, first metal layer 290 is formed on semiconductor substrate 224 utilizing one of the following techniques: chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), evaporation, and the like. In some embodiments, the semiconductor substrate 224 is first cleaned using an RCA cleaning process.

The method 1200 continues with operation 1204 in which a first dielectric layer 226 is deposited over the first metal layer 290 on the semiconductor substrate 224. In some embodiments, the process of depositing the silicon oxide layer 226 on the first metal layer 290 on the semiconductor substrate 224 includes thermal oxidation, spin coating, physical vapor deposition, chemical vapor deposition, and the like. In some other embodiments, silicon oxide layer 226 may be formed by a process such as separation by implanted oxygen (SIMOX) or other suitable techniques (e.g., wafer bonding and grinding). In some other embodiments, the dielectric layer 226 may be a variety of dielectric materials depending on the applicationMaterial comprising aluminum oxide (Al)₂O₃) Hafnium oxide (HfO)₂) Lanthanum oxide (La)₂O₃) Zirconium oxide (ZrO)₃) Beryllium strontium titanium oxide (Ba-Sr-Ti-O), silicon nitride (Si)₃N₄) And stacks of mixtures thereof. In some embodiments, the silicon oxide layer 226 has a thickness of 500 nanometers to 3000 nanometers.

The method 1200 continues with operation 1206, where a silicon layer 228 is formed on the first dielectric layer 226, according to some embodiments. In some embodiments, silicon layer 228 comprises polysilicon. In some embodiments, the doped polysilicon may be deposited using a Chemical Vapor Deposition (CVD) process. In some embodiments, the silicon layer 228 is 270 nanometers thick. In some other embodiments, the thickness of the silicon layer 228 is in the range of 250 nanometers to 350 nanometers, depending on the application.

The method 1200 continues with operation 1208, where the silicon layer 228 is patterned to generate a plurality of gratings 204, according to some embodiments. In the illustrated embodiment, low back reflection and high directivity are achieved using the plurality of gratings 204 that each include a double etched step L-shaped sidewall profile. In some embodiments, the sidewalls of each step are perpendicular to the substrate surface (i.e., the top surface of silicon oxide layer 226). In the illustrated embodiment, each of the plurality of gratings 204 includes a fully etched trench 246, a lightly etched trench 248, and a pillar 250 in the silicon layer 228. In some embodiments, the full etch trench 246 has a trench width 240 and a trench depth 238. In some embodiments, the trench depth 238 of the full etch trench 246 is equal to the thickness 232 of the silicon layer 228. In some embodiments, trench width 240 and depth 238 are equal to 50 nanometers and 270 nanometers. In some other embodiments, the trench width 240 of the fully-etched trench 246 is in the range of 70 nanometers to 270 nanometers, depending on the application having a different operating wavelength. In some embodiments, shallow etch trenches 248 have trench width 242 and trench depth 236. In some embodiments, trench depth 236 and trench width 242 are equal to 130 nanometers and 230 nanometers. In some other embodiments, the trench depth 236 and the trench width 242 of the shallow trench 248 are in the range of 70 to 270 nanometers and 100 to 200 nanometers, depending on the application having different operating wavelengths. In some embodiments, the pillars 250 have a pillar height 238 and a pillar width 244. In some embodiments, both pillar height 238 and pillar width 244 are equal to 270 nanometers. In some other embodiments, the pillar height 238 and the pillar width 244 of the pillar 250 are in the range of 180 nanometers to 400 nanometers and 170 nanometers to 370 nanometers. In the illustrated embodiment, the shallow etch trenches 248 are located between the fully etched trenches 246 and the pillars 250 in one cycle 212. In some embodiments, in the radial direction, the grating region 202 has a length 206 and the waveguide 210 has a length 212.

The method 1200 continues with operation 1210 in which a second dielectric layer 272 is deposited atop the patterned silicon layer 228, according to some embodiments. In some embodiments, the second dielectric layer 272 is a cladding layer. In some embodiments, the second dielectric layer 272 comprises silicon oxide and has a thickness 274 from its top surface to the top surface of the underlying unpatterned silicon layer 228. In some embodiments, the thickness of the second dielectric layer 272 is 2 microns. In some embodiments, the thickness 274 of the second dielectric layer 272 may be in the range of 0.6 microns to 3 microns, depending on the application. In some embodiments, the second dielectric layer 272 may comprise other types of dielectric materials, including polysilicon and silicon nitride, depending on the application. In some other embodiments, the second dielectric layer 272 includes a plurality of layers having a gradient index (i.e., the refractive index of the layers in the second dielectric layer 272 increases). In some embodiments, the thicknesses of the multiple layers may be adjusted individually depending on the application. It should be noted that this is merely an example, and that the optimized thickness of the second dielectric layer 272 is a function of its effective index (i.e., material properties) in combination with the underlying gradient structure. Accordingly, any thickness of the second dielectric layer 272 may be used to achieve optimized coupling efficiency at a desired wavelength, and such any thickness of the second dielectric layer 272 is within the scope of the present disclosure.

In some embodiments, the second dielectric layer 272 is further polished to create a planar surface. In some embodiments, the second dielectric layer 272 is polished using a Chemical Mechanical Polishing (CMP) process.

The method 1200 continues with operation 1212, in which a second metal layer 292 is formed on the polished surface of the second dielectric layer 272, according to some embodiments. In some embodiments, the second metal layer 292 is a top reflective layer. In some embodiments, the second metal layer 292 includes at least one of: al, Cu, Ni, and combinations thereof. In some embodiments, the thickness of the second metal layer 292 is in the range of 0.1 microns to 10 microns. In some embodiments, the second metal layer 292 covers only the waveguides 210. In some embodiments, the second metal layer 292 is equal to or greater than 20 x 20 microns. In some embodiments, the second metal layer 292 is deposited utilizing one of the following techniques: PVD and CVD. In some embodiments, the second metal layer 292 is further patterned using one or more patterning processes (e.g., photolithography processes, dry/wet etch processes, soft/hard bake processes, cleaning processes, etc.) to form a top reflective layer at specified locations relative to the plurality of gratings 204.

As described above, fig. 13A to 13F illustrate in cross-section a portion of a grating coupler 1300 having the plurality of periodic gratings 204 and the waveguide 210 shown in fig. 1. Fig. 13A through 13F are simplified to better understand the concepts of the present disclosure. Although the figures illustrate the grating coupler 1300, it should be understood that the grating coupler 1300 may include many other devices that are not shown in fig. 13A-13F for clarity of illustration.

Fig. 13A is a cross-sectional view of a grating coupler 1300 including a semiconductor substrate 224 according to some embodiments of the present disclosure. In some embodiments, semiconductor substrate 224 comprises a silicon substrate. Alternatively, the semiconductor substrate 224 may comprise other elemental semiconductor materials, such as, for example, germanium. The semiconductor substrate 224 may also include compound semiconductors such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. The semiconductor substrate 224 may comprise an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide.

Fig. 13B is a cross-sectional view of a grating coupler 1300 including the deposition of a first metal layer 290, a first dielectric layer 226, and a silicon layer 228, according to some embodiments of the present disclosure. In some embodiments, first metal layer 290 includes at least one of: al, Cu, Ni, and combinations thereof. In some embodiments, the thickness of first metal layer 290 is in the range of 0.1 microns to 10 microns.

In some embodiments, the process of depositing the silicon oxide layer 226 on the first metal layer 290 on the semiconductor substrate 224 includes thermal oxidation, spin coating, physical vapor deposition, chemical vapor deposition, and the like. In some other embodiments, silicon oxide layer 226 may be formed by a process such as implanted oxygen Separation (SIMOX) or other suitable techniques such as wafer bonding and grinding. In some other embodiments, the dielectric layer 226 may be a variety of dielectric materials, including aluminum oxide (Al), depending on the application₂O₃) Hafnium oxide (HfO)₂) Lanthanum oxide (La)₂O₃) Zirconium oxide (ZrO)₃) Beryllium strontium titanium oxide (Ba-Sr-Ti-O), silicon nitride (Si)₃N₄) And stacks of mixtures thereof. In some embodiments, the silicon oxide layer 226 has a thickness of 500 nanometers to 3000 nanometers.

In some embodiments, silicon layer 228 comprises polysilicon. In some embodiments, the doped polysilicon may be deposited using a Chemical Vapor Deposition (CVD) process. In some embodiments, the silicon layer 228 is 270 nanometers thick. In some other embodiments, the thickness of the silicon layer 228 is in the range of 250 nanometers to 350 nanometers, depending on the application.

Fig. 13C is a cross-sectional view of the grating coupler 1300 including patterning the silicon layer 228 with a first photoresist layer (not shown) at one of various stages of fabrication corresponding to operation 1208 shown in fig. 12, in accordance with some embodiments of the present disclosure. In some embodiments, the first photoresist layer may comprise a negative photoresist layer or a positive photoresist layer that may be patterned in response to a lithographic light source. In some alternative embodiments, the first photoresist layer may comprise an electron beam (e-beam) resist layer (e.g., polymethylmethacrylate, methyl methacrylate, etc.) that is patternable in response to an electron beam lithography energy source. In some embodiments, a first photoresist layer is formed over silicon layer 228 utilizing a deposition process known in the art (e.g., spin coating, spray coating, dip coating, roll coating, etc.). The first photoresist layer is then patterned in a photolithography process, which may involve various exposure, development, baking, stripping, etching, and rinsing processes. Thus, the opening in the first patterned photoresist layer is formed such that at least a portion of the top surface of the silicon layer 228 is exposed.

In some embodiments, the exposed silicon layer 228 at the opening is etched using the first photoresist layer as a mask. In some embodiments, the silicon layer 228 exposed at the opening of the first photoresist layer is etched using a dry etch process, such as plasma enhanced Deep Reactive Ion Etching (DRIE), based on an appropriate chemistry depending on the material of the silicon layer 228. In some embodiments, after etching the silicon layer 228, the first photoresist layer may be removed by one or more chemical cleaning processes using acetone, 1-Methyl-2-pyrrolidone (NMP), dimethyl sulfoxide (DMSO), or other suitable removal chemistries. In some embodiments, it may be desirable to heat the chemistry used to a temperature above room temperature to effectively dissolve the first patterned photoresist layer. The choice of the removal agent is determined by the type and chemical structure of the first photoresist layer, the silicon layer 228, and the first dielectric layer 226, the first metal layer 290, and the substrate 224 to ensure chemical compatibility of these layers with the chemical cleaning process. In some embodiments, this cleaning process is followed by a rinsing process with isopropyl alcohol or the like, followed by a rinsing with deionized water.

Fig. 13D is a cross-sectional view of the grating coupler 1300 including patterning the silicon layer 228 on the substrate 224 with a second photoresist layer (not shown) at one of the various stages of fabrication corresponding to operation 1208 shown in fig. 12, in accordance with some embodiments of the present disclosure. In some embodiments, the etched silicon layer 228 is further etched to generate a stepped ("L" -shaped) profile.

Fig. 13E is a cross-sectional view of the grating coupler 1300 including filling the etched silicon layer 228 with the second dielectric layer 272 at one of the various stages of fabrication corresponding to operation 1210 of fig. 12, in accordance with some embodiments of the present disclosure. In some embodiments, the second dielectric layer272 contain materials of at least one of the following materials, including: silicon oxide, low dielectric constant (low-k) materials, other suitable dielectric materials, or combinations thereof. The low dielectric constant material may include Fluorinated Silica Glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), carbon-doped silicon oxide (SiO)_xC_y)、

(Black

) (Applied Materials of Santa Clara, Calif.), xerogel, aerogel, amorphous carbon fluoride, parylene, bis-benzocyclobutene (BCB), SiLK (Dow Chemical, Midland, Mich.), polyimide, and/or other future-developed low-k dielectric Materials.

The second dielectric layer 272 may be formed by various processes including depositing the second dielectric layer using PVD, CVD, or the like. The thickness of the second dielectric layer 272 is controlled by the desired effective index of refraction, which is a function of the dielectric constants of the second dielectric layer 272 and the silicon layer 228, as well as the dimensions of the grating 204.

Fig. 13F is a cross-sectional view of the grating coupler 1300 including polishing the second dielectric layer 272, depositing the second metal layer 292, and patterning the second metal layer 292 at one of the various stages of fabrication corresponding to operations 1210-1212 shown in fig. 12, in accordance with some embodiments of the present disclosure. In some embodiments, the second dielectric layer 272 is polished using a chemical-mechanical planarization (CMP) process, which is a typical planarization process. CMP utilizes chemical slurry formulations and mechanical polishing processes to remove unwanted conductive or dielectric materials on the substrate to achieve a near perfect planar and smooth surface. Due to the nature of this cleaning process, various contaminants from the slurry (e.g., trace metals, mobile ions, and organic species) as well as abrasives (e.g., silicon dioxide and aluminum oxide) may be introduced to the substrate surface. In addition, the grating coupler 1300 with the filled trenches in the silicon layer 228 is cleaned to remove contaminants and materials from the substrate after CMP and to reduce slurry residue to a desired minimum level to potentially maximize device yield. In some embodiments, the top surface of the second dielectric layer 272 is coplanar, as shown in fig. 13F.

In some embodiments, the patterning of the second metal layer 292 is performed using a third photolithography process. Thus, in some embodiments, a patterned photoresist layer is formed after a conventional patterning (e.g., photolithography) process to align with at least a portion of the grating region to allow the second reflective pattern to couple with the grating to improve coupling efficiency.

In one embodiment, a method for communication includes: transmitting an optical signal between a semiconductor photonics die located on a substrate and an array of optical fibers attached to the substrate with at least one corresponding grating coupler on the semiconductor photonics die, wherein the at least one grating coupler each comprises a plurality of coupling gratings, a waveguide, a cladding layer, a first reflective layer, and a second reflective layer, wherein the plurality of coupling gratings each comprise at least one step in a first lateral direction and extend in a second lateral direction, wherein the first lateral direction and the second lateral direction are parallel to a surface of the substrate and perpendicular to each other in a grating plane, wherein the first reflective layer is configured such that the plurality of coupling gratings is disposed between the first reflective layer and the cladding layer, wherein the second reflective layer is configured such that the cladding layer is disposed between the second reflective layer and the waveguide.

In some embodiments, the waveguide includes a first optical medium having a first thickness, wherein the first optical medium is silicon and the first thickness is in a range of 250 nanometers to 350 nanometers. In some embodiments, the plurality of coupling gratings each comprise at least one first trench, at least one second trench, and at least one post. In some embodiments, the first depth of the at least one first trench is in a range of 250 nanometers to 350 nanometers. In some embodiments, the second depth of the at least one second trench is less than the first thickness. In some embodiments, a height of the at least one pillar is equal to the first depth of the at least one first trench. In some embodiments, the plurality of coupling gratings is filled with the cladding layer, wherein the cladding layer comprises a second optical medium and a first continuous planar surface. In some embodiments, the first reflective layer and the second reflective layer each comprise at least one of: copper, nickel and aluminum. In some embodiments, the transmitting further comprises at least one of: the optical signal is received from the corresponding coupling grating at a first angle, and the optical signal is transmitted to the corresponding coupling grating at the first angle. Wherein the array of optical fibers comprises at least one optical fiber. Wherein the first angle is measured between an axis of the optical fiber array and a direction perpendicular to the grating plane. Wherein the first angle is 13.3 degrees.

In another embodiment, a system for communication includes: a semiconductor photonics die, comprising: at least one grating coupler located on the semiconductor photonics die to transmit optical signals between the semiconductor photonics die located on a substrate and an array of optical fibers attached to the substrate, wherein the at least one grating coupler each comprises a plurality of coupling gratings, a waveguide, a cladding layer, a first reflective layer, and a second reflective layer, wherein the plurality of coupling gratings each comprise at least one step in a first lateral direction and extend in a second lateral direction, wherein the first lateral direction and the second lateral direction are parallel to a surface of the substrate and perpendicular to each other in a grating plane, wherein the first reflective layer is configured such that the plurality of coupling gratings is disposed between the first reflective layer and the cladding layer, wherein the second reflective layer is configured such that the cladding layer is disposed between the second reflective layer and the waveguide.

In some embodiments, the plurality of coupling gratings each comprise at least one first trench, at least one second trench, and at least one post. In some embodiments, the first depth of the at least one first trench is in a range of 250 nanometers to 350 nanometers. In some embodiments, the second depth of the at least one second trench is less than the first thickness. In some embodiments, a height of the at least one pillar is equal to the first depth of the at least one first trench. In some embodiments, the plurality of coupling gratings is filled with the cladding layer, wherein the cladding layer comprises a second optical medium and a first continuous planar surface. In some embodiments, the first reflective layer and the second reflective layer each comprise at least one of: copper, nickel and aluminum. In some embodiments, the second reflective layer is deposited in a first region on the first planar surface of the cladding layer, wherein the first region is vertically above the waveguide.

However, in another embodiment, an apparatus for optical coupling includes: a plurality of coupling gratings, wherein each of the plurality of coupling gratings comprises at least one step in a first lateral direction and extends in a second lateral direction, wherein the first and second lateral directions are parallel to a surface of the substrate and perpendicular to each other in a grating plane; a waveguide comprising a first optical medium having a first thickness; a cladding layer, wherein the cladding layer comprises a second optical medium and a first continuous planar surface; a first reflective layer, wherein the first reflective layer is configured such that the plurality of coupling gratings is disposed between the first reflective layer and the cladding layer; and a second reflective layer, wherein the second reflective layer is configured such that the cladding layer is disposed between the second reflective layer and the waveguide.

In some embodiments, the first optical medium is silicon and the first thickness is in a range of 250 nanometers to 350 nanometers. In some embodiments, the plurality of coupling gratings each comprise at least one first trench, at least one second trench, and at least one post. Wherein the first depth of the at least one first trench is in a range of 250 nanometers to 350 nanometers. Wherein a second depth of the at least one second trench is less than the first thickness. Wherein a height of the at least one pillar is equal to the first depth of the at least one first trench.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for communication, comprising:

transmitting an optical signal between a semiconductor photonics die located on a substrate and an array of optical fibers attached to the substrate with at least one corresponding grating coupler on the semiconductor photonics die, wherein the at least one grating coupler each comprises a plurality of coupling gratings, a waveguide, a cladding layer, a first reflective layer, and a second reflective layer, wherein the plurality of coupling gratings each comprise at least one step in a first lateral direction and extend in a second lateral direction, wherein the first lateral direction and the second lateral direction are parallel to a surface of the substrate and perpendicular to each other in a grating plane, wherein the first reflective layer is configured such that the plurality of coupling gratings is disposed between the first reflective layer and the cladding layer, wherein the second reflective layer is configured such that the cladding layer is disposed between the second reflective layer and the waveguide.