CN110649038A - Array substrate, display device and preparation method of array substrate - Google Patents
Array substrate, display device and preparation method of array substrate Download PDFInfo
- Publication number
- CN110649038A CN110649038A CN201910862548.XA CN201910862548A CN110649038A CN 110649038 A CN110649038 A CN 110649038A CN 201910862548 A CN201910862548 A CN 201910862548A CN 110649038 A CN110649038 A CN 110649038A
- Authority
- CN
- China
- Prior art keywords
- layer
- common electrode
- array substrate
- thin film
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 59
- 238000002360 preparation method Methods 0.000 title claims description 16
- 239000010409 thin film Substances 0.000 claims abstract description 32
- 229910052751 metal Inorganic materials 0.000 claims abstract description 30
- 239000002184 metal Substances 0.000 claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 23
- 238000002161 passivation Methods 0.000 claims description 16
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 239000010408 film Substances 0.000 abstract description 8
- 230000002159 abnormal effect Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 126
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000005265 energy consumption Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 230000005856 abnormality Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0416—Control or interface arrangements specially adapted for digitisers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Manufacturing & Machinery (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The array substrate comprises a thin film transistor device layer, a first flat layer, a metal layer, a second flat layer, a common electrode, a first through hole and a second through hole. The common electrode comprises a first common electrode and a second common electrode, the first common electrode is in contact with the metal layer through a first through hole, the second through hole penetrates through the first flat layer and the second flat layer, and the second common electrode is in contact with the drain electrode of the thin film transistor device layer through a second through hole. The first via hole and the second via hole are formed by etching through the same photomask, so that switching among all film layers in the array substrate is reduced, the problem of abnormal switching is reduced, the production process is simplified, and the production cost is reduced.
Description
Technical Field
The disclosure relates to the field of display technologies, and in particular, to an array substrate, a display device, and a method for manufacturing the array substrate.
Background
With the rapid development of display technology, the variety of display devices is becoming more and more, and display panels have been widely used in various fields in people's lives. Especially with the advent of touch screens. Touch screens have been spread throughout various aspects of people's lives.
At present, in the preparation process of the display panel, a plurality of passes of exposure treatment are required, and each additional process increases the overall manufacturing difficulty. With the appearance of touch display screens, the process flow is further increased, so that the existing preparation process becomes more complex. In the existing process of manufacturing a touch screen, a touch electrode needs to be manufactured, the touch electrode is connected with a common electrode, and the common electrode is controlled by transmitting signals through the touch electrode. In the existing design, the common electrode is connected with the touch electrode and the third metal layer through the via holes, and the third metal layer is connected with the source electrode or the drain electrode of the thin film transistor through the corresponding via holes, so that the purpose of connecting the common electrode with the source electrode or the drain electrode of the thin film transistor is realized through the multi-switching conduction mode. And when one through hole is added, a corresponding photomask etching process needs to be added, so that the production energy consumption and the production cost of the display panel are increased.
In summary, in the conventional display panel manufacturing process, multiple exposure processes are required, and meanwhile, the conductive connection manner of multiple switching on the device connection further increases the process flow, increases the production energy consumption and production cost of the display panel, and is not beneficial to process simplification.
Disclosure of Invention
The invention provides an array substrate, a display device and a preparation method of the array substrate, and aims to solve the problems that in the existing preparation process of the array substrate, exposure and etching processes are multiple, the process flow is complex, the preparation and production energy consumption of the display device is high, the production cost is high and the like.
To solve the above technical problem, the technical solution provided by the embodiment of the present disclosure is as follows:
according to a first aspect of the embodiments of the present disclosure, there is provided an array substrate, including:
a substrate;
a thin film transistor device layer disposed on the substrate;
a first planar layer disposed on the thin film transistor device layer;
a metal layer disposed on the first planarization layer;
a second planar layer disposed on the first planar layer and the metal layer; and
a common electrode disposed on the second planarization layer;
the common electrode is electrically connected with the metal layer through a first through hole, and the common electrode is also electrically connected with a drain electrode of a thin film transistor in the thin film transistor device layer through a second through hole.
According to an embodiment of the present disclosure, the first via is disposed through the first planarization layer, and the second via is disposed through the first planarization layer and the second planarization layer.
According to an embodiment of the present disclosure, the first via hole and the second via hole are formed by the same photo-masking process.
According to an embodiment of the present disclosure, the method further comprises:
a passivation layer disposed on the common electrode and the second planarization layer;
the pixel electrode is arranged on the passivation layer, the pixel electrode is electrically connected with the common electrode through a third through hole, and the third through hole penetrates through the passivation layer.
According to an embodiment of the present disclosure, the common electrode includes a first common electrode and a second common electrode, the first common electrode is electrically connected to the metal layer through the first via hole, and the second common electrode is electrically connected to the drain electrode in the thin film transistor device layer through the second via hole.
According to an embodiment of the present disclosure, the touch layer further includes a touch electrode, and the metal layer includes a touch data signal line.
According to a second aspect of the embodiments of the present disclosure, there is also provided a display device including the array substrate provided by the embodiments of the present disclosure.
According to a third aspect of the embodiments of the present disclosure, there is provided a method for manufacturing an array substrate, including the steps of:
s100: providing a substrate, and preparing a thin film transistor device layer on the substrate;
s200: coating a first flat layer on the thin film transistor device layer, and preparing a metal layer on the first flat layer;
s300: preparing a second flat layer on the first flat layer, and etching the first flat layer and the second flat layer by using the same photomask to form through holes;
s400: and preparing a common electrode layer, a passivation layer and a pixel electrode on the second flat layer, and forming the array substrate. According to an embodiment of the present disclosure, the via hole includes a first via hole and a second via hole, the first via hole penetrates through the first flat layer, and the second via hole penetrates through the first flat layer and the second flat layer.
According to an embodiment of the present disclosure, the common electrode is electrically connected to the metal layer through a first via hole, and the common electrode is electrically connected to a drain electrode of the thin film transistor in the thin film transistor device layer through a second via hole.
In summary, the beneficial effects of the embodiment of the present disclosure are:
when the array substrate of the embodiment of the disclosure is prepared, the flat layer is provided with the deep and shallow holes, so that the common electrode is directly conducted with the source/drain electrode of the thin film transistor, the switching through the middle third metal layer is omitted, a photomask etching process is omitted, influence factors of abnormal conditions of the display device are reduced, and the problem of panel abnormality is reduced.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some of the disclosed embodiments, and that other drawings can be obtained by those skilled in the art without inventive effort.
FIG. 1 is a schematic diagram of the structure of each layer of an array substrate according to an embodiment of the disclosure;
FIG. 2 is a schematic view of a process for fabricating an array substrate according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a display device according to an embodiment of the disclosure.
Detailed Description
The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. It is to be understood that the described embodiments are merely illustrative of some, but not all embodiments of the disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any inventive step, are intended to be within the scope of the present disclosure.
In an embodiment of the disclosure, as shown in fig. 1, fig. 1 is a schematic view of a structure of each layer of an array substrate according to an embodiment of the disclosure. The array substrate comprises a substrate 100, a polysilicon layer 107 arranged on the substrate 100, a gate insulating layer 101 arranged on the substrate 100 and the polysilicon layer 107, a gate 109 arranged on the gate insulating layer 101, an interlayer insulating layer 102 arranged on the gate 109 and the gate insulating layer 101, a second flat layer 103 arranged on the interlayer insulating layer 102, a metal layer 114 arranged on the second flat layer 103, a first flat layer 104 arranged on the metal layer 114 and the second flat layer 103, a common electrode 110 arranged on the first flat layer 104, and a passivation layer 105 arranged on the common electrode 110 and the first flat layer 104.
Preferably, in the embodiment of the present disclosure, in order to satisfy the touch function of the display panel, the metal layer 114 is a touch data signal line layer, and transmits a touch signal through the touch data signal line and controls the common electrode 110.
When the metal layer 114 and the common electrode 110 are prepared, the array substrate provided by the embodiment of the disclosure further includes a first via hole 116 and a second via hole 117, the first via hole 116 is disposed on the first flat layer 104 and at a position corresponding to the metal layer 114, the second via hole 117 penetrates through the first flat layer 104 and the second flat layer 103, and the second via hole 117 is disposed at a position corresponding to the source electrode 108.
Specifically, in the embodiment of the present disclosure, the common electrode 110 includes a first common electrode 112 and a second common electrode 113. The first common electrode 112 and the second common electrode 113 are arranged in an array and are insulated from each other.
The first common electrode 112 is connected and contacted with the metal layer 114 through a first via hole 116, and the second common electrode 113 is connected and contacted with the source electrode 108 of the thin film transistor through a second via hole 117 penetrating through the first and second planarization layers 104 and 103. Thereby realizing the signal conduction and control among different film layers.
The first via 116 is different from the second via 117 in that the depth of the first via 116 is smaller than the depth of the second via 117, and the second via 117 directly penetrates through the first and second planar layers 104 and 103. Thus, when the planarization layer is etched and the first via hole 116 and the second via hole 117 are formed, the first planarization layer 104 and the second planarization layer 103 may be subjected to a single exposure process, i.e., the same photomask process is used to perform exposure and development on the planarization layer, so that the second via hole 117 may be obtained by deepening the depth of the hole. Thereby effectively saving a photomask, simplifying the production process flow and saving the production cost.
Meanwhile, in the embodiment of the present disclosure, the second common electrode 113 is directly connected to the source electrode 108 through the second via hole 117. The problem that the common electrode can be connected with the source electrode 108 only through the transfer of the metal layer in the conventional array substrate is solved. In the display device, the more film layers are transferred to each other, the more the possibility of subsequent problems is increased. The embodiment of the disclosure effectively reduces and solves the problem of multiple switching abnormalities between the inner film layers of the array substrate.
In the embodiment of the present disclosure, the pixel electrode 111 is further included. The pixel electrode 111 is disposed on the passivation layer 105, wherein a third via hole 118 is disposed on the pixel electrode 111 at a position corresponding to the second common electrode 113. The pixel electrode 111 is in contact with the second common electrode 113 through the third via hole 118.
Meanwhile, through the second via hole 117, the second common electrode 113 and the third via hole 118, the pixel electrode 111 and the source electrode 108 of the thin film transistor are in conductive contact only by one-time switching.
Specifically, as shown in fig. 2, fig. 2 is a schematic flow chart of a manufacturing process of the array substrate according to the embodiment of the disclosure. When the array substrate is prepared, the preparation process flow comprises the following steps:
s100: providing a substrate, and preparing a thin film transistor device layer on the substrate
The thin film transistor device layer comprises a source electrode, a drain electrode and a polycrystalline silicon layer of the thin film transistor, and insulating layers and other film layers arranged among the film layers. In the preparation, the preparation is carried out according to the conventional preparation process of the thin film transistor device layer, and the detailed description is omitted.
S200: coating a first flat layer on the thin film transistor device layer, and preparing a metal layer on the first flat layer
After the step S100 is completed, the first planarization layer is continuously prepared thereon, and a metal layer is disposed on the first planarization layer, wherein the metal layer is a third metal layer, and during the preparation, the preparation processes such as exposure and etching are mainly performed.
S300: preparing a second flat layer on the first flat layer, and etching the first flat layer and the second flat layer to form via holes by using the same photomask
In step S300, deep and shallow via holes are formed in the first and second planar layers, and the deep and shallow via holes are etched and prepared through the same photomask. Specifically, the via hole comprises a first via hole and a second via hole, the first via hole penetrates through the first flat layer, and the second via hole penetrates through the first flat layer and the second flat layer. The first via hole and the second via hole are formed through the same photomask, and only the etching depths are different, so that a photomask etching process is omitted, one-time exposure process is saved, the preparation process of the array substrate is simplified, and the production efficiency is improved.
S400: preparing a common electrode layer, a passivation layer and a pixel electrode on the second flat layer, and forming the array substrate
After the preparation of the via hole is finished, other film layers of the array substrate are continuously prepared, and the other film layers mainly comprise a common electrode layer, a passivation layer and a pixel electrode, wherein the passivation layer is arranged on the common electrode and the second flat layer, the pixel electrode is arranged on the passivation layer, the pixel electrode is electrically connected with the common electrode through a third via hole, and the third via hole penetrates through the passivation layer.
The final fabrication forms the array substrate provided in the embodiments of the present disclosure.
Preferably, the source 108, the drain 1081, the gate 109, the polysilicon layer 107 and their corresponding layers form a thin film transistor device layer 116.
The polysilicon layer 107 is made of low temperature polysilicon, the gate 109, the source 108 and the drain 1081 are made of one or more of molybdenum, titanium, aluminum and copper, the passivation layer 105 is made of silicon nitride and silicon oxide, and the pixel electrode 111 is made of indium tin oxide.
In the embodiment of the present disclosure, the polysilicon layer 107 includes a channel region 12, N-type heavily doped regions 10 located at two ends of the polysilicon layer 107, and an N-type lightly doped region 11 located between the channel region 12 and the N-type heavily doped region 10.
In the thin film transistor device layer 116, a fourth via 119 is further included, and the source electrode 108 and the drain electrode 1081 are in contact with the heavily N-doped region 10 through the fourth via 119.
The substrate 100 is a buffer layer made of silicon oxide or silicon nitride, the interlayer insulating layer 102 is made of silicon nitride or silicon oxide or a composite material of the silicon nitride and the silicon oxide, and the substrate 100 may further include a reflective layer 106.
Correspondingly, the embodiment of the disclosure also provides a display device. As shown in fig. 3, fig. 3 is a schematic view of a display device according to an embodiment of the disclosure. The display device 200 includes an array substrate 201, the array substrate 201 is provided in the embodiment of the present disclosure, and the display device 200 has a simple manufacturing process and a low production cost.
The array substrate, the display device and the method for manufacturing the array substrate provided by the embodiments of the present disclosure are described in detail above, and the description of the embodiments is only used to help understand the technical solution and the core idea of the present disclosure; those of ordinary skill in the art will understand that: it is to be understood that modifications may be made to the arrangements described in the embodiments above, and such modifications or alterations may be made without departing from the spirit of the respective arrangements of the embodiments of the present disclosure.
Claims (10)
1. An array substrate, comprising:
a substrate;
a thin film transistor device layer disposed on the substrate;
a first planar layer disposed on the thin film transistor device layer;
a metal layer disposed on the first planarization layer;
a second planar layer disposed on the first planar layer and the metal layer; and
a common electrode disposed on the second planarization layer;
the common electrode is electrically connected with the metal layer through a first through hole, and the common electrode is also electrically connected with a drain electrode of a thin film transistor in the thin film transistor device layer through a second through hole.
2. The array substrate of claim 1, wherein the first via is disposed through the first planar layer and the second planar layer.
3. The array substrate of claim 2, wherein the first via and the second via are formed by a same photo-masking process.
4. The array substrate of claim 1, further comprising:
a passivation layer disposed on the common electrode and the second planarization layer;
the pixel electrode is arranged on the passivation layer, the pixel electrode is electrically connected with the common electrode through a third through hole, and the third through hole penetrates through the passivation layer.
5. The array substrate of claim 1, wherein the common electrode comprises a first common electrode and a second common electrode, the first common electrode is electrically connected with the metal layer through the first via, and the second common electrode is electrically connected with a drain electrode in the thin film transistor device layer through the second via.
6. The array substrate of claim 1, wherein the metal layer comprises touch data signal lines.
7. A display device comprising the array substrate according to any one of claims 1 to 6.
8. The preparation method of the array substrate is characterized by comprising the following steps:
s100: providing a substrate, and preparing a thin film transistor device layer on the substrate;
s200: coating a first flat layer on the thin film transistor device layer, and preparing a metal layer on the first flat layer;
s300: preparing a second flat layer on the first flat layer, and etching the first flat layer and the second flat layer by using the same photomask to form through holes;
s400: and preparing a common electrode layer, a passivation layer and a pixel electrode on the second flat layer, and forming the array substrate.
9. The method for preparing the array substrate according to claim 8, wherein the via holes comprise a first via hole and a second via hole, the first via hole penetrates through the first flat layer, and the second via hole penetrates through the first flat layer and the second flat layer.
10. The method for manufacturing the array substrate according to claim 9, wherein the common electrode is electrically connected to the metal layer through a first via hole, and the common electrode is electrically connected to a drain electrode of the thin film transistor in the thin film transistor device layer through a second via hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910862548.XA CN110649038A (en) | 2019-09-12 | 2019-09-12 | Array substrate, display device and preparation method of array substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910862548.XA CN110649038A (en) | 2019-09-12 | 2019-09-12 | Array substrate, display device and preparation method of array substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110649038A true CN110649038A (en) | 2020-01-03 |
Family
ID=69010489
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910862548.XA Pending CN110649038A (en) | 2019-09-12 | 2019-09-12 | Array substrate, display device and preparation method of array substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110649038A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111725241A (en) * | 2020-06-29 | 2020-09-29 | 昆山龙腾光电股份有限公司 | Array substrate, preparation method thereof and electronic price tag |
| CN113193012A (en) * | 2021-04-13 | 2021-07-30 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, preparation method thereof and display device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104656332A (en) * | 2015-01-28 | 2015-05-27 | 上海天马微电子有限公司 | Array substrate, preparation method thereof, and display device |
| CN204440372U (en) * | 2015-03-13 | 2015-07-01 | 京东方科技集团股份有限公司 | A kind of In-cell touch panel and display device |
| CN106908978A (en) * | 2017-04-28 | 2017-06-30 | 厦门天马微电子有限公司 | Touch-control display panel and touch control display apparatus |
| CN107479284A (en) * | 2017-08-30 | 2017-12-15 | 武汉华星光电技术有限公司 | A kind of array base palte and preparation method thereof, display panel |
| CN109597522A (en) * | 2018-10-26 | 2019-04-09 | 武汉华星光电技术有限公司 | Touch-control array substrate and touch-control display panel |
-
2019
- 2019-09-12 CN CN201910862548.XA patent/CN110649038A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104656332A (en) * | 2015-01-28 | 2015-05-27 | 上海天马微电子有限公司 | Array substrate, preparation method thereof, and display device |
| CN204440372U (en) * | 2015-03-13 | 2015-07-01 | 京东方科技集团股份有限公司 | A kind of In-cell touch panel and display device |
| CN106908978A (en) * | 2017-04-28 | 2017-06-30 | 厦门天马微电子有限公司 | Touch-control display panel and touch control display apparatus |
| CN107479284A (en) * | 2017-08-30 | 2017-12-15 | 武汉华星光电技术有限公司 | A kind of array base palte and preparation method thereof, display panel |
| CN109597522A (en) * | 2018-10-26 | 2019-04-09 | 武汉华星光电技术有限公司 | Touch-control array substrate and touch-control display panel |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111725241A (en) * | 2020-06-29 | 2020-09-29 | 昆山龙腾光电股份有限公司 | Array substrate, preparation method thereof and electronic price tag |
| CN111725241B (en) * | 2020-06-29 | 2023-07-25 | 昆山龙腾光电股份有限公司 | Array substrate, preparation method thereof and electronic price tag |
| CN113193012A (en) * | 2021-04-13 | 2021-07-30 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, preparation method thereof and display device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110649043B (en) | Array substrate, display panel, display device and preparation method of array substrate | |
| CN110379823B (en) | Array substrate and OLED display panel | |
| KR100295063B1 (en) | Power semiconductor device having trench gate structure and method for fabricating thereof | |
| WO2017166431A1 (en) | Tft array substrate and manufacturing method therefor, and display device | |
| US11139316B2 (en) | LTPS array substrate and method for manufacturing same | |
| WO2019205489A1 (en) | In-cell touch array substrate, display panel and manufacturing method therefor | |
| WO2016029564A1 (en) | Array substrate and manufacturing method thereof, display panel and display device | |
| JPH10135475A (en) | Semiconductor device and its manufacture | |
| WO2016106892A1 (en) | Array substrate, display panel, and manufacturing method for array substrate | |
| KR100268007B1 (en) | Fabrication method of lcd | |
| CN103943628A (en) | TFT array substrate, manufacturing method and display panel thereof | |
| CN110649038A (en) | Array substrate, display device and preparation method of array substrate | |
| CN108649036B (en) | Array substrate and manufacturing method thereof | |
| CN111710726B (en) | Thin film transistor substrate and preparation method thereof | |
| JP4481284B2 (en) | Method for manufacturing semiconductor device | |
| US10361261B2 (en) | Manufacturing method of TFT substrate, TFT substrate, and OLED display panel | |
| US20190333938A1 (en) | In-cell touch array substrate, display panel and manufacturing method thereof | |
| CN105679705A (en) | Manufacturing method of array substrate | |
| WO2019210602A1 (en) | Array substrate, manufacturing method therefor and display panel | |
| US11424337B2 (en) | Array substrate, manufacturing method thereof, and display panel | |
| US10510784B2 (en) | Array substrate and method of manufacturing the same, and display apparatus | |
| CN113728442A (en) | Array substrate and manufacturing method thereof | |
| CN114883346A (en) | Array substrate, manufacturing method thereof and display panel | |
| CN111029346A (en) | Display panel, manufacturing method thereof and electronic equipment | |
| JP4481361B2 (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200103 |
|
| RJ01 | Rejection of invention patent application after publication |