CN110633227B - Memory resetting circuit and mainboard applying same - Google Patents
Memory resetting circuit and mainboard applying same Download PDFInfo
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- CN110633227B CN110633227B CN201810643562.6A CN201810643562A CN110633227B CN 110633227 B CN110633227 B CN 110633227B CN 201810643562 A CN201810643562 A CN 201810643562A CN 110633227 B CN110633227 B CN 110633227B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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Abstract
A memory reset circuit is used for resetting a memory when a mainboard is started, and comprises a control chip and a logic control unit, wherein the control chip is used for outputting a first control signal with a first level and a second control signal with the first level within a preset time when the mainboard is started, and the first control signal and the second control signal are converted into a second level from the first level after the preset time; the control chip is used for receiving the first control signal and the second control signal and outputting a corresponding reset signal according to the received first control signal and the second control signal, and the reset signal is used for controlling the internal memory to be reset. Therefore, the memory can be reset when the mainboard is started, and the cost is saved. In addition, the circuit wiring on the main board is simplified.
Description
Technical Field
The invention relates to a memory reset circuit and a mainboard using the same.
Background
Generally, after a computer system is rebooted or booted, the system requires a memory reset. In the prior art, a control chip is usually used to cooperate with a plurality of transistors to complete the reset operation of the memory.
However, adding multiple transistors to the motherboard will increase the cost of the product and also make the motherboard more complicated.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a memory reset circuit and a motherboard using the same.
A memory reset circuit for resetting a memory when a motherboard is powered on, the memory reset circuit comprising:
the control chip is used for outputting a first control signal with a first level and a second control signal with the first level within a preset time when the mainboard is started, and the first control signal and the second control signal are converted from the first level to the second level after the preset time; and
the control chip is used for receiving the first control signal and the second control signal and outputting a corresponding reset signal according to the received first control signal and the second control signal;
when the logic control unit receives a first control signal with a first level and a second control signal with the first level, the logic control unit outputs a reset signal with the first level to the memory, and the reset signal with the first level controls the memory to be reset.
Further, when the logic control unit receives the first control signal with the second level and the second control signal with the second level, the logic control unit outputs a reset signal with the second level to the memory, and the reset signal with the second level does not control the memory to be reset.
Further, the control chip includes a first signal pin and a second signal pin, where the first signal pin is used to output the first control signal, and the second signal pin is used to output the second control signal.
Further, the control chip comprises a first signal pin and a second signal pin, the logic control unit comprises an and gate, first to third resistors and a capacitor, a first input end of the and gate is connected to the first signal pin of the control chip, the first input end of the and gate is grounded through the first resistor, a second input end of the and gate is connected to the second signal pin of the control chip, an output end of the and gate is connected to the memory through the second resistor, an output end of the and gate is grounded through the capacitor, a power supply end of the and gate is connected to a first power supply, a ground end of the and gate is grounded, and the first signal pin of the control chip is connected to the output end of the and gate through the third resistor.
Further, the memory reset circuit further includes a second power supply, and the second power supply is connected to a node between the first signal pin and the first input terminal through a fourth resistor.
Further, the control chip is a platform central controller, the first level is a low level, and the second level is a high level.
A motherboard comprising a memory and a memory reset circuit, the memory reset circuit to reset the memory when the motherboard is powered on, the memory reset circuit comprising:
the control chip is used for outputting a first control signal with a first level and a second control signal with the first level within a preset time when the mainboard is started, and the first control signal and the second control signal are converted from the first level to the second level after the preset time; and
the logic control unit is used for receiving the first control signal and the second control signal and outputting a corresponding reset signal according to the received first control signal and the second control signal;
when the logic control unit receives a first control signal with a first level and a second control signal with the first level, the logic control unit outputs a reset signal with the first level to the memory, and the reset signal with the first level controls the memory to be reset.
Further, when the logic control unit receives the first control signal and the second control signal with the second level, the logic control unit outputs a reset signal with the second level to the memory, and the reset signal with the second level does not control the memory to be reset.
Further, the control chip comprises a first signal pin and a second signal pin, the logic control unit comprises an and gate, first to third resistors and a capacitor, a first input end of the and gate is connected to the first signal pin of the control chip, the first input end of the and gate is grounded through the first resistor, a second input end of the and gate is connected to the second signal pin of the control chip, an output end of the and gate is connected to the memory through the second resistor, an output end of the and gate is grounded through the capacitor, a power supply end of the and gate is connected to a first power supply, a ground end of the and gate is grounded, and the first signal pin of the control chip is connected to the output end of the and gate through the third resistor.
Further, the memory reset circuit further includes a second power supply connected to a node between the first signal pin and the first input terminal through a fourth resistor.
In the memory reset circuit and the mainboard using the memory reset circuit, the logic control unit receives the first control signal and the second control signal output by the control chip, outputs the low-level reset signal within the preset time of starting the mainboard to control the memory to reset, and outputs the high-level reset signal after the preset time to no longer control the memory to reset. Therefore, the memory can be reset when the mainboard is started, and the cost is saved. In addition, the circuit wiring on the main board is simplified.
Drawings
Fig. 1 is a block diagram of a motherboard according to a preferred embodiment of the present invention.
FIG. 2 is a block diagram of a preferred embodiment of the memory reset circuit of FIG. 1.
Fig. 3 is a circuit diagram illustrating the connection between the memory reset circuit and the memory in fig. 1.
Description of the main elements
The following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention.
In order to make the objects, technical solutions and advantages of the present invention more clearly apparent, the memory reset circuit and the motherboard using the same of the present invention will be described in detail with reference to the accompanying drawings and embodiments.
Referring to fig. 1 and 2, in a preferred embodiment, a main board 300 includes a memory reset circuit 100 and a memory 200.
The memory reset circuit 100 is configured to reset the memory 200 when the motherboard 300 is powered on.
The memory reset circuit 100 may include a control chip 10 and a logic control unit 20.
The control chip 10 is configured to output a first control signal and a second control signal having a first level within a preset time after the motherboard 300 is powered on, where the first control signal and the second control signal are converted from the first level to a second level after the preset time.
The logic control unit 20 is electrically connected to the control chip 10, and configured to receive the first control signal and the second control signal, and output a corresponding reset signal according to the received first control signal and the received second control signal.
When the logic control unit 20 receives the first control signal and the second control signal with the first level, the logic control unit 20 outputs a reset signal with the first level to the memory 200, and the reset signal with the first level controls the memory 200 to reset.
When the logic control unit 20 receives the first control signal and the second control signal with the second level, the logic control unit 20 outputs a reset signal with the second level to the memory 200, and the reset signal with the second level does not control the memory 200 to be reset.
In this way, the logic control unit 20 receives the first control signal and the second control signal within a preset time to output a low level reset signal to control the memory to be reset. The logic control unit 20 receives the first control signal and the second control signal after a preset time, so as to output a high-level reset signal to no longer control the memory reset. Therefore, the memory can be reset when the mainboard is started, and the cost is saved. In addition, the circuit wiring on the main board is simplified.
It should be noted that the meaning of the memory 200 performing the reset operation is to clear all the stored contents in the memory.
In a preferred embodiment, the control chip is a Platform Controller Hub (PCH).
The first level is a low level state, and the second level is a high level state.
Referring to fig. 3, in a preferred embodiment, the control chip 10 may include a first signal pin RESET _ N for outputting the first control signal and a second signal pin SLP _ S4#, the second signal pin SLP _ S4# for outputting the second control signal.
The logic control unit 20 may further include an and gate U1, a first resistor R1, a second resistor R2, a third resistor R3, and a capacitor C1.
A first input end of the and gate U1 is connected to a first signal pin RESET _ N of the control chip 10 to receive a first control signal output from the control chip 10.
The first input end of the and gate U1 is further grounded through the first resistor R1, and the second input end of the and gate U1 is connected to the second signal pin SLP _ S4# of the control chip 10, so as to receive the second control signal output by the control chip 10.
The output end of the and gate U1 is connected to a reset signal pin DRAMRST # of the memory 200 through the second resistor R2, so as to output a reset signal to the memory 200.
The output end of the and gate U1 is further grounded through the capacitor C1, the power supply end of the and gate U1 is connected to a first power supply V1, the ground end of the and gate U1 is grounded, and the first signal pin RESET _ N of the control chip 10 is further connected to the output end of the and gate U1 through the third resistor R3.
A first control signal output by a first signal pin RESET _ N of the control chip 10 is a RESET control signal sent by the control chip 10, and a second control signal output by a second signal pin SLP _ S4# of the control chip 10 is a sleep signal sent by the control chip 10. In addition, the two control signals are both a control signal which changes from a low level to a high level.
Further, the memory RESET circuit 100 may further include a second power source V2, and the second power source V2 is connected to a node P between the first signal pin RESET _ N and the first input terminal of the and gate U1 through a fourth resistor R4.
Wherein the second power supply V2 is configured to output a supply voltage after the preset time.
The operation of the memory reset circuit 100 will be described as follows:
when the motherboard 300 is turned on, the first signal pin RESET _ N and the second signal pin SLP _ S4# of the control chip 10 output the first control signal and the second control signal, respectively. Within the preset time (e.g., 1ms), both the first control signal and the second control signal are in a low level state.
Thus, the and gate U1 outputs a low reset signal to the memory 200 after receiving the low first control signal and the low second control signal, so as to control the memory 200 to reset.
Then, after the preset time, the first control signal and the second control signal both change to high level. In this way, the and gate U1 outputs a high level reset signal to the memory 200 after receiving the high level first control signal and the high level second control signal, and the high level reset signal no longer controls the memory 200 to reset.
In addition, since the second power supply V2 will output a high voltage signal to the first input terminal of the and gate U1 after the preset time. In this way, even if the first signal pin RESET _ N of the control chip 10 cannot output the first control signal with high level, the second power supply V2 can still ensure that the first input terminal of the and gate U1 can continue to receive the control signal with high level. Therefore, the and gate U1 does not output a low level reset signal, so that the memory 200 is prevented from being reset when a motherboard is in an accident, and important data can be stored.
In the memory reset circuit 100 and the motherboard 300 using the memory reset circuit 100, the logic control unit 20 receives the first control signal and the second control signal output by the control chip 10, outputs the low-level reset signal within a preset time of booting the motherboard to control the memory to be reset, and outputs the high-level reset signal after the preset time to no longer control the memory to be reset. Therefore, the memory can be reset when the mainboard is started, and the cost is saved. In addition, the circuit wiring on the main board is simplified.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention and are not limited, although the present invention is described in detail with reference to the preferred embodiments.
It will be understood by those skilled in the art that various modifications and equivalent arrangements can be made without departing from the spirit and scope of the present invention. Moreover, based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.
Claims (10)
1. A memory reset circuit for resetting a memory when a motherboard is powered on, the memory reset circuit comprising:
the control chip is used for outputting a first control signal with a first level and a second control signal with the first level within a preset time when the mainboard is started, and the first control signal and the second control signal are converted from the first level to the second level after the preset time; and
the logic control unit is used for receiving the first control signal and the second control signal and outputting a corresponding reset signal according to the received first control signal and the second control signal;
when the logic control unit receives a first control signal with a first level and a second control signal with the first level, the logic control unit outputs a reset signal with the first level to the memory, and the reset signal with the first level controls the memory to be reset.
2. The memory reset circuit of claim 1, wherein when the logic control unit receives a first control signal having a second level and a second control signal having the second level, the logic control unit outputs a reset signal having the second level to the memory, the reset signal having the second level will not control the memory to be reset.
3. The memory reset circuit of claim 2, wherein the control chip comprises a first signal pin and a second signal pin, the first signal pin is configured to output the first control signal, and the second signal pin is configured to output the second control signal.
4. The memory reset circuit according to claim 3, wherein the control chip comprises a first signal pin and a second signal pin, the logic control unit comprises an and gate, first to third resistors, and a capacitor, a first input terminal of the and gate is connected to the first signal pin of the control chip, a first input terminal of the and gate is further grounded through the first resistor, a second input terminal of the and gate is connected to the second signal pin of the control chip, an output terminal of the and gate is connected to the memory through the second resistor, an output terminal of the and gate is further grounded through the capacitor, a power supply terminal of the and gate is connected to a first power supply, a ground terminal of the and gate is grounded, and the first signal pin of the control chip is further connected to the output terminal of the and gate through the third resistor.
5. The memory reset circuit of claim 4, further comprising a second power supply connected to a node between the first signal pin and the first input through a fourth resistor.
6. The memory reset circuit of claim 1 wherein the control chip is a platform hub controller, the first level is low, and the second level is high.
7. A motherboard comprising a memory and a memory reset circuit, the memory reset circuit to reset the memory when the motherboard is powered on, the memory reset circuit comprising:
the control chip is used for outputting a first control signal with a first level and a second control signal with the first level within a preset time when the mainboard is started, and the first control signal and the second control signal are converted from the first level to the second level after the preset time; and
the logic control unit is used for receiving the first control signal and the second control signal and outputting a corresponding reset signal according to the received first control signal and the second control signal;
when the logic control unit receives a first control signal with a first level and a second control signal with the first level, the logic control unit outputs a reset signal with the first level to the memory, and the reset signal with the first level controls the memory to be reset.
8. The motherboard of claim 7, wherein when the logic control unit receives the first control signal and the second control signal having the second level, the logic control unit outputs a reset signal having the second level to the memory, the reset signal having the second level not controlling the memory to be reset.
9. The main board according to claim 7, wherein the control chip includes a first signal pin and a second signal pin, the logic control unit includes an and gate, first to third resistors, and a capacitor, a first input terminal of the and gate is connected to the first signal pin of the control chip, a first input terminal of the and gate is further grounded through the first resistor, a second input terminal of the and gate is connected to the second signal pin of the control chip, an output terminal of the and gate is connected to the memory through the second resistor, an output terminal of the and gate is further grounded through the capacitor, a power supply terminal of the and gate is connected to a first power supply, a ground terminal of the and gate is grounded, and the first signal pin of the control chip is further connected to the output terminal of the and gate through the third resistor.
10. The motherboard of claim 9, wherein the memory reset circuit further comprises a second power supply, the second power supply connected to a node between the first signal pin and the first input through a fourth resistor.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810643562.6A CN110633227B (en) | 2018-06-21 | 2018-06-21 | Memory resetting circuit and mainboard applying same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810643562.6A CN110633227B (en) | 2018-06-21 | 2018-06-21 | Memory resetting circuit and mainboard applying same |
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| CN110633227A CN110633227A (en) | 2019-12-31 |
| CN110633227B true CN110633227B (en) | 2022-07-01 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101226942A (en) * | 2007-01-16 | 2008-07-23 | 旺宏电子股份有限公司 | Replacement method of non-volatilization internal memory |
| TW201701277A (en) * | 2015-06-26 | 2017-01-01 | 英業達股份有限公司 | Device for resetting hard disk drive |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI345788B (en) * | 2007-11-02 | 2011-07-21 | Inventec Corp | Memory reset apparatus |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101226942A (en) * | 2007-01-16 | 2008-07-23 | 旺宏电子股份有限公司 | Replacement method of non-volatilization internal memory |
| TW201701277A (en) * | 2015-06-26 | 2017-01-01 | 英業達股份有限公司 | Device for resetting hard disk drive |
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