CN110618746A - Soc power consumption and performance optimization device and method based on display processing logic - Google Patents
Soc power consumption and performance optimization device and method based on display processing logic Download PDFInfo
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- CN110618746A CN110618746A CN201910739380.3A CN201910739380A CN110618746A CN 110618746 A CN110618746 A CN 110618746A CN 201910739380 A CN201910739380 A CN 201910739380A CN 110618746 A CN110618746 A CN 110618746A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
- G06F1/3215—Monitoring of peripheral devices
- G06F1/3218—Monitoring of peripheral devices of display devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3243—Power saving in microcontroller unit
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/325—Power saving in peripheral device
- G06F1/3265—Power saving in display device
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
Abstract
The invention provides a device and a method for optimizing SOC power consumption and performance based on display processing logic, wherein the device comprises the following steps: the SOC screen display control and processing logic unit is used for taking out display data corresponding to the display layers 1-N in the memory of the SOC system, processing and synthesizing the display data, and outputting the display data to the external display screen line by line; the SOC data bus performance control unit is used for controlling the bus performance of the SOC screen display control and processing logic unit in the process of acquiring data from the SOC system memory, and the bus performance comprises SOC data bus priority; and the SOC CLOCK control unit controls the CLOCK frequency high-low switching and the CLOCK switch in real time, so that the CLOCK frequency corresponding to the SOC screen display control and processing logic unit is matched with the display data quantity of the display layers 1-N, and the purposes of improving power consumption and performance are achieved.
Description
Technical Field
The invention relates to a soc power consumption and performance optimization device and method of an operating system.
Background
At present, a mainstream operating system (for example, android) adopts a drawing mode of multiple layers when performing image display processing, and correspondingly adopts the same multiple layer processing mode on the screen display processing logic design of the SOC.
At present, the frequency and priority of a data bus and a processing unit are often set by a mainstream operating system according to the maximum data condition of each layer, which causes the bus and the processing unit to be always in high priority and high frequency, and finally has a great influence on the power consumption and performance of the system.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a soc power consumption and performance optimization device and method based on display processing logic, which dynamically adjust the frequency and priority of a display unit and a data bus according to the number of layers required by current display, the data amount required by each layer and the current processing condition of the layers, so as to achieve the purposes of improving power consumption and performance.
The device of the invention is realized as follows: an apparatus for display processing logic based SOC power consumption and performance optimization, comprising:
one end of the SOC screen display control and processing logic unit is connected with an SOC system memory through a data bus, and the other end of the SOC screen display control and processing logic unit is connected with an external display screen; the display data processing module is used for taking out the display data corresponding to the display layers 1-N in the SOC system memory, processing and synthesizing the display data and outputting the processed display data to the external display screen line by line;
the SOC data bus performance control unit is connected to the data bus and used for controlling the bus performance of the SOC screen display control and processing logic unit in the process of taking data from the SOC system memory, and the bus performance comprises SOC data bus priority; and
the SOC CLOCK control unit is connected with the SOC screen display control and processing logic unit and is used for controlling the high-low switching of the CLOCK frequency corresponding to the SOC screen display control and processing logic unit in real time so that the CLOCK frequency corresponding to the SOC screen display control and processing logic unit is matched with the display data quantity of the display layers 1-N;
when the SOC screen display control and processing logic unit finds that the number of display layers needing to be processed and synthesized is increased or the processing difficulty of the display layers is increased, the SOC CLOCK control unit is controlled to increase the frequency in advance, and the SOC data bus performance control unit is controlled to increase the bus performance in advance;
otherwise, when the SOC screen display control and processing logic unit finds that the number of display layers to be processed and synthesized is reduced or the processing difficulty of the display layers is reduced, the SOC CLOCK control unit is controlled to reduce the frequency and the SOC data bus performance control unit is controlled to reduce the bus performance.
Further, when the SOC screen display control and processing logic unit finds that the number of display layers to be processed and synthesized increases or the processing difficulty of the display layers increases, control processing logic, data cache logic and corresponding clocks corresponding to the newly added display layers are also opened in advance;
on the contrary, when the SOC screen display control and processing logic unit finds that the number of display layers to be processed and synthesized is reduced or the processing difficulty of the display layers is reduced, the control processing logic, the data cache logic and the corresponding clock corresponding to the reduced display layers are also closed.
Furthermore, the SOC screen display control and processing logic unit has N control processing logic circuits, and each control processing logic circuit controls and processes one display layer correspondingly;
when the SOC screen display control and processing logic unit needs to open or close the control processing logic, the data cache logic and the corresponding clock corresponding to the display layer, the control processing logic, the data cache logic and the corresponding clock of the control processing logic circuit corresponding to the display layer are opened or closed.
The method of the invention is realized as follows: a SOC power consumption and performance optimization method based on display processing logic comprises the following steps:
and S1, taking out the display data corresponding to the display layers 1-N in the SOC system memory, processing, synthesizing, and outputting to the external display screen line by line.
S2, when it is detected in advance that the number of display layers which need to be processed and synthesized by the data sent to the external display screen is increased or the processing difficulty of the display layers is increased, the frequency of taking out and processing the display data is increased in advance, and the bus performance is increased in advance;
on the contrary, when detecting that the number of layers required to be processed and synthesized by the data sent to the external display screen is reduced or the processing difficulty of the layers with the display is reduced, the frequency of taking out and processing the display data is reduced, and the performance of the bus is reduced.
Further, when it is detected in advance that the number of display layers to be processed and synthesized of data sent to an external display screen is increased or the processing difficulty of the display layers is increased, control processing logic, data cache logic and corresponding clocks corresponding to the newly added display layers are opened in advance;
otherwise, when it is detected that the number of layers to be processed and synthesized by the data sent to the external display screen has been reduced or the processing difficulty of the layers with the display has been reduced, the control processing logic, the data cache logic and the corresponding clock corresponding to the reduced display layers are also closed.
The invention has the following advantages: according to the invention, the frequency and priority of the display unit and the data bus are dynamically adjusted according to the number of layers required by current display, the data quantity required by each layer and the current processing condition of the layers, so that the purposes of improving power consumption and performance are achieved. The method of the present invention can be realized by hardware or software.
Drawings
The invention will be further described with reference to the following examples with reference to the accompanying drawings.
Fig. 1 is a block diagram of the schematic circuit structure of the optimization device of the present invention.
Fig. 2 is a display data hierarchy diagram of a system memory of each display layer according to an embodiment of the present invention.
Fig. 3 is a display data hierarchy diagram of a system memory of each display layer according to another embodiment of the present invention.
Detailed Description
Referring to fig. 1, the hardware circuit structure of the SOC power consumption and performance optimizing apparatus based on display processing logic of the present invention includes an SOC screen display control and processing logic unit, an SOC data bus performance control unit, and an soclock control unit;
one end of the SOC screen display control and processing logic unit is connected with an SOC system memory through a data bus, and the other end of the SOC screen display control and processing logic unit is connected with an external display screen; the display data processing module is used for taking out the display data corresponding to the display layers 1-N in the SOC system memory, processing and synthesizing the display data and outputting the processed display data to the external display screen line by line; specifically, a control processing logic circuit may be correspondingly arranged in the SOC screen display control and processing logic unit for each display layer, and there are N control processing logic circuits, and each control processing logic circuit controls and processes one display layer correspondingly.
The SOC data bus performance control unit is connected to the data bus and used for controlling the bus performance of the SOC screen display control and processing logic unit in the process of taking data from the SOC system memory, and the bus performance mainly comprises SOC data bus priority; and
the SOC CLOCK control unit is connected with the SOC screen display control and processing logic unit and is used for controlling the high-low switching of the CLOCK frequency corresponding to the SOC screen display control and processing logic unit in real time so that the CLOCK frequency corresponding to the SOC screen display control and processing logic unit is matched with the display data quantity of the display layers 1-N;
when the SOC screen display control and processing logic unit finds that the number of display layers needing to be processed and synthesized is increased or the processing difficulty of the display layers is increased, the SOC CLOCK control unit is controlled to increase the frequency in advance, and the SOC data bus performance control unit is controlled to increase the bus performance in advance; control processing logic, data caching logic and corresponding clocks corresponding to the newly added display layers are opened in advance;
otherwise, when the SOC screen display control and processing logic unit finds that the number of display layers to be processed and synthesized is reduced or the processing difficulty of the display layers is reduced, the SOC CLOCK control unit is controlled to reduce the frequency and the SOC data bus performance control unit is controlled to reduce the bus performance. And closing the control processing logic, the data caching logic and the corresponding clock corresponding to the reduced display layer.
When the SOC screen display control and processing logic unit needs to open or close the control processing logic, the data cache logic and the corresponding clock corresponding to the display layer, the control processing logic, the data cache logic and the corresponding clock of the control processing logic circuit corresponding to the display layer are opened or closed.
The SOC power consumption and performance optimization method based on the display processing logic comprises the following steps:
and S1, taking out the display data corresponding to the display layers 1-N in the SOC system memory, processing, synthesizing, and outputting to the external display screen line by line.
S2, when it is detected in advance that the number of display layers which need to be processed and synthesized by the data sent to the external display screen is increased or the processing difficulty of the display layers is increased, the frequency of taking out and processing the display data is increased in advance, and the bus performance is increased in advance; control processing logic, data caching logic and corresponding clocks corresponding to the newly added display layers are opened in advance;
on the contrary, when detecting that the number of layers required to be processed and synthesized by the data sent to the external display screen is reduced or the processing difficulty of the layers with the display is reduced, the frequency of taking out and processing the display data is reduced, and the performance of the bus is reduced. And closing the control processing logic, the data caching logic and the corresponding clock corresponding to the reduced display layer.
The display processing logic-based SOC power consumption and performance optimization method of the present invention can be implemented by a hardware circuit (e.g., a circuit device as shown in fig. 1) or by software.
The present invention will be further described with reference to the accompanying drawings and specific embodiments, and for convenience of description, the following display layers are simply referred to as layers, and the display data is simply data:
example one
Fig. 2 is a display data hierarchy diagram of a system memory of each display layer according to an embodiment of the present invention. Layer 1 corresponds to the display data of the entire screen, where the external display screen is a screen with a width of 2160 4096, and layer 2 represents an area of 2160 4096, i.e. starting from line 120 and ending with 180, and layers 3 and 2 represent similar. In the figure, the position of the upper end of the main shaft,
the area case represented by position 1 is: only the case of layer 1 needs to be displayed so this area only needs to process the data of layer 1. Since the SOC screen display control and processing logic unit may use data of Y (Y is greater than or equal to 1) rows up and down the row when processing data of one row in one layer, the memory data required for the position 1 is 2160 × Y pixel data.
The area situation in which position 2 is located is: the data of the layer 1 and the layer 2 need to be displayed, the display data is data of one line of each of the two layers, and the total data is 2 lines, so that the needed memory data is 2160 × Y × 2 pixel points.
The area situation in which position 3 is located is: the data of the layer 1, the layer 2 and the layer 3 need to be displayed, the display data is data of one line of each of the three layers, and the total data is 3 lines, so that the needed memory data is 2160 × Y × 3 pixels.
As can be seen, the memory data bandwidth required for location 3 is the highest, assuming that the highest required frequency is FREQ 1. The bus performance (e.g., data priority) of the data bus needs to be set highest.
For the area corresponding to the position 1, since data is reduced by 2/3 compared to the position 3, the corresponding frequency may be adjusted to FREQ3, the corresponding voltage may be reduced synchronously after the frequency is reduced, and processing logic and buffering logic related to the layer 2 and the layer 3 may be closed (closing a clock and other common power consumption control methods) to save power consumption. The bus performance of the data bus can be properly reduced (the bus performance can be reduced under the condition of reducing the frequency, and the bus performance can also be directly reduced), so that other modules (such as a cpu, a gpu and a video coding and decoding module) of the system can acquire data more easily, and the system performance is improved.
For the region corresponding to the position 2, since the data is reduced by 1/3 compared with the position 3, the corresponding frequency can be adjusted to FREQ2, and the corresponding voltage can be synchronously reduced after the frequency is reduced; and the processing logic and the cache logic related to the layer 3 can be closed (a common power consumption control method such as clock is closed) to save power consumption. The bus performance of the data bus can be further reduced (the bus performance can be reduced under the condition of reducing the frequency, and the bus performance can also be directly reduced), so that other modules (such as a cpu, a gpu and a video coding and decoding module) of the system can acquire data more easily, and the system performance is improved.
For the area corresponding to the position 1, there is only one layer-layer 1, although the data amount is less than the data amount of the multiple layers, when the SOC screen display control and processing logic unit detects that the acquired data cannot meet the processing requirement when performing layer 1 processing, it indicates that the whole system memory is busy, which needs to restore the frequency from FREQ3 to FREQ1 or FREQ 2.
The above data of Y lines for each layer is only for convenience of description, and in practice, data of upper and lower Y lines (Y is greater than or equal to 1, different algorithms, and values of Y are different, for example, in a scaling algorithm, Y is 4) may be needed at the same time when data of one layer is processed.
The process flow of the embodiment shown in FIG. 2, according to the present invention, is as follows:
when the SOC screen display control and processing logic unit processes display data, starting from the 1 st line of the layer 1, only one layer of the layer 1 needs to be processed during processing, and the SOC screen display control and processing logic unit can control the SOCCLOCK control unit to reduce the frequency and further reduce the corresponding voltage; the SOC screen display control and processing logic unit controls the SOC data bus performance control unit to reduce the bus performance (such as reducing the priority) configuration; meanwhile, the SOC screen display control and processing logic unit can also select to close the control logic, the data cache logic and the corresponding clock of the layers 2-3.
Assuming that the range of the overlapped rows of the layer 1 and the layer 2 is 120-180 th rows, when the SOC screen display control and processing logic unit processes 119 th rows, it checks in advance that the number of layers required for the first row (here, taking one row check in advance as an example, it can also check in advance for multiple rows, for example, it checks the 5 th row in advance when processing 115 th row) will increase and then data will increase, at this time, the SOC screen display control and processing logic unit needs to control the SOC CLOCK control unit to increase the frequency in advance, notify the voltage control module to increase the voltage, and control the SOC data bus performance control unit to appropriately increase the bus performance; the SOC screen display control and processing logic unit controls the SOC CLOCK control unit to open the control logic, the data cache logic, the corresponding CLOCK and the like corresponding to the layer 2.
When the SOC screen display processing logic processes to 181 rows, the two layers are changed into one layer (layer 2 is displayed from the 120 th row to the end of the 180 th row), so that the frequency and the corresponding voltage can be reduced; reduced bus performance (e.g., reduced priority) configuration; and meanwhile, clocks for closing the control logic and the data cache logic of the layers 2-3 can be selected.
Several treatments referred to above: reducing the frequency may further reduce the corresponding voltage, reduce the bus performance (e.g., reduce the priority) configuration, close the clocks of the control logic and data cache logic of layer 2. The configuration can be selected according to the specific requirements of the system. If the power consumption is expected to be reduced, the frequency can be reduced, and then the corresponding voltage, the control logic of the layer 2 and the clock of the data caching logic can be reduced. If it is desired to improve the performance of other modules of the system, such as (cpu, gpu, video codec modules), the bus performance of the module can be reduced (e.g. priority reduction) without reducing the frequency voltage.
Example two
Fig. 3 is a display data hierarchy diagram of a system memory of each display layer according to another embodiment.
As for the position 2 in fig. 3, although the data is also data of two layers, namely, the layer 1 and the layer 2, one row of the layer 1 is data of 2160 pixels, but the data enters the layer 2, only 60 pixels are provided in one row of the layer 2, the total pixel amount is Y × 2160+ Y × 60, and the data amount is not increased too much, so that the frequency and the bus performance of the data bus can be kept unchanged, the frequency does not need to be increased, and if the clock of the layer 2 is closed, the clock of the layer 2 only needs to be restored in advance. For the threshold of how much data amount is increased and the frequency needs to be increased, the system can be configured after actual test, such as: the frequency needs to be increased by 20% or 40% in the test data, so that the display effect and the performance are not affected.
Although specific embodiments of the invention have been described above, it will be understood by those skilled in the art that the specific embodiments described are illustrative only and are not limiting upon the scope of the invention, and that equivalent modifications and variations can be made by those skilled in the art without departing from the spirit of the invention, which is to be limited only by the appended claims.
Claims (5)
1. An SOC power consumption and performance optimization device based on display processing logic is characterized in that: the method comprises the following steps:
one end of the SOC screen display control and processing logic unit is connected with an SOC system memory through a data bus, and the other end of the SOC screen display control and processing logic unit is connected with an external display screen; the display data processing module is used for taking out the display data corresponding to the display layers 1-N in the SOC system memory, processing and synthesizing the display data and outputting the processed display data to the external display screen line by line;
the SOC data bus performance control unit is connected to the data bus and used for controlling the bus performance of the SOC screen display control and processing logic unit in the process of taking data from the SOC system memory, and the bus performance comprises SOC data bus priority; and
the SOC CLOCK control unit is connected with the SOC screen display control and processing logic unit and is used for controlling the high-low switching of the CLOCK frequency corresponding to the SOC screen display control and processing logic unit in real time so that the CLOCK frequency corresponding to the SOC screen display control and processing logic unit is matched with the display data quantity of the display layers 1-N;
when the SOC screen display control and processing logic unit finds that the number of display layers needing to be processed and synthesized is increased or the processing difficulty of the display layers is increased, the SOC CLOCK control unit is controlled to increase the frequency in advance, and the SOC data bus performance control unit is controlled to increase the bus performance in advance;
otherwise, when the SOC screen display control and processing logic unit finds that the number of display layers to be processed and synthesized is reduced or the processing difficulty of the display layers is reduced, the SOC CLOCK control unit is controlled to reduce the frequency and the SOC data bus performance control unit is controlled to reduce the bus performance.
2. The soc power consumption and performance optimization device based on display processing logic according to claim 1, wherein:
when the SOC screen display control and processing logic unit finds that the number of display layers needing to be processed and synthesized is increased or the processing difficulty of the display layers is increased, control processing logic, data caching logic and corresponding clocks corresponding to the newly added display layers are opened in advance;
on the contrary, when the SOC screen display control and processing logic unit finds that the number of display layers to be processed and synthesized is reduced or the processing difficulty of the display layers is reduced, the control processing logic, the data cache logic and the corresponding clock corresponding to the reduced display layers are also closed.
3. The soc power consumption and performance optimization device based on display processing logic according to claim 2, wherein: the SOC screen display control and processing logic unit is provided with N control processing logic circuits, and each control processing logic circuit correspondingly controls and processes one display layer;
when the SOC screen display control and processing logic unit needs to open or close the control processing logic, the data cache logic and the corresponding clock corresponding to the display layer, the control processing logic, the data cache logic and the corresponding clock of the control processing logic circuit corresponding to the display layer are opened or closed.
4. A SOC power consumption and performance optimization method based on display processing logic is characterized in that: the method comprises the following steps:
and S1, taking out the display data corresponding to the display layers 1-N in the SOC system memory, processing, synthesizing, and outputting to the external display screen line by line.
S2, when it is detected in advance that the number of display layers which need to be processed and synthesized by the data sent to the external display screen is increased or the processing difficulty of the display layers is increased, the frequency of taking out and processing the display data is increased in advance, and the bus performance is increased in advance;
on the contrary, when detecting that the number of layers required to be processed and synthesized by the data sent to the external display screen is reduced or the processing difficulty of the layers with the display is reduced, the frequency of taking out and processing the display data is reduced, and the performance of the bus is reduced.
5. The SOC power consumption and performance optimization method based on display processing logic of claim 4, wherein:
when the number of display layers which need to be processed and synthesized and are sent to the external display screen is detected to be increased or the processing difficulty of the display layers is detected to be increased in advance, control processing logic, data caching logic and corresponding clocks corresponding to the newly added display layers are opened in advance;
otherwise, when it is detected that the number of layers to be processed and synthesized by the data sent to the external display screen has been reduced or the processing difficulty of the layers with the display has been reduced, the control processing logic, the data cache logic and the corresponding clock corresponding to the reduced display layers are also closed.
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