CN110601803A - System chip supporting carrier aggregation technology - Google Patents
System chip supporting carrier aggregation technology Download PDFInfo
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- CN110601803A CN110601803A CN201910748927.6A CN201910748927A CN110601803A CN 110601803 A CN110601803 A CN 110601803A CN 201910748927 A CN201910748927 A CN 201910748927A CN 110601803 A CN110601803 A CN 110601803A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/0001—Arrangements for dividing the transmission path
Abstract
The invention discloses a system chip supporting a carrier aggregation technology, which comprises a data caching unit, a scheduling unit, a baseband processing unit and a distributing unit, wherein the data caching unit is used for caching data; the data caching unit receives a plurality of paths of carrier signals sent by the radio frequency transceiver, and sends a path of carrier signals to be processed to the baseband processing unit according to the instruction of the scheduling unit, the baseband processing unit demodulates and decodes the path of carrier signals and then outputs the path of carrier signals to the distributing unit, the plurality of paths of carrier signals multiplex the same baseband processing unit, and the distributing unit converges and synchronizes the output data of the baseband processing unit and then sends the output data to the subsequent processing unit; the invention can reduce the area of the chip and reduce the power consumption.
Description
Technical Field
The invention belongs to the technical field of chip architecture, and particularly relates to a system chip supporting a carrier aggregation technology.
Background
Carrier Aggregation (Carrier Aggregation) technology is to aggregate a plurality of carriers into a wider frequency spectrum, and can also aggregate discontinuous frequency spectrum fragments together, thereby being capable of well meeting the requirements of frequency spectrum compatibility of 5G, LTE and LTE-Advanced systems, not only accelerating the standardization process, but also utilizing the existing network, terminal equipment and frequency spectrum resources to the maximum extent.
The existing receiver chip for carrier aggregation is implemented by stacking hardware circuits with the same function, such as a carrier 1 baseband processing unit to a carrier N baseband processing unit in fig. 1, and the specific working principle is as follows: the signal transmitted by the radio frequency transceiver is sent to the scheduling unit, the data to be processed by different carriers are distributed to the baseband processing units of the corresponding carriers, then the different baseband processing units complete the corresponding functions of demodulation, decoding and the like, and then the data are delivered to the distribution unit, and the distribution unit completes the information aggregation, synchronization and the like output by the different baseband processing units and then delivers the information to the subsequent processing unit.
The advantage of above-mentioned scheme is that the realization is fairly simple, with original realization circuit simple replication can, increase simple signal distribution and assemble can, but its shortcoming is also very obvious:
1) the area overhead is large: each carrier corresponds to an independent processing unit, and the processing units cannot be shared, so that the redundancy is large, and the area of the aggregation of N carriers is increased by N times (relative to a non-carrier aggregation scheme);
2) the utilization rate is low: as described above, each carrier corresponds to an independent processing unit, and if the coincidence of different carriers is unbalanced, some processing units are heavily loaded, some processing units are lightly loaded, and even in a standby state, so that the utilization rate is not high enough;
3) high power consumption, especially static power consumption: compared with non-carrier aggregation, the area of the scheme is increased by N times (N carriers), so that the dynamic power consumption is also increased by at least N times; since the support of carrier aggregation is realized by stacking hardware circuits, the circuit scale is increased by N times, and complete shutdown is difficult to realize even if some carriers have no traffic, so that the leakage current is also increased proportionally. High power consumption results in short standby time and reduced product competitiveness.
Disclosure of Invention
In view of this, the present invention provides a system chip supporting carrier aggregation technology, which can reduce chip area and power consumption.
The technical scheme for realizing the invention is as follows:
a system chip supporting a carrier aggregation technology comprises a data caching unit, a scheduling unit, a baseband processing unit and a distribution unit;
the data caching unit receives multiple paths of carrier signals sent by the radio frequency transceiver, one path of carrier signals to be processed at present is sent to the baseband processing unit according to instructions of the scheduling unit, the baseband processing unit demodulates and decodes the path of carrier signals and then outputs the demodulated and decoded carrier signals to the distributing unit, the multiple paths of carrier signals multiplex the same baseband processing unit, and the distributing unit converges and synchronizes output data of the baseband processing unit and then sends the output data to the subsequent processing unit.
A system chip supporting a carrier aggregation technology comprises a data caching unit, a scheduling unit, a baseband processing unit and a distribution unit;
in the baseband processing unit, a data intensive operation module performs parallel processing on a plurality of paths of signals to be processed by a plurality of hardware circuits, and a control type operation module performs serial processing on a plurality of paths of signals to be processed by a single hardware circuit;
the data caching unit receives multiple paths of carrier signals sent by the radio frequency transceiver, sends one path of carrier signals to be processed to the corresponding operation module in the baseband processing unit for parallel or serial processing according to the instruction of the scheduling unit, and the distribution unit converges and synchronizes the output data of the baseband processing unit and then sends the output data to the subsequent processing unit.
Further, the data intensive arithmetic modules include FFT (fast fourier transform), matrix decomposition, matrix multiplication, matrix inversion, MIMO (multiple input multiple output control) and channel decoding.
Further, the operation module of the control type comprises data distribution, modulation and demodulation, resource de-mapping and descrambling.
Has the advantages that:
1. the invention is smaller than the traditional scheme in chip area no matter the serial processing or parallel and serial mixing scheme is carried out on the carrier signal by improving the processing efficiency.
2. The invention does not simply copy the hardware circuit by N parts, so the utilization rate of the hardware circuit is superior to the traditional scheme;
3. the invention is smaller than the traditional scheme in both dynamic power consumption and static power consumption.
Drawings
Fig. 1 is a schematic diagram of a conventional chip architecture for carrier aggregation.
Fig. 2 is a schematic diagram of a chip architecture supporting a carrier aggregation technique according to the present invention.
Fig. 3 is a schematic diagram of a chip architecture supporting carrier aggregation technology according to the present invention.
Detailed Description
The invention is described in detail below by way of example with reference to the accompanying drawings.
The invention provides a system chip supporting a carrier aggregation technology, as shown in fig. 2, comprising a data caching unit, a scheduling unit, a baseband processing unit and a distribution unit;
the data buffer unit receives a plurality of paths of carrier signals sent by the radio frequency transceiver, and sends a path of carrier signals to be processed to the baseband processing unit according to the instruction of the scheduling unit, the baseband processing unit demodulates and decodes the path of carrier signals, and the plurality of paths of carrier signals multiplex the same baseband processing unit, so that the data of the plurality of paths of carrier signals are processed in series and then are delivered to the distribution unit, and the distribution unit converges and synchronizes the output data of the baseband processing unit and then sends the output data to the subsequent processing unit. The distribution unit can have own data cache or can share with the data cache unit.
The efficiency of the baseband processing unit can be increased by increasing the operating frequency or increasing the voltage, and since the power consumption is proportional to the square of the voltage and proportional to the operating frequency, it is preferable to increase the operating frequency.
The scheme is realized by improving the performance of a hardware circuit, namely simply changing the space by time, and greatly saves the area compared with the traditional chip architecture for carrier aggregation.
On the basis of the above scheme, a mixing scheme is extended, as shown in fig. 3:
in the baseband processing unit, a data intensive operation module performs parallel processing on multiple signals to be processed by using multiple hardware circuits, that is, a carrier aggregation function is realized by copying the hardware circuits, and the data intensive operation module includes FFT (fast fourier transform), matrix decomposition, matrix multiplication, matrix inversion, MIMO (multiple input multiple output control), channel decoding, and the like. The control type operation module serially processes a plurality of paths of signals to be processed by a single hardware circuit, namely, the function of carrier aggregation is realized by increasing the working frequency; and control type operation modules such as data distribution, modulation and demodulation, resource de-mapping, descrambling and the like.
The data caching unit receives multiple paths of carrier signals sent by the radio frequency transceiver, sends one path of carrier signals to be processed to the corresponding operation module in the baseband processing unit for parallel or serial processing according to the instruction of the scheduling unit, and the distribution unit converges and synchronizes the output data of the baseband processing unit and then sends the output data to the subsequent processing unit.
The functional blocks XX/YY/ZZ in FIG. 3 are examples only and do not represent specific functionality. The functional module-XX/ZZ represents that the carrier aggregation function is realized by copying a hardware circuit, and the functional module-YY represents that the related bottom layer function of carrier aggregation is realized by improving the working frequency and the like.
The hybrid scheme is realized by combining the traditional scheme and the first scheme, the advantages of the traditional scheme and the first scheme are combined, the area and the power consumption are optimized in a finer dimension, part of modules are realized by simply copying a hardware circuit, and part of modules are realized by improving the performance (such as working frequency), so that the area of the whole chip is slightly increased compared with that of the first scheme, but the power consumption is lower than that of the first scheme.
Aiming at the defects of the existing chip implementation architecture of the carrier aggregation technology, the invention provides two more optimized implementation architecture schemes, one scheme has a high area advantage, the other scheme has a high power consumption advantage, and the decision of the specific architecture depends on the actual system specification and constraint conditions.
In summary, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (4)
1. A system chip supporting carrier aggregation technology is characterized by comprising a data buffer unit, a scheduling unit, a baseband processing unit and a distribution unit;
the data caching unit receives multiple paths of carrier signals sent by the radio frequency transceiver, one path of carrier signals to be processed at present is sent to the baseband processing unit according to instructions of the scheduling unit, the baseband processing unit demodulates and decodes the path of carrier signals and then outputs the demodulated and decoded carrier signals to the distributing unit, the multiple paths of carrier signals multiplex the same baseband processing unit, and the distributing unit converges and synchronizes output data of the baseband processing unit and then sends the output data to the subsequent processing unit.
2. A system chip supporting carrier aggregation technology is characterized by comprising a data buffer unit, a scheduling unit, a baseband processing unit and a distribution unit;
in the baseband processing unit, a data intensive operation module performs parallel processing on a plurality of paths of signals to be processed by a plurality of hardware circuits, and a control type operation module performs serial processing on a plurality of paths of signals to be processed by a single hardware circuit;
the data caching unit receives multiple paths of carrier signals sent by the radio frequency transceiver, sends one path of carrier signals to be processed to the corresponding operation module in the baseband processing unit for parallel or serial processing according to the instruction of the scheduling unit, and the distribution unit converges and synchronizes the output data of the baseband processing unit and then sends the output data to the subsequent processing unit.
3. The system-on-chip supporting carrier aggregation techniques as claimed in claim 2, wherein the data intensive operations modules include FFT, matrix decomposition, matrix multiplication, matrix inversion, MIMO and channel decoding.
4. The system-on-chip supporting the carrier aggregation technology as claimed in claim 2 or 3, wherein the operation module of the control type includes data distribution, modulation and demodulation, de-resource mapping and descrambling.
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| CN201910748927.6A CN110601803A (en) | 2019-08-14 | 2019-08-14 | System chip supporting carrier aggregation technology |
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| CN201910748927.6A CN110601803A (en) | 2019-08-14 | 2019-08-14 | System chip supporting carrier aggregation technology |
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| CN110601803A true CN110601803A (en) | 2019-12-20 |
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| CN106559110A (en) * | 2015-09-29 | 2017-04-05 | 中国电信股份有限公司 | Active antenna, carrier polymerizing method and system |
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| US4485383A (en) * | 1980-12-01 | 1984-11-27 | Texas Instruments Incorporated | Global position system (GPS) multiplexed receiver |
| EP3174347A1 (en) * | 2010-02-15 | 2017-05-31 | NTT DoCoMo, Inc. | Mobile terminal apparatus and method of transmitting an uplink control information signal |
| CN106302276A (en) * | 2015-05-29 | 2017-01-04 | 展讯通信（上海）有限公司 | Mobile terminal and receive signal processing system and method |
| CN106559110A (en) * | 2015-09-29 | 2017-04-05 | 中国电信股份有限公司 | Active antenna, carrier polymerizing method and system |
| CN108811187A (en) * | 2017-04-27 | 2018-11-13 | 展讯通信（上海）有限公司 | More more logical mobile terminals of card |
| US20190165975A1 (en) * | 2017-11-27 | 2019-05-30 | Samsung Electronics Co., Ltd. | Radio frequency integrated circuit supporting carrier aggregation and wireless communication device including the same |
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