CN110599941A - Display panel, driving method and display device - Google Patents
Display panel, driving method and display device Download PDFInfo
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- CN110599941A CN110599941A CN201910900362.9A CN201910900362A CN110599941A CN 110599941 A CN110599941 A CN 110599941A CN 201910900362 A CN201910900362 A CN 201910900362A CN 110599941 A CN110599941 A CN 110599941A
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 230000003139 buffering effect Effects 0.000 claims description 9
- 230000000694 effects Effects 0.000 abstract description 6
- 230000004044 response Effects 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 18
- 239000003990 capacitor Substances 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000002096 quantum dot Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
Abstract
The invention discloses a display panel, a driving method and a display device, wherein the display panel comprises a plurality of data lines, a plurality of multi-way gates, a reset circuit, a reset control line, a reset signal line, a plurality of data input lines and a plurality of gate control signal lines. Therefore, when the display panel is driven, the data lines can be reset in the reset stage, and the data signals remained in the last charging period cannot be stored on the data lines at the beginning of the data writing stage, so that the grid opening signals can be loaded on the grid lines corresponding to the pixel units in each row line by line and the gating opening signals can be loaded on the gating control signal lines in sequence in the data writing stage, so that the pixel units are normally charged, and the display effect can be improved. Also, the multi-pulse driving timing may be employed to improve the response time of the display panel.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel, a driving method and a display device.
Background
Generally, a plurality of data lines for transmitting data signals are provided on a display panel. Data signals are usually provided to each data line and then to the pixel cells to charge the pixel cells. However, when the pixel units electrically connected to the current row gate line need to be charged with the low-voltage data signal, if the data line keeps the high-voltage data signal, the high-voltage data signal is charged into the pixel units electrically connected to the current row gate line first, so that the pixel units electrically connected to the current row gate line cannot write the required low-voltage data signal, and abnormal display is caused.
Disclosure of Invention
The embodiment of the invention provides a display panel, a driving method and a display device, which can reset a data line in the display panel.
The display panel provided by the embodiment of the invention comprises a plurality of data lines, a plurality of multi-channel gates, a reset circuit, a reset control line, a reset signal line, a plurality of data input lines and a plurality of gate control signal lines; wherein: one of said multiplexers corresponds to one of said data input lines, and one of said data input lines is electrically connected to a plurality of said data lines through one of said multiplexers;
the multiplexer is used for respectively providing signals of the corresponding data input lines to each electrically connected data line under the control of signals of a plurality of gating control signal lines;
the reset circuit is used for respectively providing the signals of the reset signal lines to each data line under the control of the reset control line.
Optionally, the reset circuit comprises: a plurality of reset transistors; wherein: one of the reset transistors corresponds to one of the data lines;
the control end of the reset transistor is electrically connected with the reset control line, the first end of the reset transistor is electrically connected with the reset signal line, and the second end of the reset transistor is electrically connected with the corresponding data line.
Optionally, one of the multiplexers comprises: a plurality of gate transistors, one gate transistor corresponding to one data line, a first terminal of each gate transistor electrically connected to the corresponding data line, a second terminal of each gate transistor electrically connected to the corresponding data input line, and control terminals of different gate transistors in the same multiplexer electrically connected to different gate control signal lines.
Optionally, the plurality of gating transistors comprises: a first gating transistor, a second gating transistor, a third gating transistor; the plurality of gate control signal lines include: a first strobe control signal line, a second strobe control signal line, a third strobe control signal line; wherein:
the control end of the first gating transistor of each multiplexer is electrically connected with the first gating control signal line, the control end of the second gating transistor of each multiplexer is electrically connected with the second gating control signal line, and the control end of the third gating transistor of each multiplexer is electrically connected with the third gating control signal line.
Optionally, the method further comprises: a plurality of pixel units and a plurality of grid lines; wherein: the pixel unit comprises a plurality of sub-pixel units;
one row of the sub-pixel units is electrically connected with one grid line;
and one column of the sub-pixel units is electrically connected with one data line.
Optionally, the reset signal terminal is the same as a pixel reset signal terminal electrically connected to the sub-pixel unit.
Optionally, the reset circuit is located at one end of the data line, and the multiplexer is located at the other end of the data line.
Correspondingly, an embodiment of the present invention further provides a method for driving any one of the display panels, including: driving each row of pixel units row by row to be charged in at least one charging period;
wherein one charging cycle comprises:
in the reset stage, gate closing signals are loaded on the gate lines corresponding to the row pixel units, gate closing signals are loaded on the gate control signal lines, and reset opening signals are loaded on the reset control end so as to control the reset circuit to provide the signals of the reset signal lines to the corresponding data lines;
and in the data input stage, a grid opening signal is loaded on the grid line corresponding to the row of pixel units, a gating opening signal is sequentially loaded on the gating control signal line, and a resetting closing signal is loaded on the resetting control line.
Optionally, after the data input stage, the method further includes: a buffering phase comprising: a pre-buffering stage and a post-buffering stage, wherein:
and in the pre-buffering stage, grid closing signals are loaded on the grid lines corresponding to the row of pixel units, gating closing signals are loaded on the gating control signal lines, and reset opening signals are loaded on the reset control lines.
And in the post-buffering stage, grid closing signals are loaded on the grid lines corresponding to the row of pixel units, gating opening signals are sequentially loaded on the gating control signal lines, and resetting closing signals are loaded on the resetting control lines.
Correspondingly, the embodiment of the invention also provides a display device which comprises any one of the display panels provided by the embodiment of the invention.
The display panel comprises a plurality of data lines, a plurality of multi-way gates, a reset circuit, a reset control line, a reset signal line, a plurality of data input lines and a plurality of gate control signal lines. Therefore, when the display panel is driven, the data lines can be reset in the reset stage, and the data signals remained in the last charging period cannot be stored on the data lines at the beginning of the data writing stage, so that the grid opening signals can be loaded on the grid lines corresponding to the pixel units in each row line by line and the gating opening signals can be loaded on the gating control signal lines in sequence in the data writing stage, so that the pixel units are normally charged, and the display effect can be improved. Also, the multi-pulse driving timing may be employed to improve the response time of the display panel.
Drawings
FIG. 1 is a schematic diagram of a display panel in the related art;
FIG. 2 is a driving timing diagram of the display panel shown in FIG. 1;
FIG. 3 is a schematic diagram of a display panel according to another related art;
FIG. 4 is a driving timing diagram of the display panel shown in FIG. 3;
FIG. 5 is a timing diagram of another driving method corresponding to the display panel shown in FIG. 1;
FIG. 6 is a timing diagram of another driving method corresponding to the display panel shown in FIG. 1;
FIG. 7 is a timing diagram of another driving method corresponding to the display panel shown in FIG. 1;
fig. 8 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of a pixel circuit according to an embodiment of the invention;
FIG. 10 is a timing diagram of a driving method according to an embodiment of the present invention;
fig. 11 is a timing diagram of another driving method according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. And the embodiments and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
It should be noted that the sizes and shapes of the figures in the drawings are not to be considered true scale, but are merely intended to schematically illustrate the present invention. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.
Generally, a display panel includes: in practical application, the gate driving circuit loads a gate scanning signal to the gate lines row by row, and the source driving circuit loads a data signal to the data lines, so that data signals can be input to the sub-pixel units row by row to drive the sub-pixel units to be charged. The source driving circuit inputs data voltage signals to the data lines through data input lines corresponding to the data lines one to one. In order to reduce the number of input signal lines, a Multiplexer (MUX) is provided. For example, as shown in fig. 1, one MUX includes a first selection switch MUX1, a second selection switch MUX2, and a third selection switch MUX3, and a general driving timing diagram thereof includes a t1 phase and a t2 phase in one period t as shown in fig. 2. The first selection switch mux1, the second selection switch mux2 and the third selection switch mux3 are turned on in time division to load data signals to the data lines during a period t1, and the data signals on the data lines are input to the sub-pixel units during a period t 2. Wherein, Gate is the signal on the Gate line.
In practical applications, in order to reduce the number of data input lines due to a wiring space and the like, a manner in which one MUX electrically connects more than 3 data lines may be employed. However, as the number of data lines controlled by one MUX increases, the time length required for the t1 phase is longer, and the time length for the t2 phase is shorter, so that there is a risk of insufficient writing of data signals. For example, as shown in fig. 3, one MUX includes a first selection switch MUX1, a second selection switch MUX2, a third selection switch MUX3, a fourth selection switch MUX4, a fifth selection switch MUX5, and a sixth selection switch MUX 6. The general driving timing diagram is shown in fig. 4, and it can be seen that the duration of the t2 phase is significantly reduced compared to fig. 2.
In view of the above problem, as the driving timing chart shown in fig. 5, the t2 phase may be made to include the t1 phase. However, such timing may cause problems of display errors, such as: setting the last row of grid lines at the end side of signal scanning as the (n) th row, and when the pixel units on the (n-1) th row of grid lines are required to display black and the pixel units on the (n) th row of grid lines display white, the two rows are all black, and the reason is that: when the pixel units on the grid line of the (n-1) th row are required to display black, high voltage is required to be written into the data lines, so that after the MUX is closed, high voltage is stored on all the data lines by means of the parasitic capacitors, when the grid line of the (n) th row is opened, the high voltage stored in the parasitic capacitors of the data lines can be written into the sub-pixel units firstly, and when the MUX is opened, the real low voltage required to display white can not be written into the pixel circuits due to the fact that the grid electrode of the data writing transistor in the pixel circuit is set high, so that black pictures can be displayed continuously, and abnormal display is caused, wherein the grid electrode of the data writing transistor is a control end of the data writing transistor.
Meanwhile, when one row of sub-pixel units is driven to be charged, the response time of the display panel can be improved through multi-pulse driving timing, that is, when one row of sub-pixel units is driven to be charged, the timing of a plurality of periods t is set. For example, as shown in fig. 6, three periods t, that is, three pulse driving timings are provided. However, the driving timing in which the stage t1 is set before the stage t2 has a problem that the last rows at the end of signal scanning have gray scale differences from other rows because:
as shown in fig. 7, gate (n) is a signal on the gate line of the nth row, and the rest is the same. At stage t1, the MUX sequentially writes the data signals into the column data lines, and at stage t2, the pixel cells are charged by the data signals stored in the column data lines. When a multi-pulse driving time sequence is adopted, the pulse number is set to be 3, and when real data voltage is written into the sub-pixel units electrically connected with the grid lines of the (n) th row or the (n-1) th row, only one row of sub-pixel units and each data line are divided in parallel; when the sub-pixel units electrically connected with the grid lines of the (n-2) th row or the (n-3) th row write real data voltage, two rows of sub-pixel units and each data line perform voltage division in parallel. When the pixel units electrically connected with the grid lines of the (n-4) th row or the (n-5) th row write real data voltage, three rows of sub-pixel units and each data line perform voltage division in parallel. That is, the pixel units on the grid lines of the nth row and the (n-1) th row have gray scale differences with the pixel units on the grid lines of the (n-2) th row and the (n-3) th row, and the pixel units on the grid lines of the (n-2) th row and the (n-3) th row also have gray scale differences with the pixel units on the grid lines of the (n-4) th row and the (n-5) th row.
An embodiment of the present invention provides a display panel, as shown in fig. 8, including a plurality of Data lines Data, a plurality of multiplexers 200, a Reset circuit 100, a Reset control line Reset, a Reset signal line Vint, a plurality of Data input lines Sk (k is 1, 2 … …), and a plurality of gate control signal lines; wherein: one multiplexer 200 corresponds to one Data input line Sk, and one Data input line Sk is electrically connected with a plurality of Data lines Data through one multiplexer 200;
the multiplexer 200 is configured to provide signals of the corresponding Data input lines Sk to each of the electrically connected Data lines Data under the control of signals of the plurality of gate control signal lines;
the Reset circuit 100 is configured to supply a signal of the Reset signal line Vint to each of the Data lines Data, respectively, under the control of the Reset control line Reset.
Through the mutual matching of the signal lines and the circuits, the display panel provided by the embodiment of the invention can provide the signals of the reset signal line Vint to each Data line Data through the reset circuit 100, so as to reset each Data line Data, and cover the Data signals stored on the Data lines by using the signals of the reset signal line Vint. Therefore, when the display panel is driven, the data lines can be reset in the reset stage, and the data signals remained in the last charging period cannot be stored on the data lines at the beginning of the data writing stage, so that the grid opening signals can be loaded on the grid lines corresponding to the pixel units in each row line by line and the gating opening signals can be loaded on the gating control signal lines in sequence in the data writing stage, so that the pixel units are normally charged, and the display effect can be improved.
In a specific implementation manner, in the display panel provided in the embodiment of the present invention, as shown in fig. 8, the reset circuit 100 includes: a plurality of reset transistors MR; wherein: one reset transistor MR corresponds to one Data line Data;
the control end of the Reset transistor MR is electrically connected to the Reset control line Reset, the first end of the Reset transistor MR is electrically connected to the Reset signal line Vint, and the second end of the Reset transistor MR is electrically connected to the corresponding Data line Data.
For example, as shown in fig. 8, the control terminals of all the Reset transistors MR are electrically connected to one Reset control line Reset, and a plurality of Reset control lines Reset may be provided according to actual needs to control the Reset transistors MR to be turned on at different times or at the same time, which is not limited herein.
In specific implementation, the reset transistor MR is turned on under the control of a signal from the reset signal line Vint, and the signal from the reset signal line Vint is supplied to each Data line Data, so as to reset the Data lines Data.
In particular, in the display panel according to the embodiment of the present invention, as shown in fig. 8, a multiplexer 200 includes: a plurality of gate transistors (e.g., M01, M02, M03), one gate transistor corresponding to one Data line Data, each gate transistor having a first end electrically connected to the corresponding Data line Data, each gate transistor having a second end electrically connected to the corresponding Data input line Sk, and different gate transistors in the same multiplexer 200 having control ends electrically connected to different gate control signal lines. Illustratively, as shown in FIG. 8, a multiplexer 200 includes three gating transistors. Of course, in practical applications, the number of gating transistors included in one multiplexer 200 is not limited to three, for example, six. Therefore, the number of the gating transistors MUX included in one multiplexer 200 can be set according to actual needs, and is not limited herein.
In a specific implementation, the plurality of gating control signal lines control the plurality of gating transistors to be turned on in a time-sharing manner, so that signals of the Data input lines Sk can be provided to the plurality of Data lines Data in a time-sharing manner.
In a specific implementation, in the display panel provided in the embodiment of the present invention, the plurality of gate transistors may include three gate transistors: a first gate transistor M01, a second gate transistor M02, a third gate transistor M03; the plurality of gate control signal lines may include three gate control signal lines: a first gate control signal line CK _1, a second gate control signal line CK _2, and a third gate control signal line CK _ 3; wherein: the control terminal of the first gate transistor M01 of each multiplexer 200 is electrically connected to the first gate control signal line CK _1, the control terminal of the second gate transistor M02 of each multiplexer 200 is electrically connected to the second gate control signal line CK _2, and the control terminal of the third gate transistor M03 of each multiplexer 200 is electrically connected to the third gate control signal line CK _ 3. The design is helpful to reduce the number of signal lines and simplify the circuit structure, and certainly, more gate control signal lines can be arranged according to actual needs, which is not limited herein.
In specific implementation, as shown in fig. 8, the display panel provided in the embodiment of the present invention further includes: a plurality of pixel units 300, a plurality of gate lines G; wherein: the pixel unit 300 includes a plurality of sub-pixel units 310;
a row of sub-pixel units 310 is electrically connected with a gate line G;
a column of sub-pixel units 310 is electrically connected to one Data line Data.
In practical implementation, the plurality of pixel units 300 arranged in an array are located in the display area of the display panel. Each pixel cell 300 includes a plurality of sub-pixel cells 310. Illustratively, the pixel unit 300 may include a red sub-pixel unit R, a green sub-pixel unit G, and a blue sub-pixel unit B, so that color mixing may be performed by red, green, and blue to realize color display. Alternatively, the pixel unit 300 may also include a red sub-pixel unit R, a green sub-pixel unit G, a blue sub-pixel unit B, and a white sub-pixel unit, so that color display may be realized by mixing red, green, blue, and white. Of course, in practical applications, the light emitting color of the sub-pixel unit in the pixel unit 300 can be determined according to practical application environments, and is not limited herein.
In specific implementation, each sub-pixel unit 310 includes a light emitting device and a pixel circuit to drive the light emitting device L to emit light through the pixel circuit.
Illustratively, the pixel circuit in one sub-pixel unit 310 may be as shown in fig. 9, but is not limited thereto.
The pixel circuit in fig. 9 includes: the first switching transistor M1, the second switching transistor M2, the third switching transistor M3, the fourth switching transistor M4, the fifth switching transistor M5, the sixth switching transistor M6, the seventh switching transistor M7, the capacitor Cst, the fourth switching transistor M4 is a data writing transistor, wherein,
a first terminal of the capacitor Cst is electrically connected to the first power terminal VDD, and a second terminal of the capacitor Cst is electrically connected to the node N1; a first terminal of the fifth switching transistor M5 is electrically connected to the first terminal of the capacitor Cst, a control terminal of the fifth switching transistor M5 is electrically connected to the enable signal terminal EM, and a second terminal of the fifth switching transistor M5 is electrically connected to the first terminal of the fourth switching transistor M4; a first end of the fourth switching transistor M4 is electrically connected to a first end of the third switching transistor M3, a control end of the fourth switching transistor M4 is electrically connected to the gate line G, and a second end of the fourth switching transistor M4 is electrically connected to the Data line Data; a control terminal of the third switching transistor M3 is electrically connected to the node N1, and a second terminal of the third switching transistor M3 is electrically connected to a second terminal of the second switching transistor M2; a first terminal of the second switching transistor M2 is electrically connected to the node N1, a control terminal of the second switching transistor M2 is electrically connected to the gate line G, and a second terminal of the second switching transistor M2 is electrically connected to a first terminal of the sixth switching transistor M6; a first terminal of the first switching transistor M1 is electrically connected to the node N1, a control terminal of the first switching transistor M1 is electrically connected to the pixel reset control terminal Rst, and a second terminal of the first switching transistor M1 is electrically connected to the pixel reset signal line Vi; a control terminal of the sixth switching transistor M6 is electrically connected to the enable signal terminal EM, and a second terminal of the sixth switching transistor M6 is electrically connected to a second terminal of the seventh switching transistor M7; a first terminal of the seventh switching transistor M7 is electrically connected to the second terminal of the first switching transistor M1, a control terminal of the seventh switching transistor M7 is electrically connected to the pixel reset control terminal Rst, and a second terminal of the seventh switching transistor M7 is electrically connected to the first terminal of the light emitting device L; a second terminal of the light emitting device L is electrically connected to a second power source terminal VSS.
In a specific implementation, the control terminal of the switching transistor is a gate of the switching transistor.
In a specific implementation, in the display panel provided in the embodiment of the present invention, the working process of the pixel circuit may be substantially the same as that of the circuit in the related art, and is not described herein again.
In a specific implementation, the light emitting device L may be: at least one of Organic Light Emitting Diodes (OLED), Micro Light Emitting Diodes (Micro-LED), and Quantum Dot Light Emitting Diodes (QLED).
In specific implementation, in the display panel provided in the embodiment of the present invention, the reset signal line Vint and the pixel reset signal line Vi electrically connected to the sub-pixel unit 310 may be the same signal line. Thus, the number of signal lines in the display panel can be reduced, and the circuit structure can be simplified.
In a specific implementation manner, in the display panel provided in the embodiment of the present invention, if the reset circuit 100 is located at one end of the Data line Data, the multiplexer 200 may be located at the other end of the Data line Data.
In a specific implementation, as shown in fig. 8, the reset Transistor MR and the gate Transistor may be P-type transistors, and the design principle of the above-mentioned transistors is the same as that of the present invention, and the scope of the present invention also falls within the protection scope of the present invention, and the above-mentioned transistors may be Thin Film Transistors (TFTs) or Metal Oxide semiconductor field effect transistors (MOS), and are not limited herein. Depending on the type of each transistor and the signal of the control terminal of each transistor, the first terminal of each transistor may be a source and the second terminal may be a drain, or the first terminal of each transistor may be a drain and the second terminal may be a source, which is not particularly distinguished herein.
Based on the same inventive concept, an embodiment of the present invention further provides a driving method of the display panel provided by the embodiment of the present invention, including:
driving each row of pixel cells 300 row by row for charging in at least one charging period T;
wherein one charging period T includes:
a Reset stage T1, in which a gate turn-off signal is applied to the gate line G corresponding to the row pixel unit 300, a gate turn-off signal is applied to each gate control signal line, and a Reset turn-on signal is applied to the Reset control line Reset, so as to control the Reset control circuit to provide the signal of the Reset signal line Vint to the corresponding Data line Data;
in the data input stage T2, a gate-on signal is applied to the gate line G corresponding to the row pixel unit 300, a gate-on signal is sequentially applied to each gate control signal line, and a Reset-off signal is applied to the Reset control line Reset.
In practical implementation, in the driving method of a display panel provided in the embodiment of the present invention, after the data input stage T2, the method further includes: a buffering stage, the buffering stage comprising: a pre-buffering phase T3 and a post-buffering phase T4, wherein:
in the pre-buffer stage T3, a gate off signal is applied to the gate line G corresponding to the row pixel unit 300, a gate off signal is applied to each gate control signal line, and a Reset on signal is applied to the Reset control line Reset.
In the post-buffer stage T4, a gate-off signal is applied to the gate line G corresponding to the row pixel unit 300, a gate-on signal is sequentially applied to each gate control signal line, and a Reset-off signal is applied to the Reset control line Reset.
In practical implementation, in the pixel circuit provided in the embodiment of the invention, during the reset phase T1 or before the reset phase T1, the signal of the pixel reset control terminal Rst controls the first switching transistor M1 to be turned on, so as to provide the signal of the pixel reset signal terminal Vi to the node N1, and reset the node N1. When the third switching transistor is a P-type transistor, the signal of the pixel reset signal terminal Vi is at a low level.
Specifically, the gate-off signal applied to the gate line G corresponding to one row of the pixel unit 300 is: a signal for turning off the switching transistors electrically connected between the control terminal and the gate line G; the gate turn-on signal is: and a signal for turning on the switching transistors whose control terminals are electrically connected to the gate line G.
Specifically, the gate off signal applied to the gate control signal line is: a signal for turning off all the gating transistors whose control ends are electrically connected with the gating control line; the strobe on signal is: and a signal for turning on all the gating transistors whose control terminals are electrically connected with the gating control line.
Specifically, the Reset-off signal applied to the Reset control line Reset is: a signal for turning off all the Reset transistors MR whose control terminals are electrically connected to the Reset control line Reset; the reset start signal is: and a signal for turning on all the Reset transistors MR whose control terminals are electrically connected to the Reset control line Reset.
In the driving method provided by the embodiment of the invention, the Data lines Data are reset in the reset stage T1, and the Data signals remaining in the last charging period are not stored in each column of Data lines Data at the beginning of the Data writing stage T2, so that the gate start signals can be loaded to the gate lines G corresponding to each row of the pixel units 300 row by row and the gate start signals can be loaded to the gate control signal lines in sequence in the Data writing stage T2, so that the pixel units are normally charged, and the display effect can be improved.
In the driving method provided by the embodiment of the present invention, the gate line G corresponding to each row of the pixel units 300 is loaded with the gate start signal row by row in the Data writing stage T2, so that the increase of the number of Data lines Data controlled by each multiplexer 200 does not reduce the time length for turning on the gate line G, thereby improving the problem of insufficient Data signal writing caused by the large number of Data lines Data controlled by one multiplexer 200.
Meanwhile, the driving method provided by the embodiment of the invention may include a plurality of charging cycles T, that is, may include a plurality of data input stages T2. Therefore, for each sub-pixel unit 310, the Data signal is directly written in through the multiplexer 200 and the Data line Data in the Data input stage T2, that is, the embodiment of the present invention can adopt a multi-pulse driving timing sequence to improve the response time of the display panel, and can avoid the problem of gray scale difference of the pixel units electrically connected to the last several rows of gate lines at the end of scanning.
The present invention will be described in detail with reference to specific examples. It should be noted that the present embodiment is intended to better explain the present invention, but not to limit the present invention.
The operation of the display panel according to the embodiment of the present invention is described below with reference to a circuit timing diagram. In the following description, 1 denotes a high potential, and 0 denotes a low potential. It should be noted that 1 and 0 are logic potentials, which are only used to better explain the specific operation of the embodiment of the present invention, and not specific voltage values.
The first embodiment,
The following describes the operation of the display panel according to the embodiment of the present invention with reference to the circuit signal timing diagram shown in fig. 10, by taking the display panel shown in fig. 8 and the pixel circuit shown in fig. 9 as examples. The display panel shown in fig. 8 includes three gate control signal lines: a first gate control signal line CK _1, a second gate control signal line CK _2, and a third gate control signal line CK _ 3. A multiplexer includes three gating transistors: a first gating transistor M01, a second gating transistor M02, and a third gating transistor M03. FIG. 10 is a timing diagram of circuit signals for an example of a gate line G _ n-1 in a display panel.
Specifically, the reset phase T1, the data input phase T2, the pre-buffer phase T3, and the post-buffer phase T4 in one charging period T in the input timing chart shown in fig. 10 are selected.
At stage T1, Reset is 0, G _ n-1 is 1, CK _2 is 1, CK _3 is 1,
when Reset is 0, the Reset transistors MR in the display panel are all turned on, and a signal Vint of the Reset signal line is supplied to each data line electrically connected to the Reset transistors MR, thereby resetting the data lines. G _ n-1 is equal to 1, the second switching transistor M2 and the fourth switching transistor M4 in the pixel circuit of the sub-pixel unit electrically connected corresponding to the gate line are turned off. When CK _1 is equal to 1, the first gate transistors M01 in the display panel are all turned off, CK _2 is equal to 1, the second gate transistors M02 in the display panel are all turned off, and CK _3 is equal to 1, the third gate transistors M03 in the display panel are all turned off.
In stage T2, Reset is 1, G _ n-1 is 0, CK _2 is 1, CK _3 is 1,
when Reset is equal to 1, the Reset transistors MR in the display panel are all turned off, and CK _1 is equal to 0, the first gate transistors M01 in the display panel are all turned on, and the data signal on each data input line Sk is written into the data line corresponding to the first gate transistor M01. When CK _2 is equal to 1, the second gate transistors M02 in the display panel are all turned off, and CK _3 is equal to 1, the third gate transistors M03 in the display panel are all turned off. G _ N-1 is equal to 0, the second switching transistor M2 and the fourth switching transistor M4 in the pixel circuit of the sub-pixel unit electrically connected corresponding to the gate line are turned on, so that the data signal in the data line is written into the node N1.
Then, Reset is 1, G _ n-1 is 0, CK _1 is 1, CK _2 is 0, CK _3 is 1,
when Reset is equal to 1, the Reset transistors MR in the display panel are all turned off, CK _2 is equal to 0, the second gate transistors M02 in the display panel are all turned on, and the data signal of each data input line Sk in the second stage is written into the data line corresponding to each second gate transistor M02. When CK _1 is equal to 1, the first gate transistors M01 in the display panel are all turned off, and CK _3 is equal to 1, the third gate transistors M03 in the display panel are all turned off. G _ N-1 is equal to 0, the second switching transistor M2 and the fourth switching transistor M4 in the pixel circuit of the sub-pixel unit electrically connected to the corresponding gate line are turned on, the third switching transistor M3 is also turned on because the potential of the node N1 is equal to 0, and the data signal in the data line is written into the node N1 through the fourth switching transistor M4, the third switching transistor M3 and the second switching transistor M2.
Then, Reset is 1, G _ n-1 is 0, CK _1 is 1, CK _2 is 1, CK _3 is 0,
when Reset is equal to 1, the Reset transistors MR in the display panel are all turned off, CK _3 is equal to 0, the third gate transistors M03 in the display panel are all turned on, and the data signal of each data input line Sk in the second stage is written into the data line corresponding to each third gate transistor M03. When CK _1 is equal to 1, the first gate transistors M01 in the display panel are all turned off, and CK _2 is equal to 1, the second gate transistors M02 in the display panel are all turned off. G _ N-1 is equal to 0, the second switching transistor M2 and the fourth switching transistor M4 in the pixel circuit of the sub-pixel unit electrically connected to the corresponding gate line are turned on, the third switching transistor M3 is also turned on because the potential of the node N1 is equal to 0, and the data signal in the data line is written into the node N1 through the fourth switching transistor M4, the third switching transistor M3 and the second switching transistor M2.
Then, Reset is 1, G _ n-1 is 0, CK _1 is 1, CK _2 is 1, CK _3 is 1,
when Reset is 1, the Reset transistors MR in the display panel are all turned off. When CK _1 is equal to 1, the first gate transistors M01 in the display panel are all turned off, CK _2 is equal to 1, the second gate transistors M02 in the display panel are all turned off, and CK _3 is equal to 1, the third gate transistors M03 in the display panel are all turned off. G _ n-1 is equal to 0, the second switching transistor M2 and the fourth switching transistor M4 in the pixel circuit of the sub-pixel unit electrically connected to the corresponding gate line are turned on.
At stage T3, Reset is 0, G _ n-1 is 1, CK _2 is 1, CK _3 is 1,
the working process of the stage T3 is substantially the same as that of the stage T1, and is not described herein again.
At the stage T4, when G is equal to 1, the second switching transistor M2 and the fourth switching transistor M4 in the pixel circuit of the sub-pixel unit electrically connected to the gate line G _ n-1 are turned off, and other working processes are substantially the same as those at the stage T2, which is not described herein again.
As can be seen from the first embodiment, in the driving method provided in the embodiment of the present invention, the Data lines Data are reset in the reset phase T1, and the Data signals remaining in the previous charging period are not stored in each column of Data lines Data at the beginning of the Data writing phase T2, so that the gate start signal can be loaded to the gate line G corresponding to each row of the pixel units 300 row by row and the gate start signal can be loaded to each gate control signal line in sequence in the Data writing phase T2, so that the pixel units are normally charged, and the display effect can be further improved. In addition, in the Data writing phase T2, the gate-on signal is applied to the gate line G corresponding to each row of the pixel units 300 row by row, so that the increase of the number of Data lines Data controlled by each multiplexer 200 does not reduce the time length for turning on the gate line G, and the problem of insufficient Data signal writing caused by the large number of Data lines Data controlled by one multiplexer 200 can be improved.
Example II,
The following takes the display panel shown in fig. 8 as an example, and the working process of the display panel provided in the embodiment of the present invention is described with reference to the circuit signal timing diagram shown in fig. 11, and only the differences between the embodiment and the above embodiment will be described below, and the same parts will not be repeated herein.
The timing diagram of the circuit signals shown in fig. 11 includes three adjacent charging cycles: the working process of each charging cycle may be substantially the same as that of the charging cycle in the first embodiment, and details thereof are not repeated herein.
As can be seen from the second embodiment, the driving method provided in the embodiment of the present invention may include a plurality of charging cycles T, that is, may include a plurality of data input phases T2. Therefore, for each sub-pixel unit 310, the Data signal is directly written in through the multiplexer 200 and the Data line Data in the Data input stage T2, that is, the embodiment of the present invention can adopt a multi-pulse driving timing sequence to improve the response time of the display panel, and can avoid the problem of gray scale difference of the pixel units electrically connected to the last several rows of gate lines at the end of scanning.
Based on the same inventive concept, the embodiment of the invention also provides a display device, which comprises any one of the display panels provided by the embodiment of the invention. The display device can be implemented by referring to the above embodiments of the display panel, and repeated descriptions are omitted.
In a specific implementation, the display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should not be construed as limiting the invention.
The display panel comprises a plurality of data lines, a plurality of multi-way gates, a reset circuit, a reset control line, a reset signal line, a plurality of data input lines and a plurality of gate control signal lines. Therefore, when the display panel is driven, the data lines can be reset in the reset stage, and the data signals remained in the last charging period cannot be stored on the data lines at the beginning of the data writing stage, so that the grid opening signals can be loaded on the grid lines corresponding to the pixel units in each row line by line and the gating opening signals can be loaded on the gating control signal lines in sequence in the data writing stage, so that the pixel units are normally charged, and the display effect can be improved. Also, the multi-pulse driving timing may be employed to improve the response time of the display panel.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A display panel is characterized by comprising a plurality of data lines, a plurality of multi-way gates, a reset circuit, a reset control line, a reset signal line, a plurality of data input lines and a plurality of gate control signal lines; wherein: one of said multiplexers corresponds to one of said data input lines, and one of said data input lines is electrically connected to a plurality of said data lines through one of said multiplexers;
the multiplexer is used for respectively providing signals of the corresponding data input lines to each electrically connected data line under the control of signals of a plurality of gating control signal lines;
the reset circuit is used for respectively providing the signals of the reset signal lines to each data line under the control of the reset control line.
2. The display panel according to claim 1, wherein the reset circuit comprises: a plurality of reset transistors; wherein: one of the reset transistors corresponds to one of the data lines;
the control end of the reset transistor is electrically connected with the reset control line, the first end of the reset transistor is electrically connected with the reset signal line, and the second end of the reset transistor is electrically connected with the corresponding data line.
3. The display panel of claim 1, wherein one of the multiplexers comprises: a plurality of gate transistors, one gate transistor corresponding to one data line, a first terminal of each gate transistor electrically connected to the corresponding data line, a second terminal of each gate transistor electrically connected to the corresponding data input line, and control terminals of different gate transistors in the same multiplexer electrically connected to different gate control signal lines.
4. The display panel of claim 3, wherein the plurality of gating transistors comprises: a first gating transistor, a second gating transistor, a third gating transistor; the plurality of gate control signal lines include: a first strobe control signal line, a second strobe control signal line, a third strobe control signal line; wherein:
the control end of the first gating transistor of each multiplexer is electrically connected with the first gating control signal line, the control end of the second gating transistor of each multiplexer is electrically connected with the second gating control signal line, and the control end of the third gating transistor of each multiplexer is electrically connected with the third gating control signal line.
5. The display panel of claim 1, further comprising: a plurality of pixel units and a plurality of grid lines; wherein: the pixel unit comprises a plurality of sub-pixel units;
one row of the sub-pixel units is electrically connected with one grid line;
and one column of the sub-pixel units is electrically connected with one data line.
6. The display panel according to claim 5, wherein the reset signal terminal is the same terminal as a pixel reset signal terminal to which the sub-pixel unit is electrically connected.
7. The display panel according to any one of claims 1 to 6, wherein the reset circuit is located at one end of the data line, and the multiplexer is located at the other end of the data line.
8. A driving method of the display panel according to any one of claims 1 to 7, comprising:
driving each row of pixel units row by row to be charged in at least one charging period;
wherein one charging cycle comprises:
in the reset stage, gate closing signals are loaded on the gate lines corresponding to the row pixel units, gate closing signals are loaded on the gate control signal lines, and reset opening signals are loaded on the reset control end so as to control the reset circuit to provide the signals of the reset signal lines to the corresponding data lines;
and in the data input stage, a grid opening signal is loaded on the grid line corresponding to the row of pixel units, a gating opening signal is sequentially loaded on the gating control signal line, and a resetting closing signal is loaded on the resetting control line.
9. The driving method of claim 8, further comprising, after the data input stage: a buffering phase comprising: a pre-buffering stage and a post-buffering stage, wherein:
in the pre-buffering stage, gate closing signals are loaded on the grid lines corresponding to the row of pixel units, gating closing signals are loaded on the gating control signal lines, and reset opening signals are loaded on the reset control lines;
and in the post-buffering stage, grid closing signals are loaded on the grid lines corresponding to the row of pixel units, gating opening signals are sequentially loaded on the gating control signal lines, and resetting closing signals are loaded on the resetting control lines.
10. A display device characterized by comprising the display panel according to any one of claims 1 to 7.
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