CN110545079A - DPD lookup table generation method and device - Google Patents

Abstract

The application discloses a DPD lookup table generation method and device. The method comprises the following steps: respectively increasing the sampling rate of an input signal and an output signal of the power amplifier; determining a power amplifier characteristic coefficient according to the DPD model and by using the input signal and the output signal after the sampling rate is increased; obtaining an LUT according to the power amplifier characteristic coefficient and the input signal after the sampling rate is increased; and weighting each LUT according to the obtained weight of each LUT, and extracting each weighted LUT according to the sampling rate lifting multiple. By adopting the method and the device, the increase of resources and power consumption can be avoided while the signal sampling rate is improved.

Description

DPD lookup table generation method and device

Technical Field

The present invention relates to the field of wireless communication technologies, and in particular, to a method and an apparatus for generating a digital pre-distortion (DPD) lookup table.

Background

The rapid global growth of mobile broadband users and the continuous emergence of new services such as instant messaging, social networking, file sharing, mobile video, mobile cloud computing, etc., bring about the rapid growth of data volume and data rate demands of mobile users. In order to meet user requirements, the signal bandwidth needs to be increased. Currently, a 4G network Long Term Evolution (LTE) system supports 3-carrier configuration, a maximum signal bandwidth is 60MHz, a 5G system may require at least a single carrier signal bandwidth of 100MHz, and a multi-carrier signal bandwidth of 500MHz or more than 700 MHz.

in a communication system, in order to improve the linearization index of a power amplifier and to improve the operating efficiency thereof as much as possible, a DPD technique is commonly used in a transmitter. The DPD process is inverse characteristic fitting of the characteristics of the power amplifier, and the more consistent the DPD process is with the characteristics of the power amplifier, the better the actual predistortion effect is, and the better the Adjacent Channel Power Ratio (ACPR) index of the power amplifier is. To better correct the non-linear characteristics of the power amplifier, DPD techniques typically require a sampling rate of 3-5 times the signal bandwidth.

The development of future communication systems requires wider and wider signal bandwidth, which means that the sampling rate of signals in transmission, feedback, DPD and field-programmable gate array (FPGA) operation needs to be increased. High sampling rates will bring about a doubling of FPGA resources and power consumption.

Therefore, how to avoid the increase of resources and power consumption while improving the signal sampling rate for the broadband signal is a technical problem to be solved at present.

disclosure of Invention

The embodiment of the application provides a DPD lookup table generation method and device, which are used for avoiding the increase of resources and power consumption while improving the signal sampling rate.

In a first aspect, a method for generating a DPD lookup table is provided, including: the sampling rate of an input signal and an output signal of the power amplifier is improved; determining a power amplifier characteristic coefficient according to the DPD model and by using the input signal and the output signal after the sampling rate is increased; obtaining an LUT (look-up table) according to the power amplifier characteristic coefficient and the input signal after the sampling rate is improved; and weighting each LUT according to the weight of each LUT, and extracting the weighted LUTs.

According to the scheme, DPD aliasing can be avoided by increasing the sampling rate of the input signal and the output signal, and the number of LUTs can be reduced while the linearization index of the power amplifier is improved by weighting each LUT and extracting each weighted LUT.

In one possible implementation manner, weighting the LUTs according to their weights respectively includes: for each LUT, a weighted cumulative sum of the LUT and the other LUTs is determined from weights of the other LUTs relative to the LUT and the other LUTs.

According to the above aspect, for each LUT, the weighted sum of the LUT and the other LUTs is determined based on the weights of the other LUTs with respect to the LUT and the other LUTs, and therefore, the influence of each LUT can be integrated to improve the linearization index of the power amplifier.

In a possible implementation manner, if the DPD model is a DPD model based on a memory polynomial whose maximum memory depth is M, where M is an integer greater than or equal to 1, extracting weighted LUTs according to a sampling rate increase multiple includes: dividing the weighted LUTs into M groups according to the ascending or descending order of the memory depth of each LUT, wherein each group comprises the same number of LUTs; one LUT is extracted from each set of LUTs, respectively.

According to the scheme, the number of LUTs can be reduced by a grouping and extracting method, so that the resource overhead and the power consumption overhead of the FPGA are avoided being increased.

in one possible implementation, the power amplifier characteristic coefficient is determined according to the following formula:

A＝(YY)YX

wherein, A is a power amplifier characteristic coefficient matrix, Y is an output signal matrix after the sampling rate is increased, and X is an input signal matrix after the sampling rate is increased.

in a possible implementation manner, obtaining the LUT according to the power amplifier characteristic coefficient and the input signal after the sampling rate is increased includes:

The LUT is derived according to the following equation:

Wherein p is a nonlinear order, m is a memory depth of the memory polynomial, amp is a power amplifier characteristic coefficient with the memory depth of m and the nonlinear order of p, and L UT _ h is an LUT with the memory depth of m.

In one possible implementation, increasing the sampling rate of the input signal and the output signal of the power amplifier includes: and increasing the sampling rate of the input signal and the output signal of the power amplifier to K times, wherein K is an integer larger than 1.

In a second aspect, an apparatus for generating a DPD lookup table is provided, including: the sampling rate increasing module is used for increasing the sampling rate of the input signal and the output signal of the power amplifier; the power amplifier characteristic coefficient determining module is used for determining a power amplifier characteristic coefficient according to the DPD model and by utilizing the input signal and the output signal after the sampling rate is increased; the lookup table generation module is used for obtaining an LUT according to the power amplifier characteristic coefficient and the input signal after the sampling rate is improved; and the lookup table extraction module is used for weighting each LUT according to the weight of each LUT and extracting the weighted LUTs.

In a possible implementation manner, the lookup table extraction module is specifically configured to: for each LUT, a weighted cumulative sum of the LUT and the other LUTs is determined from weights of the other LUTs relative to the LUT and the other LUTs.

In a possible implementation manner, the lookup table extraction module is specifically configured to: if the DPD model is based on a memory polynomial with the maximum memory depth of M, wherein M is an integer greater than or equal to 1, dividing the weighted LUTs into M groups according to the ascending order or the descending order of the memory depth of each LUT, wherein each group contains the same number of LUTs, and extracting one LUT from each group of LUTs respectively.

In a possible implementation manner, the sampling rate boost module is specifically configured to: and increasing the sampling rate of the input signal and the output signal of the power amplifier to K times, wherein K is an integer larger than 1.

in a third aspect, a communication device is provided, the communication device comprising: the system comprises a processor, a memory and a transceiver, wherein the processor, the memory and the transceiver are connected through a bus; the processor is configured to read a program in the memory and execute the method of any of the first aspect.

in a fourth aspect, there is provided a computer-readable storage medium having stored thereon computer-executable instructions for causing the computer to perform the method of any of the first aspects above.

drawings

FIG. 1 is a diagram illustrating a DPD modeling process in the prior art;

FIG. 2 is a diagram illustrating a prior art implementation of a predistorter;

Fig. 3 is a schematic diagram of a LUT generation flow provided in an embodiment of the present application;

FIG. 4 is a diagram of a DPD architecture in an embodiment of the present application;

FIG. 5 is a schematic diagram of LUT speed reduction in an embodiment of the present application;

Fig. 6 is a schematic structural diagram of an LUT generation apparatus according to an embodiment of the present application;

Fig. 7 is a schematic structural diagram of a communication device according to an embodiment of the present application.

Detailed Description

In a communication system, a Memory Polynomial (MP) model is a common DPD model for correcting memory effect of a power amplifier, and its expression can be as follows:

Wherein, y (n) is a signal output by the power amplifier, x (n) is a signal input into the power amplifier, the maximum memory depth of the DPD model is M, the maximum nonlinear order is P, amp is a coefficient of a memory term with the memory depth of M and the nonlinear order of P, and LUT (look-up-table) is a DPD lookup table. The LUT may be trained from the input signal and the output signal of the power amplifier to reflect the characteristics of the power amplifier. The LUT comprises coefficients corresponding to different signal amplitudes, when DPD processing is carried out on the signal, the corresponding coefficients can be inquired according to the signal amplitude, and the inquired coefficients are used for carrying out DPD processing on the signal and then inputting the signal into the power amplifier for transmission so as to compensate the nonlinear distortion of the power amplifier.

If the bandwidth of the forward transmission signal x (n) is 100MHz, the spectral width of the output signal y (n) after passing through the power amplifier can reach 500MHz, and in order to correctly estimate the parameters of the DPD model by using equation (1), the spectral characteristics of the output signal need to be known, that is, the time sequence used in the modeling needs to have a sampling rate capable of reconstructing the original signal. Typically, the sampling rate is approximately 3-5 times the bandwidth of the signal.

fig. 1 shows the spectrum spreading of a signal after passing through a power amplifier according to equation (1). Aliasing may occur during the process of building and solving the LUT in the DPD model and implementing predistortion through the predistorter. As can be seen from the DPD modeling and DPD process of 100MHz signals, if the sampling rate is 245.76Msps, the 3 rd order nonlinear distortion component has a part of aliasing during DPD modeling, as identified in the D3 path signal in fig. 1, and the 5 th order nonlinear distortion component is completely in an aliasing state during the modeling, as identified in the D5 path signal in fig. 1.

Aliasing generated in the DPD modeling process can be reflected in the solved power amplifier characteristic coefficient, so that the precision of the LUT is influenced, and finally the ACPR index of the power amplifier is influenced, so that the broadband signal ACPR index can not meet the requirement. In order to meet the requirements of the system on the ACPR index, increasing the sampling rate of the system is the most direct and effective way.

A complete DPD procedure usually consists of three sub-procedures: the method comprises a data synchronization alignment subprocess, a DPD model establishment and LUT (look up table) subprocess, a predistorter established in an FPGA (field programmable gate array) based on an LUT and a DPD subprocess realized by the predistorter. The first two sub-processes may be implemented in a DSP (digital signal processing), and the last sub-process is typically implemented in hardware, such as an FPGA.

the implementation of a predistorter with a memory polynomial model with a memory depth of 2 is roughly as shown in fig. 2. Building a predistorter in an FPGA typically uses a Random Access Memory (RAM) and a multiplier. As can be seen from the predistortion process shown in fig. 2, the LUTs and multipliers occupy a large portion of the resources of the FPGA. For the memory polynomial model, what affects the RAM and the multipliers is the size of the memory depth, and the larger the memory depth is, the more multipliers are used in the predistorter, and the more resources are occupied by the RAM.

According to the analysis of the existing scheme, in order to eliminate aliasing in the DPD modeling process and improve the DPD modeling accuracy, the sampling rate needs to be increased. If the sampling rate is increased by 1 time, in order to ensure the accuracy of DPD modeling, the depth of the memory polynomial is also increased by 1 time, so that the number of the trained LUTs is also increased by 1 time, which results in the occupation of the space of the RAM in the FPGA and the increase of the number of multipliers by 1 time, and the power consumption of the FPGA is also increased by 1 time. Therefore, although the method for directly increasing the sampling rate of the digital predistortion system can improve the performance, the method also increases the resources and the power consumption.

In order to improve broadband signal linearization indexes and avoid increasing FPGA resources and power consumption for realizing DPD, the embodiment of the application provides an LUT generation method. In the method, in the process of establishing a power amplifier characteristic coefficient matrix and solving the LUT, the aliasing of the LUT is eliminated in a mode of increasing the sampling rate, and then the rate of the LUT without aliasing is reduced in a mode of secondary distribution and is transmitted to the FPGA to build a predistorter for DPD processing of service signals. The method can not only improve ACPR index on the basis of the existing algorithm, but also avoid the problem of the increase of the number of LUT tables caused by the increase of the sampling rate, thereby avoiding the increase of resource cost of DPD realized by FPGA.

The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

referring to fig. 3, a schematic flowchart of a LUT table generation method provided in the embodiment of the present application is shown, where the flowchart may include:

s301: the sampling rate of the input signal and the output signal of the power amplifier is increased.

in specific implementation, the sampling rate of the input signal and the output signal can be increased by K times, wherein K is an integer greater than 1. More specifically, K takes a value of 2, i.e., the sampling rate of the input signal and the output signal is increased by a factor of 2.

S302: and determining the power amplifier characteristic coefficient according to the DPD model and by using the input signal and the output signal after the sampling rate is increased in the S301.

The DPD model is used to reflect an influence of a characteristic of a power amplifier on an input signal, and the characteristic of the power amplifier may be specifically embodied as a power amplifier characteristic coefficient. According to the DPD model, the input signal and the output signal, the power amplifier characteristic coefficient can be obtained through calculation. That is, the power amplifier characteristic coefficient may be expressed as a function of the input signal and the output signal.

In specific implementation, a DPD inverse model can be obtained in advance according to the DPD model, and the power amplifier characteristic coefficient can be directly calculated by using the input signal and the output signal through the DPD inverse model.

Equation (2) shows an expression for estimating the power amplifier characteristic coefficient matrix a by using the least square algorithm:

A＝(YY)YX……………………………………………[2]

wherein, A is a power amplifier characteristic coefficient matrix, Y is a matrix of an output signal after the sampling rate is increased, and X is a matrix of an input signal after the sampling rate is increased. (. H) represents the conjugate transpose of the matrix and (. 1) represents the inverse of the matrix. According to the formula (2), the power amplifier characteristic coefficient matrix A can be obtained through calculation by utilizing the input signal matrix X and the output signal matrix Y.

taking a DPD model based on memory polynomial as an example, the power amplifier characteristic coefficient matrix obtained by calculation can be represented as:

Wherein M is the maximum memory depth of the memory polynomial, and P is the maximum nonlinear order. The elements in the matrix A are power amplifier characteristic coefficients. For example, α M-1,1 represents a power amplifier characteristic coefficient with a nonlinear order of 1 and a memory depth of M-1.

S303: and obtaining the LUT according to the power amplifier characteristic coefficient and the input signal after the sampling rate is improved.

In this step, taking a DPD model based on memory polynomial as an example, the LUT may be determined according to the following formula:

Wherein p is a nonlinear order, m is a memory depth of a memory polynomial, amp is a coefficient of a DPD lookup table with the polynomial memory depth of m and the nonlinear order of p, and L UT _ h represents an LUT with the polynomial memory depth of m.

S304: the LUTs obtained in S303 are weighted according to the LUT weights, and the weighted LUTs are extracted. By this step, the number of LUTs can be reduced.

wherein the number of LUTs is proportional to the number of sampling rate increases. Taking a DPD model based on a memory polynomial as an example (the maximum memory depth of the memory polynomial is M), if the sampling rate of the input signal and the output signal is increased to K times, the number of LUTs obtained in S303 is M × K. And M × K LUTs can be reduced to M LUTs by S304.

In this step, LUT secondary allocation (i.e., weighting operation) may be performed first, and then LUT extraction may be performed. The LUT with various memory depths can be considered by the LUT secondary allocation to improve the nonlinear index of the power amplifier, and the number of LUTs can be reduced by LUT extraction.

Optionally, in S304, one implementation manner of weighting the LUTs obtained in S303 according to the LUT weights is as follows: for each LUT, a weighted cumulative sum of the LUT and the other LUTs is determined based on the weights of the other LUTs relative to the LUT and the other LUTs, respectively. For one LUT, the weight of the other LUT relative to the LUT is related to the adjacent relation between the LUT and the LUT, and the weight is larger when the LUT is adjacent, and the weight is smaller when the LUT is not adjacent.

Taking the DPD model based on memory polynomials as an example, LUT0 represents an LUT with a memory depth of 0, LUT1 represents an LUT with a memory depth of 1, LUT2 represents an LUT with a memory depth of 2, and so on. Then for LUT1, the weights of the LUTs relative to LUT1 are, in descending order: LUT2 versus LUT1, LUT3 versus LUT1, LUT4 versus LUT1, and so on. For LUT4, the weights of LUT3 and LUT5 relative to LUT4 are the same, the weights of LUT2 and LUT6 relative to LUT4 are the same, and the weights of LUT1 and LUT7 relative to LUT4 are the same. The weights of the LUTs relative to LUT4, in descending order: weights of LUTs 5 and 3 relative to LUT4, weights of LUTs 6 and 2 relative to LUT4, weights of LUTs 7 and 1 relative to LUT4, and so on.

Alternatively, the formula for calculating the weighted cumulative sum may be expressed as:

Wherein, LUT _ h (i) represents LUT with memory depth i, μ i represents weight of LUT _ h (i). Alternatively, 0 < μ i ≦ 1. Taking as an example the weighting process for calculating the LUT with a memory depth of 1 (that is, LUT _ h in equation 4 represents an LUT with a memory depth of 1), the weight of the LUT with a memory depth of 1 is μ 0(μ 0 is 1), the weight of the LUT with a memory depth of 2 is μ 1(μ 1 < μ 0) with respect to the LUT with a memory depth of 1, the weight of the LUT with a memory depth of 3 is μ 2(μ 2 < μ 1) with respect to the LUT with a memory depth of 1, and so on, the weights corresponding to the LUTs are multiplied by the LUTs and added up to obtain the LUT with a memory depth of 1 after weighting. According to this principle, weighting may be performed for each LUT.

optionally, in S304, one implementation manner of decimating the weighted LUT according to the sampling rate boost multiple is as follows: the weighted LUTs are divided into M groups according to the ascending or descending order of the memory depth of each LUT, each group contains the same number of LUTs, and one LUT is extracted from each group of LUTs.

Taking the DPD model using the memory polynomial as an example, if the sampling rate of the input signal and the output signal is increased to K times, in S303, the number of LUTs obtained according to the power amplifier characteristic coefficient and the input signal after the sampling rate is increased is M × K, and in S304, the number of LUTs obtained by extracting the weighted LUTs is M. I.e. one LUT is extracted from every K LUTs, resulting in M LUTs.

It can be seen from the above description that by increasing the sampling rate of the input signal and the output signal, DPD aliasing can be avoided, and by weighting the LUTs and extracting the weighted LUTs, the number of LUTs can be reduced, and at the same time, the linearization index of the power amplifier can be improved.

In order to more clearly understand the embodiment of the present application, the LUT generation method provided in the embodiment of the present application is described in detail below with reference to fig. 4, taking DPD modeling in a 5G system as an example.

In this example, a DPD model based on memory polynomials is used for modeling. The memory polynomial can be represented by the above formula 1, and the memory depth M is 5.

According to the flow shown in fig. 3, the sampling rate is raised in S301. Specifically, the sampling rates of an input signal x (n) and an output signal y (n) of the Power Amplifier (PA) are respectively increased by 2 times, the input signal after the sampling rate is increased is represented as x (2n), and the output signal after the sampling rate is increased is represented as y (2 n).

Based on the memory polynomial, the set DPD inverse model can be expressed as:

the output signal matrix Y can be expressed as:

In S302 to S303, a coefficient establishment solving LUT is performed. Specifically, according to the formula 2, the power amplifier characteristic coefficient matrix a is obtained by using the matrix of the input signal with the increased sampling rate and the matrix of the output signal with the increased sampling rate. Based on the formula 3, 10 LUTs are calculated by using the power amplifier characteristic coefficient matrix a and the input signal with the improved sampling rate, and the memory depth of each LUT is 0 to 9. The sampling rate for these 10 LUTs is increased by a factor of 1, and thus there are no aliasing components.

In S304, LUT down-rate secondary allocation is performed. Specifically, in order not to increase the resource overhead and the power consumption overhead of the FPGA, the LUT is subjected to a speed reduction process before being passed to the FPGA. According to the description of S304, the principle of half-band filtering can be adopted, and filtering is performed before decimation, so that both the validity of information and the speed reduction of the LUT can be realized. Taking an MP model with a memory depth of 5 (i.e. a memory depth of 0-4) as an example, after the sampling rate used in the power amplifier characteristic coefficient solving is increased by 1 time, the corresponding memory depth is also increased to 10 (0-9) in order to maintain the accuracy of DPD modeling accuracy. After LUT secondary allocation (i.e. weighting) and decimation, 5 LUTs are obtained. These 5 LUTs are configured in the FPGA to build predistorters for the traffic signal and for implementing DPD.

The process of performing LUT slowdown secondary allocation may be as shown in fig. 5. The assignment of LUT4_ h to other LUTs is only shown in fig. 5, and in a specific implementation, a similar secondary assignment process is performed for each LUT. After the secondary allocation is performed for each LUT, one LUT may be selected from every 2 LUTs. Of the 10 LUTs in fig. 5, the LUT shown by the solid line frame is a selected LUT, and the LUT shown by the broken line frame is a discarded LUT. Finally 5 LUTs are obtained.

Based on the same technical concept, the embodiment of the present application further provides a DPD lookup table generating apparatus, which can implement the function of LUT generation in the foregoing embodiments.

referring to fig. 6, a schematic structural diagram of a DPD lookup table generating apparatus according to an embodiment of the present application is shown, where the DPD lookup table generating apparatus may include: the device comprises a sampling rate improving module 601, a power amplifier characteristic coefficient determining module 602, a lookup table generating module 603 and a lookup table extracting module 604.

The sampling rate increasing module 601 is configured to increase sampling rates of an input signal and an output signal of the power amplifier; the power amplifier characteristic coefficient determining module 602 is configured to determine a power amplifier characteristic coefficient according to the DPD model and by using the input signal and the output signal after the sampling rate is increased; the lookup table generating module 603 is configured to obtain an LUT according to the power amplifier characteristic coefficient and the input signal after the sampling rate is increased; the look-up table extracting module 604 is configured to weight each LUT according to the weight of the LUT, and extract each weighted LUT.

optionally, the look-up table extracting module 603 is specifically configured to: for each LUT, a weighted cumulative sum of the LUT and the other LUTs is determined from weights of the other LUTs relative to the LUT and the other LUTs.

Optionally, the look-up table extracting module 603 is specifically configured to: if the DPD model is based on a memory polynomial with the maximum memory depth of M, wherein M is an integer greater than or equal to 1, dividing the weighted LUTs into M groups according to the ascending order or the descending order of the memory depth of each LUT, wherein each group contains the same number of LUTs, and extracting one LUT from each group of LUTs respectively.

optionally, the sampling rate boost module 601 is specifically configured to: and increasing the sampling rate of the input signal and the output signal of the power amplifier to K times, wherein K is an integer larger than 1.

based on the same technical concept, the embodiment of the present application further provides a communication device, which can implement the LUT generation function in the foregoing embodiments.

Referring to fig. 7, a schematic structural diagram of a communication device provided in the embodiment of the present application is shown, where the communication device may include: a processor 701, a memory 702, a transceiver 703, and a bus interface.

the processor 701 is responsible for managing the bus architecture and general processing, and the memory 702 may store data used by the processor 701 in performing operations. The transceiver 703 is used for receiving and transmitting data under the control of the processor 701.

The bus architecture may include any number of interconnected buses and bridges, with one or more processors, represented by processor 701, and various circuits, represented by memory 702, being linked together. The bus architecture may also link together various other circuits such as peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further herein. The bus interface provides an interface. The processor 701 is responsible for managing the bus architecture and general processing, and the memory 702 may store data used by the processor 701 in performing operations.

The process disclosed in the embodiments of the present invention may be applied to the processor 701, or implemented by the processor 701. In implementation, the steps of the signal processing flow may be implemented by integrated logic circuits of hardware or instructions in the form of software in the processor 701. The processor 701 may be a general purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or the like that may implement or perform the methods, steps, and logic blocks disclosed in embodiments of the present invention. A general purpose processor may be a microprocessor or any conventional processor or the like. The steps of a method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware processor, or may be implemented by a combination of hardware and software modules in the processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in the memory 702, and the processor 701 reads the information in the memory 702 and completes the steps of the signal processing flow in combination with the hardware thereof.

Specifically, the processor 701 is configured to read a program in the memory 702 and execute: the sampling rate of an input signal and an output signal of the power amplifier is improved; determining a power amplifier characteristic coefficient according to the DPD model and by using the input signal and the output signal after the sampling rate is increased; obtaining an LUT according to the power amplifier characteristic coefficient and the input signal after the sampling rate is increased; and weighting each LUT according to the weight of each LUT, and extracting the weighted LUTs.

Based on the same technical concept, the embodiment of the application also provides a computer storage medium. The computer-readable storage medium stores computer-executable instructions for causing the computer to perform the processes performed by the foregoing embodiments.

the present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

while the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims (11)

1. A method for generating a Digital Predistortion (DPD) lookup table is characterized by comprising the following steps:

the sampling rate of an input signal and an output signal of the power amplifier is improved;

determining a power amplifier characteristic coefficient according to the DPD model and by using the input signal and the output signal after the sampling rate is increased;

Obtaining a look-up table (LUT) according to the power amplifier characteristic coefficient and the input signal with the improved sampling rate;

And weighting each LUT according to the weight of each LUT, and extracting the weighted LUTs.

2. The method of claim 1 wherein weighting the LUTs separately according to their weights comprises:

for each LUT, a weighted cumulative sum of the LUT and the other LUTs is determined from weights of the other LUTs relative to the LUT and the other LUTs.

3. the method of claim 1, wherein if the DPD model is based on a memory polynomial with a maximum memory depth of M, where M is an integer greater than or equal to 1, then extracting the weighted LUTs according to a sampling rate lifting factor comprises:

Dividing the weighted LUTs into M groups according to the ascending or descending order of the memory depth of each LUT, wherein each group comprises the same number of LUTs;

One LUT is extracted from each set of LUTs, respectively.

4. The method of claim 1, wherein the power amplifier characteristic coefficients are determined according to the following formula:

A＝(YY)YX

Wherein, A is a power amplifier characteristic coefficient matrix, Y is an output signal matrix after the sampling rate is increased, and X is an input signal matrix after the sampling rate is increased.

5. the method of claim 1, wherein obtaining the LUT according to the power amplifier characteristic coefficient and the input signal after the sampling rate boosting comprises:

the LUT is derived according to the following equation:

Wherein p is a nonlinear order, m is a memory depth of the memory polynomial, amp is a power amplifier characteristic coefficient with the memory depth of m and the nonlinear order of p, and L UT _ h is an LUT with the memory depth of m.

6. The method of any of claims 1 to 5, wherein boosting the sampling rate of the input signal and the output signal of the power amplifier comprises:

And increasing the sampling rate of the input signal and the output signal of the power amplifier to K times, wherein K is an integer larger than 1.

7. an apparatus for generating a Digital Predistortion (DPD) lookup table, comprising:

The sampling rate increasing module is used for increasing the sampling rate of the input signal and the output signal of the power amplifier;

the power amplifier characteristic coefficient determining module is used for determining a power amplifier characteristic coefficient according to the DPD model and by utilizing the input signal and the output signal after the sampling rate is increased;

The lookup table generation module is used for obtaining a lookup table LUT according to the power amplifier characteristic coefficient and the input signal after the sampling rate is improved;

And the lookup table extraction module is used for weighting each LUT according to the weight of each LUT and extracting the weighted LUTs.

8. The apparatus of claim 7, wherein the look-up table extraction module is specifically configured to:

For each LUT, a weighted cumulative sum of the LUT and the other LUTs is determined from weights of the other LUTs relative to the LUT and the other LUTs.

9. The apparatus of claim 7, wherein the look-up table extraction module is specifically configured to:

If the DPD model is based on a memory polynomial with the maximum memory depth of M, wherein M is an integer greater than or equal to 1, dividing the weighted LUTs into M groups according to the ascending order or the descending order of the memory depth of each LUT, wherein each group contains the same number of LUTs, and extracting one LUT from each group of LUTs respectively.

10. The apparatus according to any of claims 7 to 9, wherein the sample rate boost module is specifically configured to: and increasing the sampling rate of the input signal and the output signal of the power amplifier to K times, wherein K is an integer larger than 1.

11. A communications apparatus, comprising: the system comprises a processor, a memory and a transceiver, wherein the processor, the memory and the transceiver are connected through a bus;

The processor is used for reading the program in the memory and executing:

The sampling rate of an input signal and an output signal of the power amplifier is improved;

Determining a power amplifier characteristic coefficient according to the DPD model and by using the input signal and the output signal after the sampling rate is increased;

obtaining a look-up table (LUT) according to the power amplifier characteristic coefficient and the input signal with the improved sampling rate;

and weighting each LUT according to the weight of each LUT, and extracting the weighted LUTs.