CN110520977A

CN110520977A - Multilayer One Time Programmable persistent memory unit and preparation method thereof

Info

Publication number: CN110520977A
Application number: CN201780089270.6A
Authority: CN
Inventors: 彭泽忠
Original assignee: Chengdu Ppm Technology Ltd
Current assignee: Chengdu Ppm Technology Ltd
Priority date: 2017-02-14
Filing date: 2017-08-28
Publication date: 2019-11-29
Also published as: WO2018149109A1

Abstract

Multilayer One Time Programmable persistent memory unit and preparation method thereof, is related to memory technology.The present invention provides a kind of multilayer One Time Programmable persistent memory unit, contains: at least two layers of One Time Programmable persistent storage module, a layer heap are stacked in the upper surface of another layer；Each layer of at least two layers One Time Programmable persistent storage module, comprising M row made of useful reverse phase doped semiconductor materials and N column, wherein M and N is greater than 1 positive integer；Each layer of the M row of at least two layers One Time Programmable persistent storage module and the intersection of N column is arranged in thin insulating dielectric substance, between M row and N column；The thin insulating dielectric substance is on one of top and bottom that each M row and N are arranged.Multilayer OTP persistent memory unit of the invention has high storage density.

Description

Multi-layer one-time programmable permanent memory unit and preparation method thereof

Technical Field

The present invention relates to memory technology.

Background

The memory devices and methods of manufacture disclosed herein relate to mass data storage. More particularly, the disclosed memory devices and methods of fabrication relate to one-time programmable (OTP) persistent memory technology.

Various digital storage technologies, including erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, NAND-flash memory, hard disks, Compact Disks (CD), Digital Versatile Disks (DVD), blu-ray disks registered by the blu-ray disc association, etc., have been widely used for data storage for over 50 years. However, the lifetime of storage media is typically less than 5 years to 10 years. The antifuse storage technology developed for large data storage cannot meet the requirement of mass data storage because of its very high cost and low storage density.

Therefore, for mass data storage, there is a continuing need for a high density, low cost, multi-layer one-time programmable (OTP) persistent memory cell that can store data for a relatively long period of time under harsh environmental conditions. In addition, there is a need for a method of fabricating a multi-layer OTP permanent memory cell that superimposes oppositely doped semiconductor layers (e.g., polysilicon, single crystal silicon, or amorphous silicon, etc.) on both sides of a thin dielectric layer to form an antifuse programmable diode memory array.

Disclosure of Invention

This section is an abstract and simplified form of disclosure that sets forth the basic concepts of the invention and is further described below in the detailed description. This abstract is not intended to be used to determine the scope of the claimed subject matter.

The memory device disclosed herein relates to the high density, highly reliable and low cost multilayer One Time Programmable (OTP) persistent memory cell described above for mass data storage that can store data for a relatively long period of time under harsh environmental conditions. In addition, the invention discloses a method for preparing the multilayer OTP permanent memory unit, which is to superpose the opposite doped semiconductor material (such as polysilicon, monocrystalline silicon and the like) on two sides of a thin dielectric layer to form an antifuse programmable diode memory array.

A multi-layer one-time programmable (OTP) nonvolatile memory cell is disclosed that includes at least two layers of OTP nonvolatile memory modules stacked on top of one another and a layer of insulating dielectric material. Each layer of the OTP permanent memory module includes M rows and N columns made of a counter-doped semiconductor material, where M and N are positive integers greater than 1. In one embodiment, a one-time programmable (OTP) nonvolatile memory module of the disclosed multi-layer OTP nonvolatile memory includes M rows and N columns of conductors. A thin insulating dielectric material is located at the intersection of the M rows and N columns of each OTP permanent memory module, and the top or bottom surface of each M row and each N column of each OTP permanent memory module. Furthermore, a thin insulating dielectric material is located between the M rows and N columns of each OTP permanent memory module. M rows of each layer of OTP nonvolatile memory module are made of p-type semiconductor material or N-type semiconductor material, and N columns of each layer of OTP nonvolatile memory module are made of semiconductor material with opposite doping. That is, if M rows of each layer of OTP nonvolatile memory modules are made of p-type semiconductor material, N columns of each layer of OTP nonvolatile memory modules are made of N-type semiconductor material, and vice versa.

Each layer of OTP permanent memory modules is stacked from bottom to top and connected at an intersection between the OTP permanent memory modules and at an intersection between M rows and N columns of the layers of OTP permanent memory modules. M rows of each layer of OTP nonvolatile memory module are positioned at the top or bottom of the N columns. The disclosed multi-level OTP persistent memory cell also includes a plurality of OTP programmable memory cells formed at an intersection of M rows and N columns of the OTP persistent memory block and at an intersection between the OTP programmable persistent memory block. Each OTP memory cell includes a p-type semiconductor region, an n-type semiconductor region, and a thin insulating dielectric region between the p-type semiconductor region and the n-type semiconductor region. Each OTP memory cell further includes at least two connection terminals located in the p-type semiconductor region and the n-type semiconductor region of each OTP memory cell. The connection terminals of each OTP memory cell are connected to each other using conductive vias (made of metal or doped polysilicon or other conductive material). A predetermined value of the thickness of the thin insulating dielectric material forming the thin insulating dielectric region of each OTP memory cell corresponds to the breakdown voltage of each OTP memory cell. A thin insulating dielectric material, such as silicon dioxide (SiO2), with a thickness of 0.5 nanometers (nm) to 4nm corresponds to a breakdown voltage of approximately 3 volts to 10 volts.

A method of fabricating a multi-layer one-time programmable (OTP) permanent memory cell using planar deposition and etching of a semiconductor, such as polysilicon or silicon, is also disclosed. The method of the present invention includes disposing a semiconductor material on a top planar surface of a wafer containing completed memory peripheral circuitry using a deposition process or an epitaxial process; forming a p-type or n-type semiconductor material doped in opposite phase by using an ion implantation process or a diffusion process; removing the redundant part of the anti-phase doped semiconductor material by using a photoetching mask process and an etching process to form strip-shaped semiconductors for forming M rows or N columns of the OTP permanent memory; filling strip-shaped semiconductor materials which are formed into M rows or N columns of the OTP permanent memory module with insulating dielectric materials by adopting a planarization process; removing the excess part of the strip-shaped semiconductor which is filled with the insulating dielectric material and overflows M rows or N columns of the OTP permanent memory module by using a chemical mechanical polishing process; creating a thin insulating dielectric film, such as silicon dioxide (SiO2), on top of the filled OTP permanent memory module M rows or N columns of strip-like semiconductor material using a thermal oxidation process, a low temperature chemical vapor deposition process, or an Atomic Layer Deposition (ALD) process; repeating the above method for a predetermined number of times, and stacking each layer of OTP permanent memory modules from the lower vertical direction to the upper vertical direction symmetrically to form a plurality of layers of OTP permanent memory cells.

Another method of making a multi-layer one-time programmable (OTP) persistent memory cell is also disclosed. Such a method comprises: depositing a thick layer of insulating dielectric material on a top planar surface of a wafer containing completed memory peripheral circuitry; forming a groove on the deposited thick insulating dielectric material layer by using a masking corrosion process and a plasma etching process, wherein the groove is used as a position of a row or a column of the OTP permanent memory module; depositing a semiconductor material in the constructed trench; counter-doping the deposited semiconductor material with p-type or n-type impurities using a diffusion or ion implantation process; removing the excessively deposited reverse-phase doped semiconductor material from the reverse-phase doped semiconductor material by adopting a conventional planarization process to form M rows or N columns of the OTP permanent memory module; creating a layer of insulating dielectric thin film on the M rows or N columns of the OTP permanent memory module by using a thermal oxidation process or a thermal deposition process or using an ALD (atomic layer deposition) process; repeating the method for a preset number of times, and symmetrically stacking each layer of OTP permanent memory modules built from the lower vertical direction to the upper direction to form a plurality of layers of OTP permanent memory cells. A thin insulating dielectric film on M rows or N columns of the OTP permanent memory module is used as a programmable dielectric material.

The method disclosed herein forms a multi-level one-time programmable (OTP) permanent memory cell using an antifuse mechanism such as "poly/thin oxide/poly", where "poly" refers to polysilicon and thin oxide refers to a thin insulating dielectric material. Methods disclosed herein, such as stacking p-poly/thin oxide/n-poly/thin oxide/p-poly/thin oxide, form vertical multi-layer high density memory, where "p-poly" refers to p-type doped polysilicon and "n-poly" refers to n-type doped polysilicon. In one embodiment, the doped polysilicon is replaced with silicon (Si). In one embodiment, a thin oxide is thermally grown or deposited over the bottom polysilicon layer. The thin oxide may also be replaced by other dielectric films such as nitride or a combination of oxide and nitride. Each layer of the multi-layer OTP nonvolatile memory cell is formed with a programmable p-n junction diode with oppositely doped polysilicon or silicon on the bottom and top, thereby significantly increasing the stacked storage density at low cost. A multi-level memory array in a multi-level OTP permanent memory cell includes a programmable diode. N-channel metal oxide semiconductor (NMOS) transistors and P-channel metal oxide semiconductor (PMOS) transistors are used for programming circuitry, sensing circuitry, and decoding circuitry. For example, a p-poly/thin oxide/n-poly defined programmable diode prevents reverse current from being biased into unselected rows and unselected columns. The P-type polysilicon and n-type polysilicon also serve as row and column connecting lines, eliminating the need for expensive metal lines on top of each polysilicon to increase memory density.

The invention discloses a multilayer one-time programmable (OTP) permanent memory cell, which is an OTP permanent memory cell with high density and low cost. The prepared multilayer OTP permanent memory cell has high storage density. For example, the methods disclosed herein can produce 10 Terabyte (TB) multi-layer OTP permanent memory using a 10 nanometer (nm) silicon process on a 25mm by 25mm area chip. The resulting multi-layer OTP persistent memory cell has a very small form factor and a permanent data retention lifetime, e.g., greater than 100 years.

In one or more embodiments, a related system includes circuitry for implementing the methods disclosed herein. The circuitry may be any combination of hardware and/or firmware to configure the disclosed methods according to the design choices of a system designer. In addition, various structural elements may be used according to design choices of a system designer.

Drawings

The foregoing summary, as well as the following detailed description of the invention, will be better understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, there is shown in the drawings exemplary constructions of the invention. However, the present invention is not limited to the specific methods and components disclosed herein. The description of method steps or components referenced by numerals in the figures applies to the description of method steps or components shown by the same numerals in subsequent figures.

FIG. 1 illustrates a perspective view of a single layer OTP memory module in a multi-layer OTP persistent memory cell.

FIG. 2 illustrates a perspective view of a multi-layer OTP-persistent memory cell formed by stacking two OTP-persistent memory modules one on top of the other.

FIG. 3 illustrates a block diagram of a one-time programmable memory cell.

Fig. 4 illustrates a circuit diagram of the otp memory cell shown in fig. 3.

FIG. 5 illustrates a perspective view of one single layer one-time-programmable-persistent-memory-module embodiment of one-time-programmable-memory-cells formed at the intersection of a row and a column of the one-time-programmable-persistent-memory-module.

FIG. 6 illustrates one-time programmable memory cells formed at the row-column intersection of one-time programmable persistent memory modules as shown in FIG. 5.

FIG. 7 illustrates a partial front view of a multi-layer one-time programmable persistent memory cell.

FIG. 8 illustrates a circuit diagram of a multi-level one-time programmable persistent memory cell as shown in FIG. 7.

FIG. 9 illustrates a partial side view of one embodiment of a multi-layer one-time programmable memory cell.

FIG. 10 illustrates a circuit diagram of one embodiment of the multi-layer one time programmable persistent memory cell shown in FIG. 9.

FIG. 11 illustrates a top view of a multi-layer one-time programmable persistent memory cell.

FIG. 12 illustrates a front view of a plurality of one time programmable persistent memory module layers stacked in a bottom-up orientation to form a multi-layer one time programmable persistent memory unit.

Figure 13 illustrates a side view of a front view showing one embodiment of otp permanent memory modules stacked in a bottom-up orientation to form a multi-layer otp memory cell.

Figure 14 illustrates a top view of one embodiment showing a plurality of otp permanent memory module layers adjacent to each other with rows and columns constructed of oppositely doped semiconductor materials interconnected by conductive vias.

Fig. 15 illustrates a cross-sectional view of a multi-layer otp permanent memory cell showing interconnection of doped semiconductor material row lines on different layers of the multi-layer otp memory cell formed by stacking a plurality of otp permanent memory module layers.

Fig. 16 illustrates a cross-sectional view of a multi-layer otp permanent memory cell showing interconnection of oppositely doped semiconductor material column lines on different layers of the multi-layer otp memory cell formed by stacking a plurality of otp permanent memory module layers.

Fig. 17-19 illustrate circuit diagrams of memory array circuits of various embodiments in which a plurality of one time programmable permanent memory modules are stacked to form a multi-layer one time programmable permanent memory cell.

Fig. 20 illustrates a method of fabricating a multi-layer one-time programmable permanent memory cell using a planar deposition process and a semiconductor material etching process.

Fig. 21 illustrates a method of fabricating a multi-layer otp permanent memory cell by building a trench in an insulating dielectric material and filling the trench with a semiconductor material.

Fig. 22 is a partial schematic view of an embodiment of a schottky contact.

Detailed Description

The single-layer OTP nonvolatile memory block 101 shown in fig. 1 constitutes one layer of a multi-layer OTP memory cell 100. The OTP permanent memory module 101 includes M rows 102 and N columns 103 of counter-doped semiconductor material, where M and N are positive integers greater than 1. For example, the OTP persistent memory module 101 illustrated in FIG. 1 includes at least two rows 102 and at least two columns 103. OTP persistent memory module 101 includes first and second rows A11 and A12 at the top of first and second columns B11 and B12, as shown in FIG. 1. M and N may be any integer between 1 and 1024 × 1204. The rows 102 are made of p-type or n-type semiconductor material, while the columns 103 are made of inverted p-type or n-type semiconductor material. For example, if the first row a11 and the second row a12 are p-type semiconductor material, the first column B11 and the second column B12 are n-type semiconductor material, and vice versa.

The rows 102 and columns 103 of the one-time programmable (OTP) nonvolatile memory module 101 are aligned such that the rows 102 and columns 103 intersect perpendicularly to each other for best results. In one embodiment, rows 102 and columns 103 take on different configurations, e.g., non-linear, in a non-perpendicular direction, or in a curved manner, etc. Different configurations of rows 102 and columns 103 produce different results. The rows 102 may be referred to as word lines and the columns 103 may be referred to as bit lines accordingly. Alternatively, rows 102 are referred to as bit lines and columns 103 are referred to as word lines.

The one-time programmable (OTP) nonvolatile memory block 101 further includes a thin layer of insulating dielectric material 105, e.g., silicon dioxide (SiO2), on the

top surfaces

102a, 103a of the rows 102 and columns 103, respectively. In one embodiment (not shown), a layer of insulating dielectric material 105 (e.g., SiO2) is located on the bottom surfaces 102b of the rows 102 and the bottom surfaces 103b of the columns 103, respectively. In fig. 1, insulating dielectric material 105 is indicated as a shaded region. Excess insulating dielectric material 105 is removed outside the intersection 104 of the rows 102 and columns 103 using an etching process, after which the rows 102 and columns 103 are filled with a layer of insulating dielectric material 105 in a planarization process. In fig. 1, the filled insulating dielectric layer is indicated as a non-shaded region above the upper surface of the shaded

regions

102a and 103 a.

FIG. 2 illustrates a perspective view of a multi-layer one-time programmable (OTP) nonvolatile memory cell 100 formed by stacking 101 and 106 two layers of OTP nonvolatile memory blocks. The disclosed multi-layer OTP nonvolatile memory cell 100 includes at least two stacked OTP

nonvolatile memory modules

101 and 106 and an insulating dielectric material 105. Each layer of OTP nonvolatile memory blocks 101 and 106 includes M

rows

102 and 107, respectively, and

N columns

103 and 108, respectively, the rows and columns being formed of an inversely doped semiconductor material, where M and N are positive integers greater than 1. For example, a first layer of OTP persistent memory blocks 101 includes two rows 102 and two columns 103 of counter-doped semiconductor material, and a second layer of OTP persistent memory blocks 106 includes two rows 107 and two columns 108 of counter-doped semiconductor material. As shown in fig. 2,

rows

102 and 107, belonging to OTP persistent memory blocks 101 and 106, respectively, are located at the top of

columns

103 and 108, respectively. In one embodiment (not shown),

rows

102 and 107, belonging to OTP nonvolatile memory blocks 101 and 106, respectively, are located at the bottom of

columns

103 and 108, respectively. For optimal data storage,

rows

102 and 107, respectively belonging to OTP persistent memory blocks 101 and 106, and

columns

103 and 108 are all straight and perpendicular to each other.

As shown in FIG. 2, each one-time programmable (OTP)

persistent memory module

101 and 106 is stacked in a bottom-up orientation with row 102 and row 107 belonging to OTP

persistent memory modules

101 and 106, respectively, column 103 and column 108 being connected at

intersections

104 and 109, respectively, and 110 being the intersection between OTP

persistent memory modules

101 and 106. For example, a second OTP permanent memory module 106 includes a first row a21, a second row a22, a first column B21, and a second column B22, the module 106 stacked on top of the first OTP permanent memory module 101, the module 101 including a first row a11, a second row a12, a first column B11, and a second column B12. Insulating dielectric material 105 is located at the intersection 104 of row 102 and column 103 of OTP permanent memory module 101, between 102 and 103, at the intersection 109 of row 107 and column 108 of module 106, between 107 and 108, respectively, and also at top surface 102a of M rows 102, top surface 103a of N columns 103, top surface 107a of M rows 107, and top surface 108a of N columns 108 of module 106, respectively. In one embodiment (not shown), insulating dielectric material 105 is located at the

intersections

104, 109 of the

rows

102, 107 and

columns

103, 108 of the OTP

permanent memory modules

101, 106, respectively, between 102, 103 and 107, 108, and also at the bottom surfaces 102b, 107b of the

M rows

102, 107 and

bottom surfaces

103b, 108b of the

N columns

103, 108 of the OTP

permanent memory modules

101, 106, respectively.

The intersections between

rows

102, 107 and

columns

103, 108 of one-time programmable (OTP) persistent memory blocks 101, 106 are 104 and 109, respectively, and the intersections between OTP persistent memory blocks 101 and 106 in multi-level OTP persistent memory cell 100 are 110. FIG. 1 shows OTP memory cells at the intersection 104 of A11-B11, A11-B12, A12-B12, and A12-B11, respectively. In addition, OTP memory cells are also located at the intersection of A11-B21, A11-B22, A12-B21, A12-B22, A21-B21, A21-B22, A22-B22, and A22-B21, as shown in FIG. 2. Each layer of OTP nonvolatile memory blocks 101 and 106 includes four OTP memory cells. For example, OTP persistent memory module 101 includes four

OTP memory cells

111a, 111b, 111c, and 111d, as shown in FIG. 6. A multi-level OTP persistent memory cell 100 having at least two levels of OTP persistent memory blocks 101 and 106 includes twelve OTP memory cells. Each OTP memory cell includes a p-type semiconductor region 112, an n-type semiconductor region 114 and a thin insulating dielectric region 113 located between the p-type semiconductor region 112 and the n-type semiconductor region 114 as shown in fig. 3. A thin insulating dielectric region 113 separates the p-type semiconductor region 112 and the n-type semiconductor region 114. Each OTP memory cell also includes at least two

connection terminals

116a and 116b disposed on the p-type semiconductor region 112 and the n-type semiconductor region 114 of each OTP memory cell, as shown in fig. 6. The connection terminals, e.g., 116a and 116b, of each OTP memory cell are interconnected using conductive vias 1501, e.g., metal vias in fig. 15-16. Consider rows a11, a12 and a21, a22 of the multi-layer OTP permanent memory cell 100 shown in fig. 2, which are p-type semiconductor material, placed on top of columns B11, B12 and B21, B22, respectively, of n-type semiconductor material. The rows of p-type semiconductor material rows a11, a12, a21, a22 and columns of n-type semiconductor material B11, B12, B21, B22 form the p-type semiconductor region 112 and the n-type semiconductor region 114, respectively, of each OTP memory cell.

Fig. 3 illustrates a block diagram of a one-time programmable (OTP) memory cell 111. The OTP memory cell 111 includes a p-type semiconductor region 112, an n-type semiconductor region 114, and a thin insulating dielectric region 113 located between the p-type semiconductor region 112 and the n-type semiconductor region 114. The thickness of the thin insulating dielectric material 105 forming the thin insulating dielectric region 113 of each OTP memory cell 111 has a predetermined value corresponding to the breakdown voltage of each OTP memory cell. The thickness of the thin insulating dielectric material 105 forming the thin insulating dielectric region 113 in each OTP memory cell 111 is set to be both suitable for the programming voltage and to avoid leakage, since a thick dielectric material requires a higher programming voltage, while too thin a dielectric material causes unwanted breakdown and leakage. The insulating dielectric material 105, for example, silicon dioxide (SiO2) has a thickness of about 0.5 nanometers (nm) to 4nm, silicon nitride (Si)₃N₄) Is thickThe degree is greater than 4 nm. In one embodiment, other insulating dielectric materials having a thickness of less than 0.5 nanometers are used. Interchanging the positions of the p-type semiconductor region 112 and the n-type semiconductor region 114 may interchange the orientations of the OTP memory cell 111.

Fig. 4 illustrates an equivalent circuit diagram 115 of the one-time programmable (OTP) memory cell 111 shown in fig. 3. The OTP memory cell 111 is electrically represented as a diode in series with a programmable anti-fuse capacitor. The orientation of the OTP memory cell 111 shown in fig. 4 corresponds to the OTP memory cell 111 in fig. 3 with the p-type semiconductor region 112, the insulating dielectric region 113 and the n-type semiconductor region 114 arranged in that order. The OTP memory cell 111 blocks reverse current from other programmed bits.

Fig. 5 illustrates a perspective view of an embodiment of a single layer one-time programmable (OTP) nonvolatile memory block 101 with corresponding

OTP memory cells

111a, 111b, 111c, and 111d formed at the intersection 104 of the row 102 and column 103 of the OTP nonvolatile memory block 101 as shown in fig. 6. In this embodiment, OTP persistent memory module 101 includes M rows 102 and N columns 103 of conductors, where M and N are positive integers greater than 1. The conductor is, for example, a metal silicide, or doped polysilicon, or other conductive material. Polysilicon is a combination of polycrystalline silicon and silicide. In one example shown in fig. 5, OTP persistent memory module 101 includes at least two rows 102 and at least two columns 103. The rows 102 and columns 103 of the OTP persistent memory module 101 intersect at 104 to form a plurality of

OTP memory cells

111a, 111b, 111c and 111d as shown in fig. 6, the detailed description of which has been disclosed in fig. 2. The shaded region at the intersection 104 of the row 102 and column 103 of the OTP persistent memory module 101 shown in fig. 5 represents the insulating dielectric region 113 of each

OTP memory cell

111a, 111b, 111c, and 111 d.

FIG. 6 illustrates one-time programmable (OTP)

memory cells

111a, 111b, 111c, and 111d formed at the intersection 104 of the rows 102 and columns 103 of the OTP persistent memory block 101 shown in FIG. 5. The OTP permanent memory module 101 includes at least two rows 102 and two columns 103 of conductors forming four

OTP memory cells

111a, 111b, 111c, and 111d at four intersections 104, shown as four separate blocks in fig. 6. The

top connection terminals

116a, 116c and 116e, 116g of the four

OTP memory cells

111a, 111b, 111c and 111d are connected with two

row lines

117a and 117c, respectively. The

bottom connection terminals

116b, 116h and 116d, 116f of the four

OTP memory cells

111a, 111b, 111c and 111d are connected with two

column lines

117d and 117b, respectively.

In fig. 7-13 and 15-19 disclosed hereinafter, "L", which is a lower case of L, indicates that the layer number or module number of one OTP persistent memory module (e.g., 101 or 106) constituting the multi-layer OTP persistent memory cell 100 shown in fig. 2 may be any integer between 1 and 1024; "R" represents a row line on a layer or on one OTP persistent memory module (e.g., 101 or 106); "C" represents a column line; "x" represents the column line number; "y" represents a row line number.

Fig. 7 illustrates a partial front view of the multi-layer one-time programmable (OTP) nonvolatile memory cell 100 shown in fig. 2. As illustrated in FIG. 7, the row line layer (R)_lY) is located at (C)_l,x-1)，(C_lX) and (C)_lAnd x +1) on top of the column line layer. (C)_lAnd x) denotes a first layer column line having a column line number x. Also, (C)_lX-1) and (C)_lX +1) is at the column line (C)_lX) two column lines on either side. As shown in fig. 7, the row line layer is formed of a p-type semiconductor material, such as p-doped polysilicon (p-poly), while the column line layer is formed of an n-type semiconductor material, such as n-doped polysilicon (n-poly). Line layer (R)_lY) and a column line (C)_l+1,x-1),(C_l,x-1),(C_l+1,x),(C_l,x),(C_l+1X +1), and (C)₁X +1), and insulating dielectric material 105 at an intersection. At this level of row line (R) when a programming voltage is applied₁Y) and column line (C)₁X) the insulating dielectric material 105 at the intersection is broken down forming a p-n junction diode at the intersection of the row and column lines of the layer. The p-poly and n-poly materials diffuse through the broken down insulating dielectric material 105 forming a p-n junction diode. The distance between adjacent row lines and adjacent columns is kept at a minimum in process design rules to adequately achieve good memory density. In order to achieve better storage densityAnd the distance between the adjacent row line and the adjacent column line on each layer adopts an optimized value which is larger than the lowest value of the process design rule.

FIG. 8 illustrates a circuit diagram of a multi-level one-time programmable (OTP) nonvolatile memory cell memory array as shown in FIG. 7. The circuit diagram is shown in each column line (C)_l+1,x-1),(C_l,x-1),(C_l+1,x),(C_l,x),(C_l+1,x+1),(C_lX +1) and column line (R)_lY), a p-n junction diode 801 formed as a result of breakdown of the insulating dielectric material 105, as disclosed in detail in fig. 7.

FIG. 9 illustrates a partial side view of one embodiment of a multi-layer one-time programmable (OTP) nonvolatile memory cell 100 as shown in FIG. 2. In this embodiment, the column lines (Cl, x) of one OTP nonvolatile memory module are placed on the same row lines (R)_l,y-1),(R_l,y),(R_lY +1) and underlying row line (R)_l-1,y-1),(R_l-1,y),(R_l-1Y + 1). Row line (R)_lAnd y) denotes the number y on layer 1. Also, (R)_lY-1) and (R)_lY +1) in the row line (R)_lY) on both sides. As illustrated in fig. 9, the row lines both above and below the layer are of p-type semiconductor material, e.g., p-doped polysilicon (p-poly), while the column lines are of n-type semiconductor material, e.g., n-doped polysilicon (n-poly). The layer of row line (C)_lX) and column line (R)_l,y-1),(R_l,y),(R_l,y+1)(R_l-1,y-1),(R_l-1,y),(R_l-1Y +1), and insulating dielectric material 105 at an intersection. At the column line (C) when the programming voltage is applied₁X) and row line (R)₁Y) the insulating dielectric material 105 at the intersection is broken down, forming a p-n junction diode at the intersection of the row and column lines of the layer. The p-poly material and n-poly material diffuse through the broken down insulating dielectric material 105 forming a p-n junction diode.

FIG. 10 illustrates a circuit diagram of a memory array of one embodiment of a multi-level one-time programmable (OTP) nonvolatile memory cell shown in FIG. 9. The circuit diagram shows that at each row line ((R)_l,y-1),(R_l,y),(R_l,y+1)，(R_l-1,y-1),(R_l-1,y),(R_l-1Y +1) and a column line (C)_lX) of the semiconductor substrate, a p-n junction diode 1001 formed as a result of breaking down the insulating dielectric material 105, as disclosed in detail in fig. 9.

FIG. 11 illustrates a top view of a multi-layer one-time programmable (OTP) nonvolatile memory cell 100. As shown in fig. 11, the column lines are comprised of n-type semiconductor material, such as n-type doped polysilicon (n-poly), and the row lines are comprised of p-type semiconductor material, such as p-type doped polysilicon (p-poly). In one embodiment (not shown), the column lines are p-poly and the row lines are n-poly. The row lines of the OTP nonvolatile memory block intersect the column lines of the OTP nonvolatile memory block, and OTP nonvolatile memory cells are formed at the intersections of the row lines and the column lines. (C)_lAnd x) represents column lines numbered x on layer 1. Also, (C)_l,x-1)and(C_lX +1) is at the column line (C)_lX) two column lines on either side. (R)_lAnd y) represents row lines numbered y on layer 1. Also, (R)_l,y-1)and(R_lY +1) is at the row line (R)_lY) two row lines on either side.

Fig. 12 shows a front view of a multi-level one-time programmable (OTP) nonvolatile memory cell 100 formed by stacking a plurality of OTP nonvolatile memory modules in a bottom-up orientation. In the OTP nonvolatile memory block shown in fig. 12, the column lines are placed under the row lines, forming a multi-layer OTP nonvolatile memory cell 100. FIG. 12 is a front view of a plurality of OTP permanent memory blocks at their intersections with row lines. Comprising row lines (R)₁Y) and column line (C)₁X) a1 st (first) layer stacked on the substrate containing the row line (R)₀Y) and column line (C)₀And x) above layer 0. Likewise, comprising row lines (R)_l+1Y) and column line (C)_l+1X) the 1+1 th layer symmetrically stacked on the first layer containing the row line (R)₁Y) and column line (C)₁And x) above layer 1. And so on to obtain a multi-level OTP persistent memory cell 100.

The P-type semiconductor material row line is stacked on the N-type semiconductor material column line, and then the column line layer is stacked on the row line, so that a symmetrical layout of 'row/column/row/column', namely P/N/P/N, is obtained. Therefore, to add one layer to a one-time programmable (OTP) nonvolatile memory cell 100, a thin insulating dielectric material 105 and a layer of counter-doped semiconductor material (e.g., polysilicon) are added. On the OTP nonvolatile memory cell 100, a new OTP nonvolatile memory module is created with each additional thin insulating dielectric material 105 and counter-doped semiconductor material. The stacked layers, i.e., OTP permanent memory module layers, run on top of a silicon (Si) substrate 1201 and a gate oxide 1202 deposited as an insulating dielectric layer. Logic and programming circuitry 1203 is used to arrange the programming voltages to break down the insulating dielectric material 105 in the OTP permanent memory block of the multi-layer OTP permanent memory cell 100 at the intersection of the row and column lines. For example, when programming or reading the multi-layer OTP permanent memory cell 100, a positive voltage is applied to selected row lines and selected column lines in the memory module layers, allowing current to flow from the row lines of p-type semiconductor material to the column lines of n-type semiconductor material, resulting in a positive p-n junction conductance.

FIG. 13 illustrates a side view of an embodiment of one-time programmable (OTP) nonvolatile memory modules stacked in a bottom-up orientation to form a multi-level OTP nonvolatile memory cell 100. In the OTP nonvolatile memory block shown in fig. 13, the column lines are located below the row lines, forming a multi-layer OTP nonvolatile memory cell 100. The row and column lines of the OTP nonvolatile memory module are respectively composed of P-type semiconductor material (e.g., boron doped polysilicon, P-poly or P-type copper oxide) and N-type semiconductor material (e.g., phosphorus doped or arsenic doped polysilicon, N-poly, or N-type indium zinc oxide). FIG. 13 is a side view of an OTP permanent memory block at an intersection of a column line and a plurality of OTP permanent memory block row lines. Comprising row lines (R)₁Y) and column lines (C1, x) stacked on a first (1) layer containing row lines (R)₀Y) and column line (C)₀And x) above layer 0. Likewise, comprising row lines (R)_l+1, y) and column line (C)_lThe "L" +1 layer of +1, x (the "L" is a lower case of L) is stacked on the column line (R)_lY) and column line (C)_lX) on the "l" th layer, etc., fromA multi-level OTP permanent memory cell 100 is obtained. A number of layers, or OTP nonvolatile memory module layers, stacked symmetrically, are run on a silicon substrate 1201 with a gate oxide layer 1202 of an insulating dielectric layer deposited thereon. Logic and programming circuitry 1203 is used to arrange the programming voltages to break down the insulating dielectric material 105 in the OTP permanent memory block of the multi-layer OTP permanent memory cell 100 at the intersection of the row and column lines.

Fig. 14 illustrates a top view of an embodiment showing a plurality of one-time programmable (OTP) nonvolatile memory blocks 101, 106, 118, and 119 positioned adjacent to one another in layers, wherein the row and column lines of oppositely doped semiconductor material are interconnected by conductive vias, such as metal or doped polysilicon vias. The row and column lines of the OTP permanent memory blocks (e.g., 101 and 118) are interconnected with the row and column lines of adjacent layers of OTP permanent memory blocks (e.g., 106 and 119) using the conductive vias described above.

Fig. 15 illustrates a cross-sectional view of a multi-layer one-time programmable (OTP) nonvolatile memory cell along a row line, illustrating the interconnection between row lines of doped semiconductor material (e.g., p-type semiconductor material) on different layers of the stacked multi-layer OTP nonvolatile memory cell. Conductive via 1501 is used to connect row lines on different layers stacked to form a multi-layer OTP permanent memory cell.

Fig. 16 illustrates a cross-sectional view along a column line of a multi-layer one-time programmable (OTP) nonvolatile memory cell illustrating the interconnection between column lines of doped semiconductor material (e.g., n-type semiconductor material) on different layers of the stacked multi-layer OTP nonvolatile memory cell. Conductive vias 1501 are used to stack column lines on different layers that form a multi-layer OTP permanent memory cell.

Fig. 17-19 illustrate circuit diagrams of a memory array of an embodiment of a multi-layer OTP memory cell 100 formed by stacking layers of a one-time programmable (OPT) permanent memory module. FIG. 17 illustrates a circuit diagram of a memory array of multi-level OTP nonvolatile memory cells 100 showing a level of word lines, i.e., row lines (R) on the same OTP nonvolatile memory block_l,y+1),(R_l,y)，(R_l,y-1)，Bit line or column line (C) connected to the top layer_l+1,x-1),(C_l+1,x),(C_l+1X +1) and underlying bit line (C)_l,x-1),(C_l,x),(C_lX + 1). Top and bottom OTP memory cells connected to bit line C_l+1And C_lAnd share a common word line R_l。

FIG. 18 illustrates a circuit diagram of a multi-level OTP nonvolatile memory cell 100 memory array circuit showing one level of column line (C)_l,x-1),(C_l,x),(C_lX +1), row lines ((R) connected to adjacent top and bottom layers_l+1,y+1),(R_l,y+1),(R_l+1,y),(R_l,y),(R_l+1,y-1),(R_lY-1). Top layer R_l+1Formed OTP memory cell and bottom layer R_lFormed OTP memory cells sharing the same bit line C_l。

FIG. 19 illustrates a circuit diagram of a memory array of a multi-level OTP nonvolatile memory cell 100 showing row lines (R) on three levels_l+1,y),(R_lY) and (R)_l-1Y) to the column lines on the adjacent four layers, i.e.: top layer alignment (C)_l+1,x-1),(C_l+1X) and (C)_l+1X +1), next to top column line (C)_l,x-1),(C_lX) and (C)_lX +1), sub-bottom column line (C)_l-1,x-1),(C_l-1X) and (C)_l-1X +1), bottom column line (C)_l-2,x-1),(C_l-2X) and (C)_l-2,x+1)。

The multi-layer one-time programmable (OTP) nonvolatile memory cell 100 further includes a multi-level decoding circuit (not shown) implemented on at least two M

row lines

102 or 107 and at least two N column lines 103 or 108 in the OTP nonvolatile memory blocks 101 and 106 shown in fig. 2. The multi-stage decoding circuit can be shared by the upper and lower stacked OTP

persistent memory modules

101 and 106. A multi-level memory array typically includes multiple levels of decoders, e.g., layer decoders, segment decoders, row decoders, column decoders, etc. A multi-level OTP nonvolatile memory cell 100 having a plurality of

row lines

102, 107 and

column lines

103, 108 employs a multi-level decoder system, such as a layer decoder, a page decoder, a segment decoder, a row decoder and a column decoder, to decode addresses of the

row lines

102, 107 and

column lines

103, 108, allowing a programming and/or reading system to access data stored in the multi-level OTP nonvolatile memory cell 100.

The operating voltage table of the multi-layer one-time programmable (OTP) nonvolatile memory cell 100 shown in fig. 2 is illustrated with the following tables 1 to 4. The operating voltmeter allows a user to press a row (R) in the multi-level OTP permanent memory cell 100_l) And column (C)_l) Defined locations, where programming and/or reading data is performed. The programming voltage (Vpp), half-programming voltage (Vphf), and read voltage (Vrd) are selected according to the process technology, electrical performance, and reliability requirements of the multi-level OTP nonvolatile memory cell 100. The user can respectively assign different voltages to the row line (R) when programming and/or reading data of the multi-layer OTP permanent memory cell 100_l) And a column line (C)_l) Selected Row (SR), Unselected Row (UR), Selected Column (SC) and Unselected Column (UC) in table 1 to table 4. Vphf (1/2Vpp) on unselected rows and unselected columns is used to reduce voltage stress during programming, thereby avoiding unnecessary programming or oxide layer reliability problems. Furthermore, R_lAnd (or) C_lThe voltage on can be charged to Vphf and allowed to float, using "Vphf" in the table&Float "stands for.

Table 1 above illustrates the multi-level one-time programmable (OTP) nonvolatile memory cell 100 shown in fig. 2, and the corresponding memory array circuit is shown in fig. 8, fig. 10, and fig. 17-19 according to the operating voltage table of option 1. The user can move a row line (R)_l) The voltage is set to the programming voltage (Vpp) and the column line (C) is set_l) The voltage is set to zero and the OTP memory cells of the multi-layer OTP permanent memory cell 100 containing the selected row line (SR) and/or the selected column line (SC) are programmed. The user can change R_lIs set to Vpp, C_lIs set to a half program voltage (Vphf) and floated (with "Vphf)&Float "means) so as to contain SR and/or Unselected Columns (UC)The unselected OTP memory cells are not programmed. The user can set R_lIs zero, C_lIs zero, the Unselected Rows (UR) and/or the selected columns SC are programmed. The user can set R_lIs zero, C_lIs Vphf&Float, program UR and/or UC. Also, the user can set R_lVoltage is circuit read voltage (Vrd) and C_lConnected to a Sensing circuit (Sensing) for reading the SR and/or SC. The user can set R_lVoltage is Vrd and set C_lThe voltage is Vrd, and SR and/or UC are read. The user can set R_lIs zero, and C is_lConnected to the Sensing circuit (Sensing) to read UR and/or SC. The user can change R_lSet to zero voltage and C_lSet to Vrd, read UR and/or UC.

Table 2 above illustrates a multi-level one-time programmable (OTP) nonvolatile memory cell 100 as shown in fig. 2, and the corresponding memory array circuit as shown in fig. 8, fig. 10, and fig. 17-19 according to the operating voltage table of option 2. The user can set a row line (R)_l) Is zero, the column line voltage is the programming voltage (Vpp), and the OTP memory cells of the multi-layer OTP nonvolatile memory cell 100 containing the selected row line (SR) and/or the selected column line (SC) are programmed. The user can set R_lIs zero and C_lIs zero so that the unselected OTP memory cells containing SR and/or Unselected Columns (UC) are not programmed. The user can set R_lThe voltage is half the programming voltage (Vphf) and is floating (with Vphf)&Float representation), setting C_lIs Vpp, programming the Unselected Rows (UR) and/or SC. The user can set R_lIs Vphf&Float, set C_lFor zero voltage, UR and/or UC are programmed. Also, the user can set R_lIs a read voltage (Vrd) and C_lConnected to the detection circuit, reads the SR and/or SC. The user can set R_lIs Vrd and set C_lFor Vrd, SR and/or UC are read. The user can set R_lVoltage is zero and C is_lConnected to the detection circuit, reading UR and/or SC. The user can set R_lTo zero voltage, set C_lThe voltage is Vrd, UR and/or UC are read.

Table 3 above illustrates a multi-level one-time programmable (OTP) nonvolatile memory cell 100 as shown in fig. 2, and the corresponding memory array circuit as shown in fig. 8, fig. 10, and fig. 17-19 according to the operating voltage table of option 3. The user can set a row line (R)_l) Is a half programming voltage (Vphf) and the column line voltage is a negative programming voltage (-Vpp), programming the OTP memory cells of the multi-layer OTP nonvolatile memory cell 100 containing the selected row line (SR) and/or the selected column line (SC). The user can set R_lIs Vphf, C_lFloating (Float) so that unselected OTP memory cells containing SR and/or Unselected Columns (UC) are not programmed. The user can set R_lVoltage is zero, C_lIs negative Vphf, programming the Unselected Rows (UR) and/or SC. The user can set R_lIs zero and C_lThe voltages are floating (Float), UR programmed and/or UC. Also, the user can set R_lVoltage is read voltage (Vrd) and will C_lConnected to a Sensing circuit (Sensing) for reading the SR and/or SC. The user can set R_lIs Vrd and set C_lFor Vrd, SR and/or UC are read. The user can set R_lIs zero and C_lVoltage zero, UR and/or SC are read. The user can set R_lIs zero voltage and C_lFor Vrd, UR and/or UC are read.

Table 4 above illustrates the multi-level one-time programmable (OTP) nonvolatile memory cell 100 shown in fig. 2, and the corresponding memory array circuit shown in fig. 8, fig. 10, and fig. 17-19 according to the operating voltage table of option 4. By usingThe user can set a row line (R)_l) Half program voltage (Vphf) and column line (C) with negative voltages_l) At a voltage Vphf, OTP memory cells of the multi-layer OTP permanent memory cell 100 containing a Selected Row (SR) and/or a Selected Column (SC) are programmed. The user can set R_lVoltage is negative Vphf and C_lThe voltage is floating (Float) so that selected OTP memory cells containing SR and/or Unselected Columns (UC) are not programmed. The user can set R_lVoltage is zero, C_lThe voltage is negative Vphf, programming the Unselected Rows (UR) and/or SC. The user can set R_lVoltage zero sum C_lThe voltage is floating (Float), programming UR and/or UC. Also, the user can set R_lIs a read voltage (Vrd) and will C_lConnected to a Sensing circuit (Sensing) for reading the SR and/or SC. The user can set R_lVoltage Vrd, C_lThe voltage is Vrd, and SR and/or UC are read. The user can set R_lIs zero and C is_lConnected to the detection circuit, reading UR and/or SC. The user can set R_lVoltage zero sum C_lThe voltage is Vrd, UR and/or UC are read. In one embodiment, the sensing circuit is connected to a row line instead of a column line.

Fig. 20 shows an example of a method for fabricating the multi-layer one-time programmable (OTP) nonvolatile memory cell 100 shown in fig. 2 using a planar deposition process and a semiconductor material etching process. In the disclosed method, step 2001 is to use a deposition process or an epitaxial process to place a semiconductor material (e.g., polysilicon, silicon, etc.) on the top planar surface of the wafer containing the completed memory peripheral circuits. The memory peripheral circuitry provides an access pattern to the multi-level OTP persistent memory cell 100. Step 2002 is to counter-dope the semiconductor material with a p-type dopant or an n-type dopant using an ion implantation process or a diffusion process. Step 2003 is to remove excess portions of the counter-doped semiconductor material using a photolithographic masking and etching process to prepare a strip of semiconductor material from the counter-doped semiconductor material to form M rows 102 or N columns 103 in the OTP persistent memory module 101 as shown in fig. 2, where M and N are positive integers greater than 1. The OTP nonvolatile memory block 101 constitutes one layer of a multi-layer OTP nonvolatile memory cell 100. Step 2004 is to fill insulating dielectric material 105 with a planarization process over the M rows 102 or N columns 103 of strip-shaped semiconductor material in the formed OTP permanent memory module 101. Step 2005 is to remove excess insulating dielectric material 105 that overfills or fills higher than M rows 102 or N columns 103 of strip semiconductor material using a chemical and mechanical polishing process. Step 2006 is to form a thin insulating dielectric film on top of the filled M rows 102 or N columns 103 of the OTP permanent memory module 101 using a thermal oxidation process, or a low temperature chemical vapor deposition process, or an Atomic Layer Deposition (ALD) process. Step 2007 is to repeat the above method to a predetermined number of times, create each layer of OTP persistent memory modules 106 in a direction from bottom to top (as shown in fig. 2), stack OTP persistent memory modules 106 symmetrically, resulting in a multi-layer OTP persistent memory cell 100. A plurality of OTP memory cells, such as 111a, 111b, 111c, and 111d in fig. 6, are formed at the intersection 104 of M rows 102 or N columns 103 of OTP persistent memory block 101, and at the intersection 110 of OTP persistent memory block 101 and another layer of OTP persistent memory block 106 located above it. Creating another thin insulating dielectric film on top of the topmost OTP persistent memory block 106 and stacking M rows or N columns of oppositely doped semiconductor material (p-type semiconductor material or N-type semiconductor material) is repeated to increase the storage capacity of the OTP memory cells, e.g., 111a, 111b, 111c and 111d, in the multi-layer OTP persistent memory cell 100.

Fig. 21 shows an example of a method of fabricating a multi-layer one-time programmable (OTP) nonvolatile memory cell 100 as shown in fig. 2 by forming a trench in an insulating dielectric material and filling the trench with a semiconductor material. In the method disclosed herein, step 2101 is the deposition of a thick layer of insulating dielectric material on the top planar surface of a wafer containing completed memory peripheral circuits. Step 2102 is to construct trenches in the deposited thick insulating dielectric material using a blanket etch process to locate row or column lines of a layer of permanent memory blocks. Step 2103 is depositing a semiconductor material over the built trench. Step 2104 is to counter-dope the deposited semiconductor material with a p-type or n-type dopant using a diffusion process or an ion implantation process. In one embodiment, an in-situ deposition method is used to achieve high concentration doping, and

steps

2103 and 2104 are combined into a single step. Step 2105 is removing the excess deposited counter-doped semiconductor material using a conventional planarization process to form M rows 102 or N columns 103 of the OTP permanent memory module 101, where M and N are positive integers greater than 1. Then, at step 2106, a thick layer of insulating dielectric material is deposited on the top planar surface of the wafer. Step 2107 constructs trenches in the thick insulating dielectric material using a masked etch process for locating rows or columns of the OTP permanent memory module. The etching process is terminated until the last deposited semiconductor material is reached. Step 2108 is to create a thin insulating dielectric film on the M rows 102 or N columns 103 of the OTP permanent memory module 101 using a thermal oxidation process or a thermal deposition process or an Atomic Layer Deposition (ALD) process. As shown in fig. 2, a thin insulating dielectric film on each M row 102 or N column 103 of the OTP nonvolatile memory module 101 is used as a programmable dielectric material. Step 2109 is to repeat the above-mentioned

methods

2103, 2104, 2105, 2106, 2107 and 2108 to a predetermined number of times, create each layer of OTP persistent memory module 106 as shown in fig. 2 in a direction from the lower vertical direction to the upper direction, stack the OTP persistent memory modules 106 symmetrically, and generate the multi-layer OTP persistent memory cell 100. The storage capacity of the resulting OTP memory cells, such as 111a, 111b, 111c and 111d shown in fig. 6, can be increased, and a detailed description thereof is disclosed in fig. 20.

An embodiment of a schottky contact:

a multi-level one-time programmable persistent memory cell comprising:

at least two layers of one-time programmable permanent memory modules, one layer stacked on top of the other; each of the at least two layers of otp-nonvolatile memory blocks includes M row lines and N column lines, where M and N are positive integers greater than 1;

at each intersection point, the material of the row line M and the column line N is respectively two materials which are required for generating Schottky contact at the intersection point, for example, the material of the row line is metal which can form a Schottky tube, such as Al, Ag, Au and Pt, and the material of the column line N is metalThe material is N-type semiconductor material, such as N-Poly, N-Si, N-IZO (N-type indium zinc oxide), etc. Between the material intersections of the row lines M and column lines N is a thin dielectric such as SiO that can be used for the antifuses mentioned in this patent₂Or other materials.

Specifically, for a specific intersection of a row line and a column line, the structure is "row line material-insulating medium-column line material", and the materials of the row line and the column line are respectively two materials required for generating schottky contact at the intersection ", that is, in the case of dielectric breakdown, the materials of the row line and the column line should form schottky contact. Fig. 22 shows the structure thereof. 2201 is a metal that can be used to form schottky contact, such as Al, Ag, Au, Pt, 2202 is a thin dielectric layer, 2203 is N-type semiconductor material, such as N-Poly, N-Si, N-IZO (N-type indium zinc oxide), and the like.

The above examples have been provided for illustrative purposes only and do not set any limit on the multilayer one-time programmable (OTP) nonvolatile memory cell 100 and its method of fabrication as shown in fig. 2 and disclosed herein. While the multi-level OTP persistent memory cell 100 and method have been described in terms of various embodiments, the descriptive and descriptive statements employed for these embodiments should not be construed as limiting statements. Furthermore, although specific means, materials and embodiments have been described for the multi-layer OTP nonvolatile memory cell 100 and method of making the same, the multi-layer OTP nonvolatile memory cell 100 and method of making the same are not limited to the disclosure herein, but extend to all functionally equivalent structures, methods and applications, as set forth in the appended claims. Many modifications and variations may be made by a skilled and skilled artisan without departing from the scope and spirit of the multi-level OTP permanent memory cell 100 and the method of making the same disclosed herein.

Claims

A multi-level one-time programmable persistent memory cell comprising:

at least two layers of one-time programmable permanent memory modules, one layer stacked on top of the other; each layer of the at least two layers of otp-nonvolatile memory modules includes M rows and N columns made of an inversely doped semiconductor material, where M and N are positive integers greater than 1;

a thin insulating dielectric material is disposed at the intersection of the M rows and N columns of each layer of the at least two layers of one-time programmable permanent memory modules, between the M rows and N columns; the thin insulating dielectric material is on one of a top surface and a bottom surface of each of the M rows and N columns.
The multi-layer otp-persistent memory cell of claim 1, wherein each layer of the otp-memory modules is stacked in a bottom-up direction, connected at the intersection of M rows and N columns, and wherein the M rows in each layer of the otp-memory modules are disposed on one of the top and bottom of the N columns.
The multi-layer otp-nonvolatile memory cell of claim 1, further comprising a plurality of otp-nonvolatile memory cells formed at the intersection of M rows and N columns of the otp-nonvolatile memory module in each layer and a plurality of otp-nonvolatile memory cells formed at the intersection between the otp-nonvolatile memory modules.
The multi-layer one-time programmable permanent memory cell of claim 3 wherein the one-time programmable memory cell comprises a p-type semiconductor region, an n-type semiconductor region, and a thin insulating dielectric region between the p-type semiconductor region and the n-type semiconductor region.
The multi-layer one-time programmable permanent memory cell of claim 4 wherein each one-time programmable memory cell further comprises at least two connection terminals located in the p-type semiconductor region and the n-type semiconductor region.
The multilevel one time programmable permanent memory cell of claim 5 wherein the at least two connection terminals in each of the one time programmable memory cells are connected to each other using conductive vias.
The multi-layer one-time programmable persistent memory cell of claim 4 wherein a thickness of the thin insulating dielectric material forming the thin insulating dielectric region in the one-time programmable memory cell is a predetermined value corresponding to a breakdown voltage of each of the one-time programmable memory cells.
The multi-level one time programmable persistent memory unit of claim 1, further comprising multi-level decoder circuits for the M rows and N columns of the one time programmable persistent memory module, the multi-level decoder circuits being shared by at least two layers of the one time programmable persistent memory module stacked one on top of the other.
The multi-layer otp persistent memory cell of claim 1, wherein the M rows of each layer of the otp persistent memory module are comprised of one of a p-type semiconductor material and an N-type semiconductor material, and the N columns are comprised of an inverse of the one of the p-type semiconductor material and the N-type semiconductor material.
A multi-level one-time programmable persistent memory cell comprising:

at least two layers of otp-nonvolatile memory modules stacked one on top of the other, each layer of the at least two layers of otp-nonvolatile memory modules comprising M rows and N columns of useful conductors, wherein M and N are positive integers greater than 1;

a plurality of one-time programmable persistent memory cells formed at the intersections of M rows and N columns of the one-time programmable persistent memory modules at each layer, and a plurality of one-time programmable persistent memory cells formed at the intersections between the one-time programmable persistent memory modules.
A multi-level one-time programmable persistent memory cell comprising:

at least two layers of one-time programmable permanent memory modules, one layer stacked on top of the other; each of the at least two layers of otp-nonvolatile memory blocks includes M row lines and N column lines, where M and N are positive integers greater than 1;

at each intersection point, the materials of the row line M and the column line N are respectively two materials which are required for generating Schottky contact at the intersection point;

a thin insulating dielectric material is disposed at the intersection of the M rows and N columns of each of the at least two layers of one time programmable permanent memory modules.
A method of making a multi-layer one-time programmable permanent memory cell, the method comprising:

disposing a semiconductor material on a top planar surface of a wafer containing completed memory peripheral circuitry using one of a deposition process and an epitaxial process;

counter-doping the semiconductor material with a dopant that is one of a p-type dopant and an n-type dopant using one of an ion implantation process and a diffusion process;

removing the redundant part of the doped semiconductor material by using a photoetching mask process and an etching process, manufacturing the anti-doped semiconductor material into a strip-shaped semiconductor material strip, and forming one of M rows and N columns which are formed by anti-phase doped semiconductor material in the one-time programmable permanent memory module, wherein M and N are positive integers which are more than one;

filling strips of semiconductor material comprising one of M rows and N columns of the one time programmable permanent memory module with an insulating dielectric material using a planarization process;

removing the insulating dielectric material overfilled in strips of semiconductor material comprising one of the M rows and N columns of the one time programmable non-volatile memory module using a chemical-mechanical polishing process;

creating a thin insulating dielectric film over the filled strips of semiconductor material that make up one of the M rows and N columns of the OTP memory module using a thermal oxidation process, or a low temperature chemical vapor deposition process, or an atomic layer deposition process;

repeating the method in a direction from bottom to top to a predetermined number of times, symmetrically stacking the one-time programmable persistent memory modules produced by each repetition to produce the multi-level one-time programmable persistent memory cells.
The method of claim 12 further characterized by forming a number of one time programmable memory cells at the M row and N column intersections of the one time programmable persistent memory modules and at the intersections between the one time programmable persistent memory modules.
The method of claim 12, further comprising iteratively adding another layer of said thin insulating dielectric film on top of the topmost one of said otp-memory modules, stacking one of said M rows and N columns of counter-doped semiconductor material on said added another layer of thin insulating dielectric to add otp-memory cells in said multi-layer otp-memory cells; the counter-doped semiconductor material is one of a p-type semiconductor material and an n-type semiconductor material.
A method of making a multi-layer one-time programmable permanent memory cell, the method comprising:

depositing a thick insulating dielectric material on a top planar surface of a wafer containing completed memory peripheral circuitry;

building a trench on the deposited thick dielectric layer using a mask etch process for locating one of a row and a column of an otp permanent memory module;

depositing a semiconductor material on the trench;

counter-doping the doped semiconductor material with a dopant, which is one of a p-type dopant and an n-type dopant, using a diffusion process or an ion implantation process;

removing the excessively deposited anti-doping semiconductor material by adopting a conventional planarization process to form one of M rows and N columns of the one-time programmable permanent memory module, wherein M and N are positive integers larger than 1;

depositing a layer of insulating dielectric material on the top planar surface of the wafer;

forming a trench in the deposited thick dielectric layer using a mask etch process for locating one of a row and a column of the otp permanent memory module; the etching process will be until the last deposited semiconductor material is reached;

depositing a thin insulating dielectric film on one of the M rows and the N columns of the one-time programmable permanent memory module by using a thermal oxidation process, or a thermal deposition process, or an atomic layer deposition process, wherein the thin insulating dielectric film on one of the M rows and the N columns of the one-time programmable permanent memory module is used as a programmable dielectric material;

repeating the method in a direction from bottom to top to a predetermined number of times, symmetrically stacking the one-time programmable persistent memory modules produced by each repetition to produce the multi-level one-time programmable persistent memory cells.
The method of claim 15, further comprising forming a number of one-time programmable memory cells at an intersection of M rows and N columns of the one-time programmable persistent memory module and at an intersection between the one-time programmable persistent memory modules.
The method of claim 16, further comprising iteratively adding another layer of the thin insulating dielectric film over a topmost one of the otp-memory modules, stacking one of the M rows and N columns of counter-doped semiconductor material over the added another layer of the thin insulating dielectric film to add otp-memory cells in the multi-layer otp-memory cell; the counter-doped semiconductor material is one of a p-type semiconductor material and an n-type semiconductor material.