CN110517964B - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN110517964B
CN110517964B CN201910715828.8A CN201910715828A CN110517964B CN 110517964 B CN110517964 B CN 110517964B CN 201910715828 A CN201910715828 A CN 201910715828A CN 110517964 B CN110517964 B CN 110517964B
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China
Prior art keywords
semiconductor
semiconductor wafer
resin layer
electrode
insulating resin
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CN201910715828.8A
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CN110517964A (en
Inventor
松原宽明
近井智哉
石堂仁则
中村卓
本多广一
出町浩
熊谷欣一
作元祥太朗
渡边真司
细山田澄和
中村慎吾
宫腰武
岩崎俊宽
玉川道昭
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Rely On Technology Japan Co
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Rely On Technology Japan Co
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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Abstract

The semiconductor device and the manufacturing method thereof of the invention comprises: preparing a semiconductor wafer on which electrodes are formed, and electrically connecting a first semiconductor element formed on a semiconductor chip with the electrodes of the semiconductor wafer via bumps; before or after connecting the semiconductor wafer and the semiconductor chip, forming a first insulating resin layer in a gap between the semiconductor wafer and the semiconductor chip facing each other; forming a second insulating resin layer on the semiconductor wafer in such a manner as to reach a thickness of the buried semiconductor chip; grinding the second insulating resin layer and the semiconductor chip until the semiconductor chip reaches a prescribed thickness; forming a first insulating layer on the second insulating resin layer and on the semiconductor chip, and forming openings exposing the electrodes in the first insulating layer and the second insulating resin layer; burying the opening portion with a conductive material; forming a wiring connected to the conductive material of the buried opening portion on the first insulating layer; forming a first terminal electrically connected to the wiring; and grinding the semiconductor wafer to a prescribed thickness.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The present invention relates to a semiconductor device and a method for manufacturing the same. And more particularly, to a semiconductor device including a semiconductor module of a thin semiconductor stacked structure and a method of manufacturing the same.
Background
Conventionally, in order to achieve miniaturization of electronic devices, semiconductor modules including a plurality of semiconductor chips have been manufactured. For the connection of semiconductor chips built in such a semiconductor module, bump connection using convex electrodes (bumps) formed on the surface of the semiconductor chip is adopted in addition to conventional wire bonding for the purpose of increasing the bandwidth and reducing the power consumption (for example, patent document 1).
In recent years, in order to achieve thinning of a semiconductor device or formation of a via hole of a through-silicon via (TSV, throughSiliconVia), thinning of a semiconductor chip is required, and various processing methods of a thin semiconductor wafer have been proposed (for example, patent document 2, patent document 3). However, in the case of manufacturing a semiconductor module for bump-connecting thin semiconductor chips, there is a concern that chip cracking due to use of a back grinding (BSG) tape, dicing, pick up (pick up), and bump connection failure due to warpage of the thin chips at the time of bump connection may occur. In addition, if a wafer support is used for processing a thin wafer, there is a problem in that the cost increases accordingly.
(Prior art literature)
(Patent literature)
Patent document 1: japanese patent No. 4809957
Patent document 2: japanese patent application laid-open No. 2010-267653
Patent document 3: japanese patent application laid-open No. 2012-084780
Disclosure of Invention
The invention provides a method for manufacturing a semiconductor device, which can inhibit chip cracking and poor bump connection and can improve the yield and reliability. Further, the present invention is directed to a method for manufacturing a semiconductor device, which can reduce manufacturing costs by manufacturing a semiconductor device at a wafer level without using a wafer support.
A method for manufacturing a semiconductor device according to an embodiment of the present invention includes the steps of: preparing a semiconductor wafer on which electrodes are formed, and electrically connecting a first semiconductor element formed on a semiconductor chip to the electrodes of the semiconductor wafer via bumps; forming a first insulating resin layer in a gap between the semiconductor wafer and the semiconductor chip facing each other before or after connecting the semiconductor wafer and the semiconductor chip; forming a second insulating resin layer on the semiconductor wafer until reaching a thickness at which the semiconductor chip is buried; polishing the second insulating resin layer and the semiconductor chip until the semiconductor chip reaches a predetermined thickness; forming a first insulating layer on the second insulating resin layer and on the semiconductor chip, and forming an opening for exposing the electrode on the first insulating layer and the second insulating resin layer; burying the opening with a conductive material; forming a wiring connected to a conductive material burying the opening portion on the first insulating layer; forming a first terminal electrically connected to the wiring; and grinding the semiconductor wafer to a prescribed thickness, wherein grinding the semiconductor wafer to the prescribed thickness means grinding the semiconductor wafer until the finished thickness is reached.
According to an embodiment of the present invention, the semiconductor wafer may have a plurality of element regions in which the second semiconductor elements are formed.
According to an embodiment of the present invention, one element region of the plurality of element regions may be connected to the plurality of semiconductor chips.
According to one embodiment of the invention, the invention may further comprise the steps of: forming a buried electrode having an end electrically connected to the second semiconductor element on the semiconductor wafer; polishing the semiconductor wafer after forming the first terminal until the other end of the buried electrode is in the vicinity of the first terminal; exposing the other end of the buried electrode; and forming a second terminal electrically connected to the other end portion of the exposed buried electrode.
According to one embodiment of the invention, the invention may further comprise the steps of: forming a groove having a width wider than a dicing width and a depth equal to or greater than the finished thickness on the semiconductor wafer along a boundary line of the element region before connecting the electrode and the first semiconductor element bump; and singulating the semiconductor wafer after polishing the semiconductor wafer to a finished thickness, wherein the singulation may be to singulate the semiconductor wafer along the grooves formed in the semiconductor wafer with a scribe width narrower than the grooves.
A method for manufacturing a semiconductor device according to an embodiment of the present invention includes the steps of: preparing a semiconductor wafer having an electrode formed thereon, and preparing a first semiconductor chip having a first semiconductor element formed thereon and having a buried electrode electrically connected to the first semiconductor element; electrically connecting the first semiconductor element of the first semiconductor chip to the electrode of the semiconductor wafer via a first bump; forming a first insulating resin layer in a gap between the semiconductor wafer and the first semiconductor chip facing each other before or after connecting the semiconductor wafer and the first semiconductor chip; forming a second insulating resin layer on the semiconductor wafer until reaching a thickness at which the first semiconductor chip is buried; polishing the second insulating resin layer and the first semiconductor chip until the other end of the first buried electrode is in the vicinity of the first buried electrode; exposing the other end portion of the first buried electrode; forming a first insulating layer on the first semiconductor chip to cover the other end portion of the first buried electrode; forming a terminal connected to the other end portion of the first buried electrode through a contact hole on the first insulating layer; electrically connecting the terminal to a second semiconductor element formed on a second semiconductor chip via a second bump; forming a third insulating resin layer in a gap between the terminal and the first insulating layer, which are opposed to each other, and the second semiconductor chip before or after connecting the terminal and the second semiconductor chip; forming a fourth insulating resin layer on the first insulating layer until reaching a thickness at which the second semiconductor chip is buried; polishing the fourth insulating resin layer and the second semiconductor chip until the second semiconductor chip reaches a predetermined thickness; forming a second insulating layer on the fourth insulating resin layer and on the second semiconductor chip; forming openings in the second insulating layer, the fourth insulating resin layer, the first insulating layer, and the second insulating resin layer to expose electrodes formed on the semiconductor wafer and electrically connected to the first semiconductor element; burying the opening with a conductive material; forming a wiring connected to a conductive material burying the opening portion on the second insulating layer; forming a first terminal electrically connected to the wiring; and grinding the semiconductor wafer to a prescribed thickness, wherein grinding the semiconductor wafer to a prescribed thickness means grinding the semiconductor wafer until a finished thickness is reached.
According to an embodiment of the present invention, the semiconductor wafer may have a plurality of element regions in which the third semiconductor element is formed.
According to an embodiment of the present invention, one element region of the plurality of element regions may be connected to the plurality of first semiconductor chips.
The method for manufacturing a semiconductor device according to an embodiment of the present invention may further include the steps of: the electrode is electrically connected to at least one fourth semiconductor element formed on the third semiconductor chip via the first bump.
According to one embodiment of the present invention, the method may further comprise the steps of: forming a second buried electrode having one end electrically connected to the third semiconductor element on the semiconductor wafer; polishing the semiconductor wafer after forming the first terminal until the other end of the second buried electrode is in the vicinity of the first buried electrode; exposing the other end of the second buried electrode; and forming a second terminal electrically connected to the other end portion of the exposed second buried electrode.
According to one embodiment of the present invention, the method may further comprise the steps of: forming a groove having a width wider than a dicing width and a depth equal to or greater than the finished thickness on the semiconductor wafer along a boundary line of the element region before connecting the electrode and one end bump of the first buried electrode; and singulating the semiconductor wafer after polishing the semiconductor wafer to the finished thickness, wherein the singulation may be to singulate the semiconductor wafer along the grooves formed in the semiconductor wafer with a scribe width narrower than the grooves.
According to the present invention, a method for manufacturing a semiconductor device capable of manufacturing a semiconductor device with improved yield and reliability by suppressing chip cracking and bump connection failure can be provided. In addition, a method for manufacturing a semiconductor device can be provided which can reduce manufacturing cost.
Drawings
Fig. 1A is a diagram for explaining a method of manufacturing a semiconductor device according to a first embodiment of the present invention.
Fig. 1B is a diagram for explaining a method of manufacturing a semiconductor device according to a first embodiment of the present invention.
Fig. 2A is a diagram for explaining a method of manufacturing a semiconductor device according to the first embodiment of the present invention.
Fig. 2B is a diagram for explaining a method of manufacturing the semiconductor device according to the first embodiment of the present invention.
Fig. 3 is a diagram for explaining a method of manufacturing a semiconductor device according to a first embodiment of the present invention.
Fig. 4 is a diagram for explaining a method of manufacturing a semiconductor device according to the first embodiment of the present invention.
Fig. 5 is a diagram for explaining a method of manufacturing a semiconductor device according to the first embodiment of the present invention.
Fig. 6 is a diagram for explaining a method of manufacturing a semiconductor device according to the first embodiment of the present invention.
Fig. 7 is a diagram for explaining a method of manufacturing a semiconductor device according to the first embodiment of the present invention.
Fig. 8 is a diagram for explaining a method of manufacturing a semiconductor device according to the first embodiment of the present invention.
Fig. 9A is a diagram for explaining a method of manufacturing a semiconductor device according to a second embodiment of the present invention.
Fig. 9B is a diagram for explaining a method of manufacturing a semiconductor device according to the second embodiment of the present invention.
Fig. 10 is a diagram for explaining a method of manufacturing a semiconductor device according to a second embodiment of the present invention.
Fig. 11 is a diagram for explaining a method of manufacturing a semiconductor device according to a second embodiment of the present invention.
Fig. 12 is a diagram for explaining a method of manufacturing a semiconductor device according to a second embodiment of the present invention.
Fig. 13 is a diagram for explaining a method of manufacturing a semiconductor device according to a second embodiment of the present invention.
Fig. 14 is a diagram for explaining a method of manufacturing a semiconductor device according to a second embodiment of the present invention.
Fig. 15 is a diagram for explaining a method for manufacturing a semiconductor device according to a third embodiment of the present invention.
Fig. 16 is a diagram for explaining a method for manufacturing a semiconductor device according to a third embodiment of the present invention.
Fig. 17 is a diagram for explaining a method for manufacturing a semiconductor device according to a third embodiment of the present invention.
Fig. 18 is a diagram for explaining a method for manufacturing a semiconductor device according to a third embodiment of the present invention.
Fig. 19 is a diagram for explaining a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.
Fig. 20 is a diagram for explaining a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.
Fig. 21 is a diagram for explaining a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.
Fig. 22 is a diagram for explaining a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.
Fig. 23 is a diagram for explaining a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.
Fig. 24 is a diagram for explaining a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.
Fig. 25 is a diagram for explaining a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.
Fig. 26 is a diagram for explaining a method of manufacturing a semiconductor device according to a modification of the fourth embodiment of the present invention.
Fig. 27 is a diagram for explaining a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.
Fig. 28 is a diagram for explaining a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.
Fig. 29 is a diagram for explaining a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.
Fig. 30 is a diagram for explaining a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.
Fig. 31 is a diagram for explaining a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.
Fig. 32 is a diagram for explaining a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.
Fig. 33 is a diagram for explaining a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.
(Description of the reference numerals)
10: A semiconductor device; 101: a semiconductor wafer; 103: a first semiconductor element; 105: a semiconductor chip; 106: a second semiconductor element; 107: an electrode; 109: a bump; 111: a first insulating resin layer; 113: a second insulating resin layer; 114: a first insulating layer; 115: an opening portion; 117: wiring; 119: wiring; 121: a terminal; 123: an external terminal.
Detailed Description
Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described with reference to the accompanying drawings. However, the method for manufacturing a semiconductor device according to the present invention can be implemented in various different modes, and is not limited to the description of the embodiments described below. In the drawings referred to in this embodiment, the same reference numerals are given to the same parts or parts having the same functions, and the repetitive description thereof will be omitted. In the following description, when an element such as a layer, a film, or a region is located "on" another element, this is not limited to the case of "directly above" the other element, but includes the case where other elements are located in the middle thereof.
< First embodiment >
An outline of a method for manufacturing a semiconductor device according to a first embodiment of the present invention will be described with reference to fig. 1A to 8.
First, as shown in fig. 1A and 1B, a semiconductor wafer 101 in which a plurality of element regions are formed is prepared. The element region is a region that is formed by dicing a semiconductor wafer and then singulating the semiconductor wafer, and then functions as one semiconductor chip. Fig. 1A is a top view of a semiconductor wafer 101, and fig. 1B is a cross-sectional view taken along line B-B of region a of fig. 1A. A semiconductor element (hereinafter, referred to as a first semiconductor element) 103 may be formed in each element region of the semiconductor wafer 101. Here, the first semiconductor element 103 may further include a transistor or the like. Further, on the semiconductor wafer 101, an electrode 104 formed of a metal material such as Al is formed for each element region so as to be electrically connected to the first semiconductor element 103 via an insulating film. In addition, a wiring layer for connecting the first semiconductor element 103 and the electrode 104 may be formed on the semiconductor wafer 101. Fig. 1A is a partial cross-sectional view of a semiconductor wafer. Fig. 1A and 1B show two element regions formed on a semiconductor wafer 101. In addition, the semiconductor wafer 101 may be an interposer (interposer) substrate on which the wiring layer is formed without forming the first semiconductor element 103.
Next, a semiconductor chip 105 having a semiconductor element (hereinafter referred to as a second semiconductor element) 106 formed on a semiconductor substrate is prepared. Here, the second semiconductor element 106 includes a transistor or the like. The assembly of the semiconductor device is performed at a wafer level, and thus, a number of semiconductor chips 105 corresponding to the element region formed on the semiconductor wafer 101 are prepared. An electrode 107 electrically connected to the second semiconductor element 106 via a wiring is formed on the semiconductor chip 105 via an insulating film.
As shown in fig. 2A and 2B, the first semiconductor element 103 formed in each element region of the semiconductor wafer 101 and the second semiconductor element 106 formed in the semiconductor chip 105 are opposed to each other and bonded via the bump 109, and the first semiconductor element 103 and the second semiconductor element 106 are electrically connected. Fig. 2A is a plan view showing a state where semiconductor chips 105 are bump bonded on semiconductor wafer 101, and fig. 2B is a cross-sectional view taken along line B-B of region a of fig. 2A. Specifically, bumps 109 are formed on the electrodes 104 electrically connected to the first semiconductor element 103 and opposed to the semiconductor chip 105 and/or on the electrodes 107 electrically connected to the second semiconductor element 106 so as to be opposed to each other and bonded by heat treatment. The bump 109 may be formed by a semi-additive process (semi-additiveprocess) or the like using, for example, gold, solder, or copper pillars. Fig. 2A and 2B show a state in which the bump 109 is formed only on the electrode 104 and/or the electrode 107 for connecting the first semiconductor element 103 and the second semiconductor element 106, but the present invention is not limited to this, and the bump 109 may be formed on the electrode 104 that does not face the semiconductor chip 105. In the case where the semiconductor wafer 101 is an interposer, electrodes electrically connected to wirings formed on the interposer and electrodes 107 electrically connected to the second semiconductor element 106 may be bump-connected to each other.
As shown in fig. 2B, after the semiconductor wafer 101 and the semiconductor chip 105 are bonded via the bump 109, an underfill (hereinafter, referred to as a first insulating resin layer) 111 is filled in the gap between the semiconductor wafer 101 and the semiconductor chip 105. The first insulating resin layer 111 is not particularly limited as long as it is an insulating resin for an underfill, and for example, a filler in which silica or alumina is added to an epoxy resin, or a filler in which an amine-based curing agent or the like is added may be used. In addition, the first insulating resin layer 111 may be formed before the semiconductor wafer 101 and the semiconductor chip 105 are bump bonded.
An example of a method of performing underfill encapsulation (CUF, capillaryunderfill; capillary underfill) by filling an underfill in a gap between the semiconductor wafer 101 and the semiconductor chip 105 after bonding the semiconductor wafer 101 and the semiconductor chip 105 via the bump 109 is described below.
After the semiconductor wafer 101 and the semiconductor chips 105 are bump bonded, if necessary, in order to improve the fluidity of the underfill, the semiconductor wafer 101 and the semiconductor chips 105 are subjected to plasma treatment, and then a liquid underfill material is applied in a line shape on the semiconductor wafer 101, for example, at a position of about several hundreds μm from one side of one end of each semiconductor chip 105, using a dispenser (dispenser) or the like. When dispensing (dispense), the chip and underfill material are heated to reduce the viscosity of the solution and applied multiple times at specified intervals. The applied underfill material enters the gap between the semiconductor wafer 101 and the semiconductor chips 105 by capillary action.
An example of a method of sealing the semiconductor wafer 101 with a liquid underfill material (NCP, non-conductivepaste; a nonconductive adhesive) before bonding the semiconductor wafer 101 to the semiconductor chip 105 via the bump 109 will be described below.
Before the semiconductor wafer 101 and the semiconductor chip 105 are bump bonded, for example, a dispenser or the like may be mounted on a bump-bonding apparatus (flip-chip bonder), and an underfill material may be applied to the semiconductor wafer 101 corresponding to a part or the whole of the region for mounting the semiconductor chip 105 in a coating trace where voids (void) are not likely to occur, and the underfill material may be spread over the entire surface of the gap between the semiconductor wafer 101 and the semiconductor chip 105 while the semiconductor chip 105 is mounted on the semiconductor wafer 101, i.e., the semiconductor wafer 101 is to be bump-bonded to the semiconductor chip 105.
For example, the underfill material may be attached to the semiconductor wafer 101, the wafer before dicing the semiconductor chips 105, or both wafer units by spin coating of an underfill liquid, lamination of a film-shaped underfill material, or the like, and the semiconductor wafer 101 with the underfill material attached thereto and the singulated semiconductor chips 105 may be bump-connected to each other by the underfill material, and the gap between the semiconductor wafer 101 and the semiconductor chips 105 may be sealed with the underfill material.
According to the above-described method or the like, after the underfill is filled in the gap between the semiconductor wafer 101 and the semiconductor chip 105, the underfill is cured by heating in an oven or the like, whereby the first insulating resin layer 111 is formed.
Next, as shown in fig. 2B, an insulating resin layer (hereinafter, referred to as a second insulating resin layer) 113 for burying the thickness of the semiconductor chip 105 is formed on the semiconductor wafer 101. The resin used for the second insulating resin layer 113 is not particularly limited, but is required to have corrosion resistance and solder heat resistance based on the rewiring process, and in order to suppress warpage of the wafer, a resin having a low thermal expansion coefficient is preferable. For example, a film mold material formed of an epoxy hybrid material for compression molding or a silicone hybrid material for vacuum lamination for burying a fan-out (fan-out) packaged chip, or the like may be used. In fig. 2A, the second insulating resin layer 113 is not described.
Next, as shown in fig. 3, after the second insulating resin layer 113 is cured, the back surface of each semiconductor chip 105 on which the second semiconductor element 106 is not formed is polished by back surface polishing until the thickness required for each second insulating resin layer 113 (the finished thickness, that is, the thickness of the final semiconductor chip after the thinning process is completed) is reached. When polishing the semiconductor chips 105 and the second insulating resin layer 113, a back surface polishing (BSG, backSideGrinding) tape (surface protective tape) is attached to the back surface of the semiconductor wafer 101 on which the first semiconductor element 103 is not formed, and the semiconductor chips 105 are thinned by the back surface polishing step. After thinning each semiconductor chip 105, the back surface grinding tape is peeled from the back surface of the semiconductor wafer 101.
Next, before forming the wiring on the back surface of the semiconductor chip 105, the first insulating layer 114 is formed. The first insulating layer 114 may be formed by applying a resin coating material for mounting a wiring board, such as an epoxy resin, to the polished surfaces of the semiconductor chip 105 and the second insulating resin layer 113, or may be formed by using a film-type interlayer insulating material, a resin-attached copper foil for assisting a wiring forming process described below, or the like from the viewpoint of handling. As shown in fig. 4, an opening 115 is formed in the second insulating resin layer 113 and the first insulating layer 114 by a CO 2 laser, a UV-YAG laser, or the like, and the opening 115 is used to expose the electrode 104 formed on the semiconductor wafer 101 so as not to face the semiconductor chip 105. The opening 115 is preferably formed by laser light from the viewpoint of cost, but may be formed by photolithography. The intensity of the laser beam used to form the opening 115 is set to a condition that the electrode 104 on the semiconductor wafer 101 is not processed. In the case where the electrode 104 is damaged, as described above, the bump 109 such as a copper pillar is formed as a bump on the electrode 104 which is not opposed to the semiconductor chip 105, and the bump 109 is used to protect the electrode 104 from the laser beam, whereby the electrode 104 can be prevented from being damaged. In the case of using the CO 2 laser, resin stains are generated, and thus the decontamination treatment is continued after the opening 115 is formed. As the decontamination treatment, a treatment with a decontamination solution of alkali permanganate may be performed in the case of protecting the electrode 104 with a copper column or the like, and a treatment such as plasma decontamination may be performed in the case of exposing the electrode 104.
Next, as shown in fig. 5, a conductive layer is formed over the entire upper surface of the semiconductor wafer 101, that is, over the first insulating layer 114, over the electrode 104 exposed through the opening 115, and the side surface of the opening 115, and the conductive layer is patterned, whereby a wiring 117 burying the opening 115 and a wiring 119 connected to the wiring 117 are formed. The wirings 117 and 119 can be formed by a half-addition method or the like, for example. In the case of forming the wirings 117 and 119 by the semi-additive method, electroless copper plating is performed on the entire upper surface of the semiconductor wafer 101, then a pattern is formed with a plating resist, the wiring is formed by electrolytic copper plating based on the pattern, then the plating resist is removed, and the electroless copper plating exposed portion is removed by etching. Through these steps, the wiring 117 burying the opening 115 and the wiring 119 connected to the wiring 117 can be formed. The insulating layer forming step and the wiring step may be repeatedly performed, whereby two or more wiring layers may be formed.
After forming the wirings 117 and 119, as shown in fig. 6, an insulating film 120 is formed over the wiring 119, and a terminal 121 connected to the wiring 119 is formed over the insulating film 120. The insulating film 120 can be formed using a thermosetting epoxy insulating film for mounting a wiring board or a resin-attached copper foil, similarly to the first insulating layer 114. After the solder resist 122 is applied to the terminals 121, openings are made to expose the terminals 121. An oxidation-resistant treatment such as an organic solderability preservative (OSP, organicSolderabilityPreservative) treatment may be performed on the surface of the exposed terminal 121. The external terminals 123 may be formed on the terminal 121 at a wafer level for each element region as needed. The external terminals 123 may be formed as a ball grid array (BGA, ballGridArray) by mounting solder balls using a solder ball mounting machine.
Next, as shown in fig. 7, the back surface of the semiconductor wafer 101 on which the first semiconductor element 103 is not formed is polished by back surface polishing until a desired thickness (a finished thickness, that is, a thickness of a final semiconductor wafer after the end of the thinning process) is reached, thereby thinning the semiconductor wafer 101. When polishing the semiconductor wafer 101, a back surface polishing tape is attached to the side where the terminals 121 or the external terminals 123 are formed, and after the thinning of the semiconductor wafer 101 is completed, the back surface polishing tape is peeled off.
Then, as shown in fig. 8, the semiconductor wafer 101 is diced along with the solder resist 122, the insulating film 120, the first insulating layer 114, and the second insulating resin layer 113 along the boundary line formed in the element region of the semiconductor wafer 101, thereby manufacturing the semiconductor device 10. Before dicing the semiconductor wafer 101, an insulating film may be formed on the back surface of the semiconductor wafer 101 with an insulating resin or the like and cured, if necessary. When an insulating film is formed on the back surface of the semiconductor wafer 101, the insulating film is diced together with the semiconductor wafer to be singulated.
According to the method for manufacturing a semiconductor device of the first embodiment of the present invention, since the semiconductor wafer 101 and the semiconductor chip 105 are bump-connected before the semiconductor wafer 101 and the semiconductor chip 105 are thinned (in a state where the thicknesses of the semiconductor wafer and the semiconductor chip are thick), bump connection failure or short circuit due to bending of the chip at the time of bump connection can be suppressed, and yield and reliability of the semiconductor device can be improved. In addition, since the semiconductor chip 105 is polished after the reinforcement by the second insulating resin layer 113, chip cracking at the time of polishing the semiconductor chip 105 can be suppressed. Further, since the wiring 119 is formed before the semiconductor wafer 101 is thinned (in a state where the thickness of the semiconductor wafer 101 is thick), the wiring 119 can be stably formed without using a wafer support by utilizing the rigidity of the semiconductor wafer 101, and the manufacturing cost can be reduced.
< Second embodiment >
An outline of a method for manufacturing a semiconductor device according to a second embodiment of the present invention will be described with reference to fig. 9A to 14. In the method of manufacturing a semiconductor device according to the second embodiment, unlike the method of manufacturing a semiconductor device according to the first embodiment, a step of forming a groove wider than a dicing width on the back surface of a semiconductor wafer where no first semiconductor element is formed is included along the boundary line of each of a plurality of element regions formed in the semiconductor wafer before the first semiconductor element formed in each element region of the semiconductor wafer and the second semiconductor element formed in the semiconductor chip are opposed to each other and bonded via a bump. In the method for manufacturing a semiconductor device according to the second embodiment described below, the description repeated with the method for manufacturing a semiconductor device according to the first embodiment is omitted or simplified.
Fig. 9A is a top view of semiconductor wafer 101, and fig. 9B is a cross-sectional view taken along line B-B of region a of fig. 9A. First, as in the first embodiment, a semiconductor wafer 101 having a plurality of element regions formed therein is prepared. Then, as shown in fig. 9A and 9B, a groove 201 having a width wider than the dicing width is formed on the side of the first semiconductor element 103 on which the semiconductor wafer 101 is formed along the boundary line of the element region. The groove 201 may be formed by half dicing (halfdicing) with the aid of a blade, laser, or the like. The depth of the groove 201 is formed deeper than the finished thickness of the semiconductor wafer 101. In addition, the semiconductor wafer 101 may be an interposer (interposer) in which the first semiconductor element 103 is omitted and a wiring layer is formed.
The method of manufacturing a semiconductor device according to the second embodiment of the present invention is substantially the same as the method of manufacturing a semiconductor device according to the first embodiment except that a groove 201 is formed in the semiconductor wafer 101 along the boundary line of the element region. That is, as shown in fig. 10, the semiconductor wafer 101 and the semiconductor chip 105 are bump bonded at a wafer level, the first insulating resin layer 111 is filled in the gap between the semiconductor wafer 101 and the semiconductor chip 105, and the second insulating resin layer 113 is formed on the semiconductor wafer 101 to bury the thickness of the semiconductor chip 105. The second insulating resin layer 113 is also filled in the groove 201 formed on the semiconductor wafer 101.
Thereafter, as shown in fig. 11, the back surface of each semiconductor chip 105 is polished by back surface polishing to thin the semiconductor chip 105 until each second insulating resin layer 113 reaches a finished thickness. Next, a first insulating layer 114 is formed on the polished surfaces of the semiconductor chips 105 and the second insulating resin layer 113.
Thereafter, as shown in fig. 12, an opening 115 is formed in the second insulating resin layer 113 and the first insulating layer 114 by a CO 2 laser, a UV-YAG laser, or the like, and the opening 115 is used to expose the electrode 104 formed on the semiconductor wafer 101. A conductive layer is formed over the entire upper surface of the semiconductor wafer 101, that is, over the first insulating layer 114, over the electrode 104 exposed through the opening 115, and the side surface of the opening 115 by a half-addition method or the like, and patterning is performed, whereby a wiring 117 for burying the opening 115 and a wiring 119 connected to the wiring 117 are formed. After forming the wirings 117 and 119, an insulating film is formed over the wiring 119, and a terminal 121 connected to the wiring 119 is formed over the insulating film 120. After the solder resist 122 is applied to the terminals 121, openings are made to expose the terminals 121. An oxidation-resistant treatment such as an OSP treatment may be performed on the surface of the exposed terminal 121. On the terminals 121, external terminals 123 are formed at each element region at a wafer level as necessary.
Then, as shown in fig. 13, the back surface of the semiconductor wafer 101 where the first semiconductor element 103 is not formed is polished by back surface polishing until the thickness reaches the completion thickness, and then, as shown in fig. 14, the solder resist 122, the insulating film 120, the first insulating layer 114, and the second insulating resin layer 113 are diced along the boundary line formed in the element region of the semiconductor wafer 101 to singulate the semiconductor wafer 101, thereby manufacturing the semiconductor device 20. The dicing width is narrower than the width of the groove 201 formed on the back surface of the semiconductor wafer 101.
In the method for manufacturing a semiconductor device according to the second embodiment of the present invention, since the deep trench 201 having a thickness equal to or greater than the finished thickness of the semiconductor wafer 101 is formed in advance in the semiconductor wafer 101, the second insulating resin layer 113 is exposed in the region where the trench 201 is formed on the back surface side of the semiconductor wafer 101 where the first semiconductor element 103 is not formed when the thinning of the semiconductor wafer 101 is completed, and the side surface of the semiconductor wafer 101 corresponding to each element region is covered with the second insulating resin layer 113. That is, at the end of the polishing process of the semiconductor wafer 101, the semiconductor wafer 101 is in a state of being separated for each element region. For this reason, dicing for singulating the semiconductor wafer 101 is performed with respect to the solder resist 122, the insulating film 120, the first insulating layer 114, and the second insulating resin layer 113.
According to the method for manufacturing a semiconductor device of the second embodiment of the present invention, similarly to the method for manufacturing a semiconductor device of the first embodiment, it is possible to suppress bump connection failure or short circuit caused by bending of the chip at the time of bump connection, improve yield and reliability of the semiconductor device, and reduce manufacturing cost. Further, according to the method for manufacturing a semiconductor device of the second embodiment of the present invention, the groove 201 having a width wider than the dicing width and a depth equal to or greater than the finished thickness can be formed in advance on the semiconductor wafer 101, whereby the semiconductor wafer 101 can be separated for each element region and the solder resist 122, the insulating film 120, the first insulating layer 114, and the second insulating resin layer 113 can be diced before the dicing step. This can suppress chip cracking of the semiconductor wafer 101 caused by dicing. Further, since the side surfaces of the semiconductor wafer 101 corresponding to the respective element regions are covered with the second insulating resin layer 113, not only the chip cracking of the semiconductor wafer 101 due to dicing but also peeling of the wiring layer or the like formed on the side surface side of the semiconductor wafer 101 can be suppressed, and the yield and reliability of the semiconductor device can be further improved.
As described above, the method for manufacturing a semiconductor device according to the second embodiment of the present invention is characterized in that, before bump bonding of the semiconductor wafer 101 and the semiconductor chip 105 is performed, the groove 201 having a width wider than the dicing width and a depth equal to or greater than the finished thickness of the semiconductor wafer 101 is formed in advance on the surface of the semiconductor wafer 101 where the first semiconductor element 103 is formed along the boundary line of the element region, but the depth of the groove 201 may be smaller than the finished thickness of the semiconductor wafer 101.
< Third embodiment >
An outline of a method for manufacturing a semiconductor device according to a third embodiment of the present invention will be described with reference to fig. 15 to 18. In the method of manufacturing a semiconductor device according to the third embodiment, unlike the method of manufacturing a semiconductor device according to the first and second embodiments, when a first semiconductor element formed in each element region of a semiconductor wafer and a second semiconductor element formed in a semiconductor chip are electrically connected to each element region of the semiconductor wafer via bumps, a plurality of semiconductor chips are bump-bonded to one element region of the semiconductor wafer. In the method for manufacturing a semiconductor device according to the third embodiment described below, the description repeated with the method for manufacturing a semiconductor device according to the first embodiment and the second embodiment is omitted or simplified.
First, as shown in fig. 15, a semiconductor wafer 101 having a plurality of element regions formed therein is prepared, and similarly to the method for manufacturing a semiconductor device according to the second embodiment of the present invention, a groove 201 is formed along the boundary line of the element regions on the surface of the semiconductor wafer 101 on the side where the first semiconductor element 103 is formed. The semiconductor wafer 101 may be an interposer in which the first semiconductor element 103 is omitted and a wiring layer is formed. In addition, the step of forming the groove 201 on the semiconductor wafer along the boundary line of the semiconductor wafer 101 may be omitted.
Next, as shown in fig. 16, the first semiconductor element 103 formed in each element region of the semiconductor wafer 101 and a second semiconductor element (not shown) formed in the semiconductor chips 105a and 105b are opposed to each other, and the electrode 104 and the electrode 107 are electrically connected via the bump 109, the electrode 104 is formed in the semiconductor wafer 101 and electrically connected to the first semiconductor element 103 and opposed to the semiconductor chips 105a and 105b, and the electrode 107 is formed in the semiconductor chips 105a and 105b and electrically connected to the second semiconductor element, respectively. In the case where the semiconductor wafer 101 is an interposer, electrodes formed on the interposer and electrically connected to wirings formed on the interposer may be bump-connected to the electrodes 107 formed on the semiconductor chips 105a and 105b, respectively. Thereafter, the first insulating resin layer 111 is filled in the gap between the semiconductor wafer 101 and the semiconductor chips 105a, 105b, and the second insulating resin layer 113 is formed on the semiconductor wafer 101 to bury the thicknesses of the semiconductor chips 105a, 105 b. The second insulating resin layer 113 is also filled in the groove 201 formed on the semiconductor wafer 101. In the method of manufacturing the semiconductor device according to the present embodiment, the first semiconductor element 103 formed in one of the plurality of element regions of the semiconductor wafer 101 is bump-connected to the second semiconductor element formed in each of the plurality of semiconductor chips 105a and 105 b.
Next, as shown in fig. 17, the back surface of each semiconductor chip 105 is polished by back surface polishing until each second insulating resin layer 113 reaches a finished thickness, thereby thinning the semiconductor chip 105. Thereafter, as in the method for manufacturing the semiconductor device according to the first or second embodiment, the first insulating layer 114 is formed on the polished surfaces of the semiconductor chips 150 and the second insulating resin layer 113. An opening 115 for exposing the electrode 104 formed on the semiconductor wafer 101 is formed in the first insulating layer 114 and the second insulating resin layer 113, and a conductive layer is formed and patterned by a half-addition method or the like on the entire upper surface of the semiconductor wafer 101, that is, on the first insulating layer 114, on the electrode 104 exposed through the opening 115, and on the side surface of the opening 115, whereby a wiring 117 for burying the opening 115 and a wiring 119 connected to the wiring 117 are formed. Thereafter, an insulating film 120 is formed over the wiring 119, and a terminal 121 connected to the wiring 119 is formed over the insulating film 120. After the solder resist 122 is applied to the terminals 121, openings are made to expose the terminals 121. After the external terminals 123 are formed as needed on the terminals 121, the back surface of the semiconductor wafer 101 on which the first semiconductor elements 103 are not formed is polished by back surface polishing until the thickness reaches the finished thickness. When the thinning of the semiconductor wafer 101 is completed, the second insulating resin layer 113 is exposed at the region where the groove 201 is formed on the back surface side of the semiconductor wafer 101 where the first semiconductor element 103 is not formed. Thereafter, as shown in fig. 18, the solder resist 122, the insulating film 120, the first insulating layer 114, and the second insulating resin layer 113 are diced along boundary lines formed in the element region of the semiconductor wafer 101, and the semiconductor wafer 101 is singulated, thereby manufacturing the semiconductor device 30.
As shown in fig. 18, in the semiconductor device 30, the first semiconductor element 103 formed in one element region of the semiconductor wafer 101 is connected to the second semiconductor element (not shown) formed in each of the two semiconductor chips 105a and 105b via a bump, but the present invention is not limited thereto, and the first semiconductor element 103 formed in one element region of the semiconductor wafer 101 may be connected to the second semiconductor elements formed in three or more semiconductor chips 105 via a bump.
According to the method for manufacturing a semiconductor device of the third embodiment of the present invention, even when a semiconductor device is manufactured in which a plurality of semiconductor chips 105 are placed on one element region of a semiconductor wafer 101 and bonded, it is possible to suppress bump connection failure or short circuit caused by bending of the chips at the time of bump connection, improve yield and reliability of the semiconductor device, and reduce manufacturing cost, similarly to the method for manufacturing a semiconductor device of the first and second embodiments of the present invention.
< Fourth embodiment >
An outline of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention will be described with reference to fig. 19 to 25. In the method of manufacturing the semiconductor device according to the fourth embodiment, unlike the method of manufacturing the semiconductor device according to the first and second embodiments, the first semiconductor element formed in each element region of the semiconductor wafer is bonded to the second semiconductor element formed in the semiconductor chip via another semiconductor chip in which a Through-silicon via (TSV-SiliconVia) is formed. In the method for manufacturing a semiconductor device according to the fourth embodiment described below, the description repeated with the method for manufacturing a semiconductor device according to the first embodiment and the second embodiment is omitted or simplified.
First, a semiconductor wafer 101 having a plurality of element regions formed therein is prepared, and a groove 201 is formed along the boundary line of the element regions on the side of the semiconductor wafer 101 where the first semiconductor element 103 is formed, as in the method for manufacturing a semiconductor device according to the second embodiment of the present invention. The semiconductor wafer 101 may be an interposer in which the first semiconductor element 103 is omitted and a wiring layer is formed. In addition, a step of forming a groove in the semiconductor wafer along the boundary line of the semiconductor wafer 101 may be omitted.
Next, a semiconductor substrate 403 (hereinafter, referred to as a first semiconductor chip 403) on which the buried electrode 401 is formed is prepared. The buried electrode 401 is connected to a second semiconductor element 402 formed inside the first semiconductor chip 403 and having one end formed on the first semiconductor chip 403 via a wiring layer. The buried electrode 401 is formed by forming a via (via) in the first semiconductor chip 403 by reactive ion etching or the like, forming an insulating film of SiO 2, siN or the like on the side wall by Chemical Vapor Deposition (CVD) or the like, and burying the via by plating or the like using a conductive material, for example, a metal such as copper. An external connection electrode 405 electrically connected to the second semiconductor element 402 and the buried electrode 401 is formed on the first semiconductor chip 403.
Next, as shown in fig. 19, the electrode 104 which is connected to the first semiconductor element 103 formed in each element region of the semiconductor wafer 101 and is opposed to the first semiconductor chip 403 and the buried electrode 401 formed in the first semiconductor chip 403 are electrically connected via the first bump 409. Specifically, the first bump 409 is formed on the electrode 104 and/or the electrode 405 formed on the semiconductor wafer 101 so as to be opposed to each other and bonded by heat treatment. In the case where the semiconductor wafer 101 is an interposer, an electrode formed on the interposer and electrically connected to a wiring formed on the interposer and an electrode 107 electrically connected to the second semiconductor element 106 may be bump-connected.
After the semiconductor wafer 101 and the first semiconductor chip 403 are bonded via the first bump 409, the first insulating resin layer 411 is filled in the gap between the semiconductor wafer 101 and the first semiconductor chip 403. The first insulating resin layer 411 may also be formed before the semiconductor wafer 101 and the first semiconductor chip 403 are bump bonded.
Next, a second insulating resin layer 413 for burying the thickness of the first semiconductor chip 403 is formed on the semiconductor wafer 101. As a material of the second insulating resin layer 413, the same material as that of the second insulating resin layer 113 described in the first embodiment of the present invention is used. After the second insulating resin layer 413 is cured, as shown in fig. 20, a BSG tape is attached to the back surface of the semiconductor wafer 101 on which the first semiconductor element 103 is not formed, and the first semiconductor chip 403 is thinned by polishing the first semiconductor chip 403 by back surface polishing for each second insulating resin layer 413 from the back surface side of the first semiconductor chip 403 on which the buried electrode 401 is not formed to the front side of the other end portion of the buried electrode 401.
After the BSG tape is peeled from the back surface of the semiconductor wafer 101, the first semiconductor chip 403 is polished by Chemical Mechanical Polishing (CMP) or the like to expose the other end portion of the buried electrode 401. Thus, the buried electrode 401 functions as a TSV penetrating the first semiconductor chip 403. Next, as shown in fig. 21, a first insulating layer 415 for covering the other end portion of the buried electrode 401 exposed on the first semiconductor chip 403 is formed. The first insulating layer 415 may be formed by, for example, coating an epoxy resin coating material for a mounting wiring board, or may be formed by using a film-type interlayer insulating material, a resin-attached copper foil for assisting a wiring forming process described below, or the like from the viewpoint of handling. Next, a contact hole is formed by etching the first insulating layer 415 to expose the other end portion of the buried electrode 401, and a terminal 417 connected to the buried electrode 401 via the contact hole is formed on the first insulating layer 415. The terminal 417 may be formed of Cu or the like. In the case where the terminal 417 is a Cu terminal, a barrier layer such as Ni or Au may be formed on Cu in order to prevent alloying with solder to be connected later.
Next, a second semiconductor chip 419 having a third semiconductor element 420 formed thereon is prepared, and as shown in fig. 22, an electrode 421 electrically connected to the third semiconductor element 420 formed on the second semiconductor chip 419 and a terminal 417 connected to the other end portion of the buried electrode 401 are electrically connected to each other via a second bump 423, whereby the first semiconductor chip 403 and the second semiconductor chip 419 are bonded. Specifically, the second bump 423 is formed on the terminal 417 connected to the other end portion of the buried electrode 401 formed on the first insulating layer 415 and/or the electrode 421 formed on the second semiconductor chip 419 so as to be opposed to each other and bonded by heat treatment.
After the other end portion of the buried electrode 401 and the second semiconductor chip 419 are bonded via the second bump 423, an underfill (hereinafter, referred to as a third insulating resin layer) 425 is filled in the gap between the first insulating layer 415 and the second semiconductor chip 419. The third insulating resin layer 425 is not particularly limited as long as it is an insulating resin for an underfill. Further, the third insulating resin layer 425 may be formed before the other end portion of the buried electrode 401 and the second semiconductor chip 419 are bump bonded.
Next, an insulating resin layer (hereinafter, referred to as a fourth insulating resin layer) 427 for burying the thickness of the second semiconductor chip 419 is formed on the first insulating layer 415. As the resin used for the fourth insulating resin layer 427, the same material as the second insulating resin layer 113 described in the first embodiment of the present invention is used as the second insulating resin layer 413.
After the fourth insulating resin layers 427 are cured, as shown in fig. 23, the back surfaces of the second semiconductor chips 419 on which the third semiconductor elements 420 are not formed are ground by back grinding until each of the fourth insulating resin layers 427 reaches a desired thickness (finished thickness). When the second semiconductor chip 419 and the fourth insulating resin layer 427 are polished, a BSG tape is attached to the back surface of the semiconductor wafer 101 on which the first semiconductor element 103 is not formed, and the second semiconductor chip 419 is thinned by a back surface polishing step. After the thinning of the second semiconductor chip 419 is completed, the BSG tape is peeled from the back surface of the semiconductor wafer 101.
Next, a second insulating layer 429 is formed on the polished surfaces of the second semiconductor chip 419 and the fourth insulating resin layer 427. The second insulating layer 429 may be formed using the same material as the first insulating layer 415. As shown in fig. 24, an opening portion for exposing the electrode 104 formed on the semiconductor wafer 101 is formed in the second insulating layer 429, the fourth insulating resin layer 427, the first insulating layer 415, and the second insulating resin layer 413, and a conductive layer is formed and patterned by a half-addition method or the like over the entire upper surface of the semiconductor wafer 101, that is, over the electrode 104 exposed through the opening portion and the side surface of the opening portion, over the second insulating layer 429, whereby a wiring 431 for burying the opening portion and a wiring 433 connected to the wiring 431 are formed. After that, an insulating film 434 is formed over the wiring 433, and a terminal 435 connected to the wiring 433 is formed over the insulating film 434. After the solder resist 436 is applied to the terminal 435, an opening is made to expose the terminal 435. An external terminal 437 is formed on the terminal 435 as needed. The external terminals 437 may be BGA balls.
Thereafter, the back surface of the semiconductor wafer 101 on which the first semiconductor element 103 is not formed is polished by back surface polishing until the thickness reaches the finished thickness. At the end of thinning of the semiconductor wafer 101, the second insulating resin layer 413 is exposed at the region where the groove 201 is formed on the back surface side of the semiconductor wafer 101 where the first semiconductor element 103 is not formed. As shown in fig. 25, the semiconductor wafer 101 is singulated by dicing the solder resist 436, the insulating film 434, the second insulating layer 429, the fourth insulating resin layer 427, the first insulating layer 415, and the second insulating resin layer 413 along boundary lines formed in the element region of the semiconductor wafer 101, thereby manufacturing the semiconductor device 40.
Before singulating the semiconductor wafer 101, an insulating film may be formed on the back surface of the semiconductor wafer 101 by an insulating resin or the like and cured, as necessary. When an insulating film is formed on the back surface of the semiconductor wafer 101, the insulating film on the back surface of the semiconductor wafer 101 is diced together with the solder resist 436, the insulating film 434, the second insulating layer 429, the fourth insulating resin layer 427, the first insulating layer 415, and the second insulating resin layer 413 to singulate the semiconductor wafer 101. When the grooves 201 are not formed in advance on the semiconductor wafer 101, the semiconductor wafer 101 is diced together with the solder resist 436, the insulating film 434, the second insulating layer 429, the fourth insulating resin layer 427, the first insulating layer 415, and the second insulating resin layer 413 at the time of dicing.
According to the method for manufacturing a semiconductor device of the fourth embodiment of the present invention, it is possible to manufacture a semiconductor device including three or more stacked chips including a semiconductor chip with TSVs, which has improved yield and reliability by suppressing bump connection failure or short circuit caused by bending of the chip at the time of bump connection. In addition, the manufacturing cost can be reduced as in the method for manufacturing the semiconductor device according to the first and second embodiments of the present invention.
Further, referring to fig. 19 to 25, a method of manufacturing the semiconductor device 40 in which the first semiconductor chip 403 having the TSV formed therein and the second semiconductor chip 419 having the third semiconductor element 420 formed therein are stacked one by one on one element region of the semiconductor wafer 101 will be described, and a plurality of first semiconductor chips 403 having the TSV formed therein and a plurality of second semiconductor chips 419 having the third semiconductor element formed therein may be stacked on one element region of the semiconductor wafer 101 in the same manner as the method of manufacturing the semiconductor device according to the third embodiment of the present invention described above. That is, the plurality of first semiconductor chips 403 may be laid flat for one element region of the semiconductor wafer 101 to be bonded, and the second semiconductor chips 419 may be bonded to the plurality of first semiconductor chips 403, respectively.
In addition, when a plurality of semiconductor chips including semiconductor chips having TSVs formed thereon are stacked on an element region of a semiconductor wafer, the number of stacked semiconductor chips may be different in one semiconductor device. For example, in the case where two semiconductor chips are placed on one element region of a semiconductor wafer and bonded to the semiconductor wafer via bumps, as in the semiconductor device 40' according to one embodiment of the present invention shown in fig. 26, one of the two semiconductor chips placed on the element region of the semiconductor wafer 101 may be set as the first semiconductor chip 403 on which TSVs are formed, and the other may be set as the third semiconductor chip 439 on which the fourth semiconductor element 441 is formed, and bonded to the semiconductor wafer 101 via the first bumps 409. In this case, on the first semiconductor chip 403 formed with the TSV, the second semiconductor chip 419 formed with the third semiconductor element 420 may be bonded via the second bump 423.
< Fifth embodiment >
An outline of a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention will be described with reference to fig. 27 to 33. In the method for manufacturing a semiconductor device according to the fifth embodiment, unlike the method for manufacturing a semiconductor device according to the first to fourth embodiments, a semiconductor wafer having a first semiconductor element and TSVs having one end connected to the first semiconductor element formed in each element region is used as the semiconductor wafer. In the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention described below, an example will be described in which a semiconductor wafer having a TSV formed is applied to a semiconductor wafer used in the method for manufacturing a semiconductor device according to the second embodiment. Here, the description repeated with the method for manufacturing the semiconductor device of the second embodiment is omitted or simplified.
First, a semiconductor wafer 501 having a plurality of element regions formed therein is prepared. Here, as shown in fig. 27, a buried electrode 503 having one end exposed is formed on a semiconductor wafer 501. Further, a first semiconductor element 505 electrically connected to an exposed end portion of the buried electrode 503 is formed on the semiconductor wafer 501. Similarly to the method of manufacturing the semiconductor device according to the second embodiment of the present invention, the groove 201 is formed on the surface of the semiconductor wafer 501 on which the first semiconductor element 505 is formed along the boundary line of the element region.
As in the method for manufacturing a semiconductor device according to the second embodiment of the present invention, as shown in fig. 28, an electrode 506 and an electrode 107 are electrically connected to each other via a bump 109 to bond a semiconductor wafer 501 and a semiconductor chip 105, the electrode 506 is connected to a first semiconductor element 505 formed on the semiconductor wafer 501 and faces the semiconductor chip 105, the electrode 107 is connected to a second semiconductor element 106 formed on the semiconductor chip 105 via a wiring, a gap between the semiconductor wafer 501 and the semiconductor chip 105 is buried with a first insulating resin layer 111, and a second insulating resin layer 113 is formed on the semiconductor wafer 501 until the thickness for burying the semiconductor chip 105 is reached.
Next, as shown in fig. 29, the semiconductor chip 105 is thinned by back grinding until each of the second insulating resin layers 113 reaches a finished thickness. Thereafter, as shown in fig. 30, a first insulating layer 114 is formed on the polished surfaces of the semiconductor chip 105 and the second insulating resin layer 113. An opening for exposing the electrode 506 formed on the semiconductor wafer 501 is formed in the first insulating layer 114 and the second insulating resin layer 113, and a conductive layer is formed over the entire upper surface of the semiconductor wafer 501, that is, over the first insulating layer 114, over the electrode 506 exposed through the opening, and on the side surface of the opening by a half-addition method or the like, and is patterned, whereby a wiring 117 for burying the opening and a wiring 507 connected to the wiring 117 are formed. Thereafter, an insulating film 508 is formed over the wiring 507, and a terminal 509 connected to the wiring 507 is formed over the insulating film 508. After the solder resist 510 is applied to the terminal 509, the terminal 509 is exposed by opening.
Next, a wafer holder is mounted on the side of the terminal 509 formed on the semiconductor chip 105, and the semiconductor wafer 501 is polished until the other end of the buried electrode 503 is brought forward, thereby thinning the semiconductor wafer 501. Thereafter, the semiconductor wafer 501 is polished by CMP or the like to expose the other end portion of the buried electrode 503. Thus, the buried electrode 503 functions as a TSV penetrating the semiconductor wafer 501. At the time of exposing the other end portion of the buried electrode 503, the second insulating resin layer 113 is exposed in the region where the groove 201 is formed on the back surface side of the semiconductor wafer 501 where the first semiconductor element 505 is not formed, and the side surface of the semiconductor wafer 501 corresponding to each element region is covered with the second insulating resin layer 113.
Next, as shown in fig. 31, a second insulating layer 512 is formed on the semiconductor wafer 501. The second insulating layer 512 may be formed of the same material as the first insulating layer 114. After the second insulating layer 512 is formed with an opening for exposing the buried electrode 503, a conductive layer including a terminal 511 connected to the other end portion of the buried electrode 503 is formed on the second insulating layer 512. In the conductive layer, a wiring (not shown) may be formed in addition to the terminal 511, and a separate wiring layer may be formed between the semiconductor wafer 501 and the conductive layer as needed. The terminal 511 may be formed by applying a conductive material to the entire surface of the second insulating layer 512 and patterning the conductive material. Next, a solder resist 513 is applied to the entire surface of the terminal 511 and the second insulating layer 512, and patterning is performed to form an opening 515 exposing the terminal 511.
Next, as shown in fig. 32, a pre-solder treatment (OSP) may be applied to the exposed terminal 511 as needed, and an external terminal 517 may be formed on the opening 515. The external terminals 517 may be BGA balls using solder. In addition, after the external terminals 517 are formed on the semiconductor wafer 501, the wafer support may be peeled off from the semiconductor chip 105 side, and if necessary, the external terminals 519 may be formed on the terminals 509 connected to the wirings 507. The external terminals 519 may be BGA balls using solder.
Thereafter, as shown in fig. 33, the solder resist 510, the insulating film 508, the first insulating layer 114, the second insulating resin layer 113, the second insulating layer 512, and the solder resist 513 are diced along boundary lines formed in the element region of the semiconductor wafer 501, and the semiconductor wafer 501 is singulated, thereby manufacturing the stacked package 50 in which thin semiconductor chips are stacked.
According to the method for manufacturing a semiconductor device of the fifth embodiment of the present invention, a stack package in which bump connection failure or short circuit caused by bending of chips at the time of bump connection of semiconductor chips to each other is suppressed and yield and reliability are improved can be manufactured.
In the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention described above, an example in which a semiconductor wafer having a TSV formed is applied to the semiconductor wafer used in the method for manufacturing a semiconductor device according to the second embodiment has been described, but a stacked package may be manufactured by applying a semiconductor wafer having a TSV formed to the semiconductor wafer used in the methods for manufacturing a semiconductor device according to the first, third, and fourth embodiments.
The first to fifth embodiments of the present invention are described above with reference to fig. 1A to 33. The present invention is not limited to the above-described embodiments, and can be appropriately modified within a range not departing from the gist of the present invention.

Claims (11)

1. A method of manufacturing a semiconductor device, comprising the steps of:
Providing a semiconductor wafer, comprising:
A top side of the semiconductor wafer;
A semiconductor wafer underside;
An electrode;
a plurality of element regions each including a first semiconductor element;
A buried electrode extending partially into the semiconductor wafer from the semiconductor wafer top side and including a first end electrically connected to the first semiconductor element and a second end remote from the semiconductor wafer top side;
An insulating film between the top side of the semiconductor wafer and the electrode; and
A wiring layer within the insulating film, the wiring layer including a vertically oriented portion and a horizontally oriented portion, the wiring layer coupling the first semiconductor element to the electrode through the insulating film;
Electrically connecting a second semiconductor element formed on the semiconductor chip with the electrode via the bump;
Providing a first insulating resin layer on the top side of the semiconductor wafer until reaching a thickness at which the semiconductor chips are buried;
Removing a portion of the first insulating resin layer and a portion of the semiconductor chip until a thickness of the semiconductor chip reaches a first predetermined thickness;
Providing a first conductive wiring electrically coupled to the electrode and extending through the first insulating resin layer;
providing a second conductive wiring over the first insulating resin layer, the second conductive wiring being connected to the first conductive wiring;
Providing a first terminal electrically connected to the second conductive wiring;
Removing a portion of the semiconductor wafer from the underside of the semiconductor wafer until the thickness of the semiconductor wafer reaches a second predetermined thickness and the second end of the buried electrode is exposed; and
A second terminal coupled to the second end of the buried electrode is provided.
2. The method for manufacturing a semiconductor device according to claim 1, wherein providing the first conductive wiring comprises:
providing an opening in the first insulating resin layer to expose the electrode; and
The opening is filled with a conductive material.
3. The method for manufacturing a semiconductor device according to claim 1, further comprising:
Before or after connecting the semiconductor wafer and the semiconductor chip, a gap between the semiconductor wafer and the semiconductor chip is filled with a second insulating resin layer.
4. The method for manufacturing a semiconductor device according to claim 1, wherein:
the buried electrode is laterally spaced apart from the semiconductor chip; and
The wiring layer couples the buried electrode to the semiconductor chip.
5. The method for manufacturing a semiconductor device according to claim 1, further comprising:
providing a first insulating layer on the first insulating resin layer and the semiconductor chip;
Wherein:
providing the first conductive wiring includes providing the first conductive wiring extending through the first insulating layer; and
Providing the second conductive wiring includes forming the second conductive wiring on the first insulating layer;
Providing a second insulating layer adjacent the second end of the buried electrode; and
Providing an opening in the second insulating layer;
Wherein:
Providing the second terminal includes coupling the second terminal to the second end of the buried electrode through the opening.
6. The method for manufacturing a semiconductor device according to claim 1, further comprising:
Providing a groove having a width wider than a dicing width in the semiconductor wafer along a boundary line between the plurality of element regions formed as part of the semiconductor wafer; and
Singulating the semiconductor wafer;
Wherein:
Providing the semiconductor wafer includes providing the first semiconductor element overlapping the buried electrode such that the buried electrode extends from an underside of the first semiconductor element;
singulating the semiconductor wafer includes singulating the semiconductor wafer along the slots formed in the semiconductor wafer,
The scribe width is narrower than the width of the trench;
providing the groove occurs before providing the first insulating resin layer;
the first insulating resin layer contacts one side of the semiconductor wafer; and
The portion of the semiconductor wafer is removed, exposing the first insulating resin layer at the underside of the semiconductor wafer.
7. The method for manufacturing a semiconductor device according to claim 6, wherein:
removing the portion of the semiconductor wafer includes removing until the thickness of the semiconductor wafer reaches a finished thickness; and
The depth of the groove is greater than or equal to the finished thickness.
8. A method of manufacturing a semiconductor device, comprising the steps of:
providing a substrate, comprising:
A top side;
A bottom side opposite the top side;
An electrode;
A plurality of element regions, each element region including a first electronic element adjacent to and within the top side of the substrate;
a buried electrode having a first end electrically connected to the first electronic component within the substrate, and a second end extending partially into the substrate without extending to the bottom side of the substrate;
an insulating film between the top side of the substrate and the electrode; and
A wiring layer within the insulating film, the wiring layer including a vertically oriented portion and a horizontally oriented portion, the wiring layer coupling the first electronic component to the electrode through the insulating film;
Electrically connecting a second electronic element of the electronic chip with the electrode via the bump;
Filling a gap between the substrate and the electronic chip facing each other with a first insulating resin layer before or after connecting the substrate and the electronic chip;
Providing a second insulating resin layer on the substrate until reaching a thickness at which the electronic chip is buried;
Removing a portion of the second insulating resin layer and a portion of the electronic chip until a thickness of the electronic chip reaches a first predetermined thickness;
providing a first conductive wiring electrically coupled to the electrode, wherein the first conductive wiring extends through the second insulating resin layer;
Providing a second conductive wiring over the second insulating resin layer, the second conductive wiring being connected to the first conductive wiring;
Providing a first terminal electrically connected to the second conductive wiring;
Removing a portion of the substrate from the bottom side of the substrate until the thickness of the substrate reaches a second predetermined thickness, wherein:
a second terminal is provided to be electrically connected to the second end of the buried electrode.
9. The method for manufacturing a semiconductor device according to claim 8, further comprising:
Providing a first insulating layer on the second insulating resin layer;
providing a first opening portion in the first insulating layer and the first insulating resin layer to expose the electrode;
Filling the first opening portion with a conductive material to provide a first conductive wiring;
Providing a second insulating layer over the substrate adjacent the second end of the buried electrode; and
Providing a second opening in the second insulating layer adjacent the second end of the buried electrode;
Wherein:
The wiring layer couples the buried electrode to the first conductive wiring and the electronic chip; and
Providing the second terminal includes coupling with the second terminal through the second opening.
10. A semiconductor device, comprising:
a semiconductor substrate, the semiconductor substrate comprising:
A top side;
A bottom side;
a side extending between the top side and the bottom side;
An insulating film on the top side;
A wiring layer located within the insulating film and including a vertically oriented portion and a horizontally oriented portion; and
An electrode located above the insulating film and coupled to the wiring layer,
A semiconductor chip comprising a first major surface, wherein the first major surface comprises a first semiconductor element, the first semiconductor element being electrically connected with the electrode via a bump;
A first insulating resin layer disposed between the insulating film and the semiconductor chip;
A second insulating resin layer over portions of the semiconductor substrate and the semiconductor chip, wherein a second main surface of the semiconductor chip opposite to the first main surface is exposed via a surface of the second insulating resin layer;
A first conductive wiring electrically coupled to the electrode, wherein the first conductive wiring extends through the second insulating resin layer;
A second conductive wiring on the second insulating resin layer, the second conductive wiring being connected to the first conductive wiring;
a first terminal electrically connected to the second conductive wiring, wherein:
The semiconductor substrate includes an element region having a second semiconductor element adjacent to the top side;
the wiring layer is coupled with the second semiconductor element and the first semiconductor element; and
The semiconductor substrate further includes:
a buried electrode having a first end electrically connected to the second semiconductor element within the semiconductor substrate and a second end exposed outside the bottom side; and
And a second terminal electrically connected to the second end of the buried electrode.
11. The semiconductor device according to claim 10, further comprising:
An insulating layer adjacent to the bottom side and including an opening;
Wherein:
The wiring layer couples the buried electrode to the first conductive wiring and the first semiconductor element;
the buried electrode overlaps the second semiconductor element within the semiconductor substrate;
The buried electrode extends downward from a lower side of the second semiconductor element;
the second terminal is connected to the second end portion of the buried electrode through the opening portion in the insulating layer; and
The second insulating resin layer contacts the side surface of the semiconductor substrate and contacts the insulating layer near the bottom side.
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