CN110505161B - Message processing method and device - Google Patents

Message processing method and device Download PDF

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Publication number
CN110505161B
CN110505161B CN201910904680.2A CN201910904680A CN110505161B CN 110505161 B CN110505161 B CN 110505161B CN 201910904680 A CN201910904680 A CN 201910904680A CN 110505161 B CN110505161 B CN 110505161B
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message
processed
ethernet port
cpu
chip
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CN110505161A (en
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阎鑫淼
任红军
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Hangzhou DPTech Technologies Co Ltd
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Hangzhou DPTech Technologies Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3009—Header conversion, routing tables or routing tags
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements

Abstract

The application discloses a message processing method and device. The method is applied to equipment comprising a multi-core CPU and a field programmable gate array FPGA chip, and comprises the following steps: the method comprises the steps that an FPGA chip receives a message to be processed through an Ethernet port of the FPGA chip, and remark information is added into the message to be processed; analyzing and extracting quintuple information from the message to be processed based on message analysis logic built in the FPGA chip; determining a message receiving queue matched with the message to be processed as a target message receiving queue according to the extracted quintuple information; and adding the message to be processed to the target message receiving queue so that the CPU core corresponding to the target message receiving queue receives the message to be processed. Compared with the prior art, the advantage of parallel processing of the multi-core CPU can still be exerted when the multi-core CPU receives the message which cannot correctly identify the quintuple information.

Description

Message processing method and device
Technical Field
The present application relates to the field of network communication technologies, and in particular, to a method and an apparatus for processing a packet.
Background
Currently, a device equipped with a Central Processing Unit (CPU) generally receives a message through a network controller for Processing. Based on the advantage of parallel processing of the multi-core CPU, different CPU cores can process messages with different quintuples (source IP, destination IP, protocol number, source Port and destination Port); each CPU core usually corresponds to one message receive queue and one message transmit queue, and all the message receive queues and transmit queues are maintained by the network controller. That is, when the network controller receives a message, the message is added to a corresponding message receiving queue according to the quintuple extracted from the message, and the CPU core responsible for processing the message acquires the message from the receiving queue for processing.
In general, since the position of the quintuple in the packet is fixed, the network controller can extract the quintuple according to the fixed position of the quintuple. However, in some cases, remark information may be added to a certain position in the packet, which destroys the original information structure in the packet, so that the position of the quintuple in the packet changes, which causes the network controller to be unable to accurately extract the quintuple from the packet, and also to be unable to add the packet to the matched packet receiving queue, thereby causing the advantage of parallel processing of the multi-core CPU to be unable to be exerted.
Disclosure of Invention
In order to solve the technical problems, the application discloses a message processing method, which comprises the following technical scheme:
a message processing method is applied to equipment comprising a multi-core CPU and a Field Programmable Gate Array (FPGA) chip, wherein the FPGA chip maintains N message receiving queues, and each message receiving queue corresponds to a CPU core in the multi-core CPU;
the message processing method comprises the following steps:
the FPGA chip receives a message to be processed, and remark information is added to the message to be processed;
extracting quintuple information from the message to be processed based on a built-in message analysis logic;
determining a target message receiving queue matched with the message to be processed from the N message receiving queues according to the extracted quintuple information;
and adding the message to be processed to the target message receiving queue so that a CPU core corresponding to the target message receiving queue receives the message to be processed from the target message receiving queue for processing.
The device comprises a multi-core CPU and a field programmable gate array FPGA chip; the FPGA chip is maintained with N message receiving queues, and each message receiving queue corresponds to one CPU core in the multi-core CPU;
the FPGA chip is used for receiving a message to be processed, and remark information is added to the message to be processed; analyzing and extracting quintuple information from the message to be processed based on a built-in message analysis logic; determining a target message receiving queue matched with the message to be processed from the N message receiving queues according to the extracted quintuple information; and adding the message to be processed to the target message receiving queue so that a CPU core corresponding to the target message receiving queue receives the message to be processed from the target message receiving queue for processing.
According to the technical scheme, an FPGA chip is added, and message receiving work is transferred to the FPGA chip to be executed by a network controller. Because the FPGA chip is provided with the Ethernet port and can be used as slave equipment of the multi-core CPU on a bus, the FPGA chip can replace a network controller structurally. Due to the programmable characteristic of the FPGA chip, the message analysis logic can be arranged in the FPGA chip by writing a program, the message analysis logic can eliminate the interference of remark information and extract correct quintuple from the message, and the FPGA chip can maintain a plurality of message receiving queues to support the parallel characteristic of a multi-core CPU.
By applying the technical scheme disclosed by the application, the message can be added to the matched message receiving queue, and the parallel processing advantage of the multi-core CPU is further exerted.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the description below are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art according to these drawings.
Fig. 1 is a schematic structural diagram of a multi-core CPU receiving and sending a message through a network controller, disclosed in the prior art;
fig. 2 is a schematic diagram illustrating a principle of receiving and sending a message by a multi-core CPU through a network controller and a switch chip in the prior art;
fig. 3 is a schematic diagram illustrating a principle that a multi-core CPU receives a message through an FPGA chip according to an embodiment of the present application;
fig. 4 is a schematic flowchart of a message processing method disclosed in an embodiment of the present application;
FIG. 5 is a schematic diagram of an apparatus provided in a first embodiment of the present application;
fig. 6 is a schematic diagram illustrating a principle that a multi-core CPU receives a message through an FPGA chip and sends the message through a network controller according to a second embodiment of the present application;
fig. 7 is a schematic flowchart of a message processing method disclosed in the second embodiment of the present application;
fig. 8 is a schematic diagram illustrating a principle that a multi-core CPU receives and sends a message through an FPGA chip according to a third embodiment of the present application;
fig. 9 is a schematic structural diagram of an FPGA chip in the fourth embodiment of the present application;
fig. 10 is a schematic structural diagram of a chip including a multi-core CPU and an FPGA in the fifth embodiment of the present application;
fig. 11 is a schematic structural diagram of an apparatus including a multi-core CPU, an FPGA chip, a switch chip, and a network controller in the fifth embodiment of the present application.
Detailed Description
Fig. 1 is a schematic structural diagram of a device (such as a network switching device) equipped with a multi-core central processing unit CPU and a network controller in the related art. The network controller is provided with an Ethernet port and maintains a plurality of message receiving queues and message sending queues; the multi-core CPU comprises N CPU cores, and each CPU core corresponds to a message sending queue and a message receiving queue respectively.
After receiving the message through the Ethernet port, the network controller distributes the message to a certain message receiving queue, and a CPU core corresponding to the message receiving queue in the multi-core CPU receives the message from the queue for processing; when sending a message, a certain CPU core in the multi-core CPU inserts the message to be sent into a message sending queue corresponding to the CPU core, and the network controller sends out the message in the message sending queue through an Ethernet port of the network controller.
The method for the network controller to distribute the packet to a certain packet receiving queue may be that the network controller distributes the packet according to quintuple information (including source IP, destination IP, protocol number, source port number, and destination port number of the packet) in the packet. Since the position of the quintuple in the message is fixed, the network controller can obtain the information of the quintuple in the message by obtaining the field of the fixed position in the message.
But in some cases the message will be added with remark information. The remark information is auxiliary information required by the CPU for service processing according to the message content. The addition of remark information may affect the position of the quintuple in the message to change, so that the network controller cannot obtain correct message quintuple information when acquiring the field of the fixed position in the message. For example, if 3 bytes (i.e., 24 bits) of remark information is added to the header of the IP packet, the correct packet five-tuple information is shifted back by 24 bits, and the network controller still obtains data from the original location, and the correct packet five-tuple information cannot be obtained. When correct message five-tuple information cannot be obtained, the network controller can fixedly send the message with the remark information to a certain fixed message receiving queue because the message with the remark information cannot be distributed to the corresponding message receiving queue according to the existing rule.
As an example of a situation where remark information is added to a message so that a network controller cannot obtain correct message five-tuple information, a schematic diagram of a hardware structure for transmitting and receiving the message is shown in fig. 2. Compared to fig. 1, a switching chip is added. The exchange chip is connected with the network controller through the Ethernet port, and is also provided with a plurality of other Ethernet ports for sending or receiving messages outwards, so that the Ethernet port is expanded.
When receiving a message, the switching chip receives the message through a certain Ethernet port, remark information can be added to the received message at the head of the message, the addition of the remark information enables the position of the message quintuple information to move backwards, and then the message added with the remark information is sent to the Ethernet port of the network controller, so that the network controller cannot obtain correct message quintuple information. The remark information may include identification information of an ethernet port on the switch chip that receives the packet, so as to inform the CPU core that processes the packet of the identification information.
Under the condition that the network controller cannot obtain correct message five-tuple information by adding the remark information in the message, the network controller can fixedly send the message with the remark information to a certain fixed message receiving queue, so that the CPU core which only corresponds to the message receiving queue can process the message with the remark information, and the advantage of parallel message processing of a multi-core CPU (central processing unit) cannot be exerted when a plurality of messages with the remark information are received.
The technical scheme of this application aims at solving above-mentioned technical problem.
In order to make those skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be described in detail below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all embodiments. All other embodiments that can be derived from the embodiments given herein by a person of ordinary skill in the art are intended to be within the scope of the present disclosure.
The first embodiment is as follows:
fig. 3 is a schematic diagram of a principle that a multi-core CPU receives a message through an FPGA chip, as shown in fig. 3, the multi-core CPU includes a multi-core CPU and an FPGA chip, where the multi-core CPU includes N CPU cores, and N is a natural number greater than 1; the five-tuple information contained in the messages which are processed by different CPU cores of the multi-core CPU is different; the FPGA chip maintains N message receiving queues; the N message receiving queues correspond to N CPU cores one by one, and the message receiving queues can be distributed to the FPGA chip by the multi-core CPU according to the core number of the multi-core CPU when the equipment is initialized; for each CPU core, the CPU core can acquire a message from a message receiving queue corresponding to the CPU core maintained by the FPGA chip for processing in a mode of accessing the FPGA chip; the FPGA chip is provided with an Ethernet port and is internally provided with a preset message analysis logic, and the message analysis logic is used for analyzing and extracting correct message quintuple information from the messages added with remark information. After receiving a message from an Ethernet port, the FPGA chip extracts quintuple information from the message according to a built-in message analysis logic and distributes the message to a certain message receiving queue according to the quintuple information, so that a CPU core corresponding to the message receiving queue obtains the message from the message receiving queue.
The first embodiment will be described with reference to a specific flow of steps, as shown in fig. 4.
S401, the FPGA chip receives the message to be processed.
It should be noted that remark information is added to the message to be processed.
As an example, the message to be processed received by the FPGA chip may come from the switch chip, and the schematic structural diagram is shown in fig. 5. The switching chip is provided with a first type Ethernet port and is used for being connected with the Ethernet port of the FPGA; the switching chip is also provided with a plurality of second-type Ethernet ports for receiving and sending messages from an external network. It should be noted that the first type ethernet port, the second type ethernet port, and a third type ethernet port, which will be mentioned later, of the switch chip are all for convenience of description, and they are ethernet ports disposed at different positions on the switch chip.
Before the FPGA chip receives the message to be processed through the Ethernet port, the switching chip can receive an original message through one second-type Ethernet port, add a section of remark information to the original message to obtain the message to be processed, wherein the remark information is used for identifying the attribute of the Ethernet port for receiving the original message, for example, the remark information can contain the network port identification of the second-type Ethernet port for receiving the original message, and then send the message to be processed to the Ethernet port of the FPGA chip through the first-type Ethernet port. The network port identifier can exist in a plaintext form or can be packaged in a ciphertext form; the remark information may be of a fixed length, for example, S bytes, or may be of an indefinite length, which is not limited in this embodiment.
S402, analyzing and extracting quintuple information from the message to be processed based on the built-in message analysis logic.
The FPGA chip can eliminate the interference of remark information according to the built-in message analysis logic, and extract correct quintuple information from the message to be processed.
Under the example that the message to be processed received by the FPGA chip comes from the switching chip, the remark information contains the Ethernet port identification information of the switching chip and is fixed-length information, the FPGA chip can strip the first S bytes of the header of the message to be processed, namely the remark information is stripped by the FPGA chip, the other part of the message to be processed (namely the original message obtained by restoring the message to be processed) is extracted from the original message by using the fixed position of the message quintuple as a basis.
As another example, when the length of the remark information is not fixed, the FPGA chip checks bytes from the end of the message and records the checked byte length until the first byte length represented by the checked bytes is equal to the length of the checked bytes plus a second byte length, where the second byte length is a fixed byte length from the beginning of the message without the remark information to the byte recording the message length, and at this time, the byte currently checked is considered as the byte recording the message length, extracts the message without the remark information according to the position information, and extracts the message quintuple information from the message without the remark information according to the fixed position of the message quintuple.
S403, determining a target message receiving queue matched with the message to be processed according to the extracted quintuple information.
And the FPGA chip determines a message receiving queue matched with the message to be processed through certain calculation and matching according to the extracted correct quintuple information.
As an example, a hash value of five tuple information may be calculated, and a packet receiving queue matching the packet to be processed may be determined according to the calculated hash value. More specifically, when matching is performed according to the hash value of the quintuple information, the possible value number of the hash value can be made to be consistent with the number of the CPU cores of the multi-core CPU, and the values of the plurality of hash values correspond to the plurality of packet receiving queues one to one. For example, when the number of cores of the multi-core CPU is 100, there are also 100 message receiving queues, and the hash value is determined as a natural number within 100, that is, the quintuple information changes, and the hash value calculated according to the quintuple information is a natural number within 100, where 100 hash values correspond to 100 message receiving queues one to one, and when the hash value calculated according to the quintuple information is 5, the message receiving queue corresponding to 5 is determined as the message receiving queue matching the message.
According to the number of the CPU cores of the multi-core CPU, a certain number of bits in the hash value in the binary form can be used, so that the possible value range of the hash value is divided into a plurality of ranges, the number of the ranges is consistent with the number of the CPU cores of the multi-core CPU, and the plurality of ranges correspond to the plurality of CPU cores one by one. The FPGA chip can predetermine all M-bit binary numbers and distribute all the M-bit binary numbers to the N message receiving queues; wherein M is more than 0, more than or equal to N and less than N; and the FPGA chip calculates the hash value of the quintuple information, extracts binary numbers from the P-th bit to the P + M-1-th bit from the calculated hash value, wherein P is larger than 0, and determines a message receiving queue corresponding to the extracted M-bit binary number as a message receiving queue matched with the message to be processed. For example, when the core number of the multi-core CPU is 4, there are also 4 message receiving queues, the hash value is determined as a 32-bit binary number, the first two bits of the hash value in a binary form are selected, possible values of the hash value are divided into 4 ranges, the first two bits of the hash value are 00, 01, 10, and 11, respectively, wherein the 4 ranges correspond to the 4 message receiving queues one by one, and when the first two bits of the 32-bit binary hash value calculated by quintuple information are 00, the message receiving queue corresponding to the first two bits of the hash value being 00 is determined as a message receiving queue matched with the message.
As another example, five pieces of information in the five-tuple information may be summed as binary numbers, and then the sum is divided by the core number of the multi-core CPU, and matching is performed according to a remainder, where a plurality of remainders correspond to a plurality of message receiving queues one to one. For example, the core number of the multi-core CPU is 5, 0, 1, 2, 3, and 4 are in one-to-one correspondence with 5 different message receiving queues, and when the summation of some message five-tuple information is 19384, the remainder obtained by dividing 19384 by 5 is 4, and the message is distributed to the message receiving queue corresponding to 4.
S404, adding the message to be processed to the target message receiving queue.
After the target message receiving queue is determined, the FPGA chip adds the message to be processed to the target message receiving queue so that the CPU core corresponding to the target message receiving queue obtains the message to be processed from the target message receiving queue.
As an example, if the remark information is encapsulated, in order to enable the CPU to directly obtain the port identifier of the second type ethernet port in the plaintext when processing the packet, the FPGA chip may analyze the remark information to obtain an analysis result before adding the packet to be processed to the target packet receiving queue, and replace the remark information with the analysis result.
According to the first embodiment, when a message is received, the FPGA chip is used to maintain a plurality of message receiving queues, the FPGA chip is provided with an ethernet port connected with the switch chip, the FPGA chip is used as a slave device of the PCIE bus to interact with the multi-core CPU, and the plurality of message receiving queues correspond to the plurality of CPU cores one to one. Due to the programmable characteristic, the FPGA chip is internally provided with message analysis logic, so that the FPGA chip can extract correct message quintuple information from the message with remark information. When receiving messages, the FPGA chip receives the messages with remark information through the Ethernet port, extracts correct message quintuple information in the messages with the remark information, and distributes the messages with the remark information to a certain message receiving queue according to the message quintuple information, so that a CPU core corresponding to the message receiving queue in the multi-core CPU receives the messages from the queue for processing.
Therefore, the messages with remark information can be distributed to the message receiving queues corresponding to different CPU cores, and the original parallel processing advantage of the multi-core CPU can be exerted.
The statement of embodiment one ends up here.
On the basis of the first embodiment, the present application further discloses another message processing and sending method, as shown in the second embodiment.
Example two:
fig. 6 is a schematic diagram of a principle that a multi-core CPU receives a message through an FPGA chip and sends the message through a network controller according to the embodiment, and as shown in fig. 6, on the basis of the architecture shown in fig. 5, the device further includes the network controller; the switching chip also comprises a third type Ethernet port connected with the Ethernet port of the network controller; the network controller maintains N message sending queues; the N message sending queues correspond to N CPU cores one by one, and the message sending queues can be distributed to a network controller by a multi-core CPU according to the core number of the multi-core CPU when equipment is initialized; each CPU core can access a network controller and insert a message into a message sending queue corresponding to the CPU core in the network controller. After the FPGA chip receives a message from an Ethernet port, extracting quintuple information from the message according to a built-in message analysis logic, and distributing the message to a certain message receiving queue according to the quintuple information; the CPU core corresponding to the message receiving queue acquires the message from the message receiving queue, the CPU core determines the message to be sent which needs to be sent and sends the message to be sent to the message sending queue corresponding to the CPU core in the network controller, the network controller sends the message to be sent in the message sending queue to a third type of Ethernet port of the switching chip through the Ethernet port, and the switching chip sends the message to be sent out through a second type of Ethernet port.
Next, example two will be described with reference to a specific flow of steps, as shown in fig. 7.
S701, the CPU core obtains the message from the corresponding message receiving queue.
S702, the CPU core performs service processing on the message and determines the message to be sent according to the processing result.
As an example, after the CPU core performs service processing on the message, a new message is generated and determined as a message to be sent.
As another example, the CPU core performs service processing on the packet, and directly determines the packet as a packet to be sent.
As another example, after obtaining the result of processing the message, the CPU core determines that a certain second-type ethernet port of the switch chip is a target ethernet port, so that the message to be sent is sent out from the target ethernet port. And obtaining remark information according to the network port identification information of the target Ethernet port, and determining to send a message to be sent according to a processing result, wherein the message to be sent contains the remark information. Wherein the remark information includes the network port identification information of the target Ethernet port. Of course, the remark information may not include the port identification information of the target ethernet port.
Note that, the remark information here is not the same concept as the remark information in the first embodiment, where the remark information encapsulates the port identification information of the second type of ethernet port that sends the message, and the remark information in the distribution stage encapsulates the port identification information of the second type of ethernet port that receives the message.
And S703, the CPU core inserts the message to be sent into a message sending queue corresponding to the CPU core and maintained by the network controller.
S704, the network controller sends the message to be sent in the message sending queue to the third type ethernet port of the switch chip through the ethernet port.
Under the example that the CPU core obtains remark information according to the port identification information of the target ethernet port of the switch chip and adds the remark information to the message to obtain a message to be sent, the network controller may extract the message to be sent from the message sending queue and send the message to be sent to the third type ethernet port of the switch chip through its own ethernet port. The switching chip obtains the network port identification of the target Ethernet port according to the remark information in the message to be sent, and then sends the message to be sent or the message to be sent without remark information out from the target Ethernet port corresponding to the network port identification information.
S705, the switch chip sends the message to be sent.
As an example, when the remark information specifies that the target ethernet port sends a message, the switch chip may send the message to be sent through the target ethernet port.
As another example, when the remark information does not specify a target ethernet port to send a message, the switch chip may send the message to be sent through any second type ethernet port.
The second embodiment can separate the receiving and sending processes of the message, is more convenient to manage, and can also fully utilize the bandwidth between the multi-core CPU and the FPGA chip and the bandwidth between the multi-core CPU and the network controller.
The description of example two ends here.
Example three:
fig. 8 is a schematic diagram illustrating a principle that a multicore CPU receives and transmits a message through an FPGA chip according to this embodiment. As shown in fig. 8, on the basis of the second embodiment, the network controller is replaced by an FPGA chip, that is, the FPGA chip also maintains N message sending queues. The N message sending queues correspond to N CPU cores one by one, and the message sending queues can be distributed to the FPGA chip by the multi-core CPU according to the core number of the multi-core CPU when the equipment is initialized; each CPU core can access the FPGA chip and insert messages into a message sending queue corresponding to the CPU core in the FPGA chip. The main difference between the third embodiment and the second embodiment is that the work of maintaining the message sending queue is also performed by the FPGA chip, and the third embodiment can be understood by referring to the description of the second embodiment, and is not described herein again.
The third embodiment can simplify a hardware structure (without a network controller), and exert the parallel processing advantage of the multi-core CPU in a scenario where a received message carrying remark information needs to be processed and a message carrying remark information needs to be sent to the outside.
The description of example three ends here.
In addition to the above method embodiments, one available scheme is that when a multi-core CPU receives a plurality of messages with remark information, a network controller fixedly sends the messages with remark information to a fixed message receiving queue, so that a CPU core uniquely corresponding to the message receiving queue processes the messages with remark information, extracts correct message quintuple information, and then the CPU core distributes the messages with remark information to the corresponding CPU core according to the extracted message quintuple information.
In addition, the application also discloses related device embodiments and equipment embodiments, as shown in example four and example five.
Example four:
an FPGA chip has a schematic structural diagram shown in fig. 9.
The device comprises a multi-core CPU and the FPGA chip; the multi-core CPU comprises N CPU cores, wherein N is a natural number more than 1; the five-tuple information contained in the messages which are processed by different CPU cores of the multi-core CPU is different;
the FPGA chip maintains N message receiving queues; the N message receiving queues correspond to N CPU cores one by one, and the message receiving queues can be distributed to the FPGA chip by the multi-core CPU according to the core number of the multi-core CPU when the equipment is initialized; for each CPU core, the CPU core can acquire a message from a message receiving queue corresponding to the CPU core maintained by the FPGA chip for processing in a mode of accessing the FPGA chip; the FPGA chip is provided with an Ethernet port and is internally provided with a preset message analysis logic, and the message analysis logic is used for analyzing and extracting quintuple information from the message added with remark information;
the FPGA chip comprises:
901, a receiving module. The message processing device is used for receiving a message to be processed through an Ethernet port of the message processing device, wherein remark information is added in the message to be processed.
As an example, the message to be processed received by the receiving module may come from a switch chip, as shown in fig. 5.
The switching chip is provided with a first type Ethernet port and is used for being connected with the Ethernet port of the receiving module; the switching chip is also provided with a plurality of second-type Ethernet ports for receiving and sending messages from an external network. Before the receiving module receives the message to be processed through the Ethernet port, the switching chip receives the original message through a certain second type Ethernet port, and adds a section of remark information to the original message to obtain the message to be processed, wherein the remark information comprises the network port identification of the second type Ethernet port for receiving the original message. And then the message to be processed is sent to the Ethernet port of the receiving module through the first type of Ethernet port.
In an example that the message to be processed received by the receiving module is from the switch chip, as an example, the remark information may be of a fixed length and has S bytes, and the remark information is added by the switch chip before the original message to obtain the message to be processed.
And 902, an analysis and extraction module. And analyzing and extracting quintuple information from the message to be processed based on a built-in message analysis logic.
The analysis and extraction module can extract correct quintuple information from the message to be processed without being influenced by remark information according to the built-in message analysis logic.
Under the example that the message to be processed received by the analysis and extraction module is from the switch chip, the remark information contains the ethernet port identification information of the switch chip and is fixed-length information, as an example, the analysis and extraction module can strip the first S bytes of the header of the message to be processed, that is, the analysis and extraction module strips the remark information, and the correct message quintuple information is extracted from the message by using the fixed position of the message quintuple as the basis for the other parts of the message to be processed.
As another example, when the length of the remark information is not fixed, the parsing and extracting module checks bytes from the end of the message and records the checked byte length until the first byte length represented by the checked bytes is equal to the length of the checked bytes plus a second byte length, where the second byte length is a fixed byte length from the beginning of the message without the remark information to the byte length of the recorded message, and at this time, the byte currently checked is considered as the byte length of the recorded message, extracts the message without the remark information according to the position information, and extracts correct message quintuple information from the message without the remark information according to the fixed position of the message quintuple.
903, determining a module. And determining a message receiving queue matched with the message to be processed as a target message receiving queue according to the extracted quintuple information.
And the determining module determines a message receiving queue matched with the message to be processed through certain calculation and matching according to the extracted correct quintuple information.
As an example, a hash value of five tuple information may be calculated, and a packet receiving queue matching the packet to be processed may be determined according to the calculated hash value. More specifically, when matching is performed according to the hash value of the quintuple information, the possible value number of the hash value can be made to be consistent with the number of the CPU cores of the multi-core CPU, and the values of the plurality of hash values correspond to the plurality of packet receiving queues one to one. For example, when the core number of the multi-core CPU is 100, there are also 100 packet receiving queues, and the hash value is determined to be a natural number within 100, that is, the quintuple information changes, and the hash value calculated according to the quintuple information is a natural number within 100, where 100 hash values correspond to 100 packet receiving queues one to one, and when the hash value calculated according to the quintuple information is 5, the packet receiving queue corresponding to 5 is determined to be a packet receiving queue matching the packet.
According to the number of the CPU cores of the multi-core CPU, a certain number of bits in the hash value in the binary form can be utilized, so that the possible value range of the hash value is divided into a plurality of ranges, the number of the ranges is consistent with the number of the CPU cores of the multi-core CPU, and the ranges are in one-to-one correspondence with the CPU cores. For example, when the core number of the multi-core CPU is 4, there are also 4 message receiving queues, the hash value is determined as a 32-bit binary number, the first two bits of the hash value in a binary form are selected, possible values of the hash value are divided into 4 ranges, the first two bits of the hash value are 00, 01, 10, and 11, respectively, wherein the 4 ranges correspond to the 4 message receiving queues one by one, and when the first two bits of the 32-bit binary hash value calculated by quintuple information are 00, the message receiving queue corresponding to the first two bits of the hash value being 00 is determined as a message receiving queue matched with the message.
As another example, five pieces of information in the five-tuple information may be summed as binary numbers, and then the sum is divided by the core number of the multi-core CPU, and matching is performed according to a remainder, where a plurality of remainders correspond to a plurality of message receiving queues one to one.
904, add module. And adding the message to be processed to the target message receiving queue.
After the target message receiving queue is determined, the adding module adds the message to be processed to the target message receiving queue so that the CPU core corresponding to the target message receiving queue receives the message to be processed from the target message receiving queue.
As an example, before adding the to-be-processed packet to the target packet receiving queue, the adding module may analyze the remark information to obtain an analysis result, and replace the remark information with the analysis result.
The expression of example four ends here.
Example five:
a device, a schematic structural diagram of which is shown in fig. 10, includes a field programmable gate array FPGA chip and a multi-core CPU.
The multi-core CPU comprises N CPU cores, wherein N is a natural number more than 1; the five-tuple information contained in the messages which are processed by different CPU cores of the multi-core CPU is different.
The FPGA chip maintains N message receiving queues; the N message receiving queues correspond to N CPU cores one by one, and the message receiving queues can be distributed to the FPGA chip by the multi-core CPU according to the core number of the multi-core CPU when the equipment is initialized; for each CPU core, the CPU core can acquire a message from a message receiving queue corresponding to the CPU core maintained by the FPGA chip for processing in a mode of accessing the FPGA chip; the FPGA chip is provided with an Ethernet port and is internally provided with a preset message analysis logic, and the message analysis logic is used for analyzing and extracting quintuple information from the message added with remark information.
The FPGA chip is used for receiving a message to be processed through an Ethernet port of the FPGA chip, and remark information is added into the message to be processed; analyzing and extracting quintuple information from the message to be processed based on a built-in message analysis logic; determining a message receiving queue matched with the message to be processed as a target message receiving queue according to the extracted quintuple information; and adding the message to be processed to the target message receiving queue.
As an example of a device, the device further comprises a switch chip; the switching chip includes: the first type Ethernet port is used for being connected with the Ethernet port of the FPGA chip, and the second type Ethernet ports are used for receiving and sending messages;
the switching chip is used for receiving the original message through any second type Ethernet port before the FPGA chip receives the message to be processed through the Ethernet port; adding remark information to the original message to obtain the message to be processed, wherein the remark information comprises a network port identifier of any one second type Ethernet port; and sending the message to be processed to the Ethernet port of the FPGA chip through the first type of Ethernet port.
As another device example under the device example containing the switch chip, the device further includes a network controller, and a schematic structural diagram is shown in fig. 11; the switch chip further comprises: a third type Ethernet port used for connecting with the network controller; the network controller maintains N message sending queues; the N message sending queues correspond to the N CPU cores one by one, and the message sending queues can be distributed to the FPGA chip by the multi-core CPU according to the core number of the multi-core CPU when the equipment is initialized; each CPU core can access a network controller and insert a message into a message sending queue corresponding to the CPU core in the network controller;
any CPU core in the multi-core CPU is used for acquiring messages from the corresponding message receiving queue; processing the message, and determining a message to be sent according to a processing result; and inserting the message to be sent into a message sending queue which is maintained by the network controller and corresponds to the CPU core.
And the network controller is used for sending the message to be sent in the message sending queue to a third type Ethernet port of a switching chip through an Ethernet port.
The switch chip is further configured to send the message to be sent.
The description of example five ends here.
For the apparatus embodiment four and the apparatus embodiment five, since they correspond substantially to the method embodiments, reference may be made to the partial description of the method embodiments for relevant points. The above-described device embodiments and apparatus embodiments are only illustrative, wherein the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of the application. One of ordinary skill in the art can understand and implement it without inventive effort.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.

Claims (10)

1. A message processing method is characterized in that the method is applied to equipment comprising a multi-core CPU and a Field Programmable Gate Array (FPGA) chip, wherein the FPGA chip maintains N message receiving queues, and each message receiving queue corresponds to one CPU core in the multi-core CPU;
the message processing method comprises the following steps:
the FPGA chip receives a message to be processed, and remark information is added to the message to be processed; based on a built-in message analysis logic, the FPGA chip starts to check bytes from the end of the message to be processed and records the checked byte length until the first byte length represented by the checked byte is equal to the length of the checked byte plus a second byte length, the second byte length is a fixed byte length from the beginning of the message without remark information to the byte for recording the message length, at the moment, the byte which is checked currently is considered as the byte for recording the message length, the message without remark information is extracted according to the position information, and quintuple information is extracted from the message without remark information according to the fixed position of the quintuple of the message;
determining a target message receiving queue matched with the message to be processed from the N message receiving queues according to the extracted quintuple information;
and adding the message to be processed to the target message receiving queue so that a CPU core corresponding to the target message receiving queue receives the message to be processed from the target message receiving queue for processing.
2. The method of claim 1, wherein the device further comprises a switch chip, the switch chip comprising: the first type of Ethernet port is used for being connected with the Ethernet port of the FPGA chip, and the second type of Ethernet ports are used for receiving and sending messages;
before the FPGA chip receives a message to be processed, the method further includes:
the switching chip receives an original message through any second type Ethernet port;
adding remark information to the original message by the switching chip to obtain the message to be processed, wherein the remark information comprises a network port identifier of any one second type Ethernet port;
and the switching chip sends the message to be processed to the FPGA chip through the first type of Ethernet port.
3. The method according to claim 2, wherein the length of the remark information is S bytes, and the remark information is located before the original packet;
the FPGA chip analyzes and extracts quintuple information from the message to be processed based on a built-in message analysis logic, and the method comprises the following steps:
the FPGA chip strips remark information of the first S bytes of the message to be processed based on a built-in message analysis logic to obtain an original message;
quintuple information is extracted from a fixed position in the original message.
4. The method of claim 3, wherein before the FPGA chip adds the pending packet to a target packet receive queue, the method further comprises:
the FPGA chip analyzes the remark information in the message to be processed to obtain an analysis result;
and the FPGA chip replaces the remark information with an analysis result.
5. The method of claim 2, wherein the device further comprises a network controller; the switch chip further comprises: a third type Ethernet port connected with the Ethernet port of the network controller; the network controller maintains N message sending queues; each message sending queue corresponds to one CPU core in the multi-core CPU;
the method further comprises the following steps:
the CPU core acquires a message from a corresponding message receiving queue;
the CPU core processes the message and determines a message to be sent according to a processing result;
the CPU core inserts the message to be sent into a message sending queue which is maintained by the network controller and corresponds to the CPU core;
the network controller sends the message to be sent in the message sending queue to a third type Ethernet port of the switching chip through an Ethernet port;
and the switching chip sends the message to be sent.
6. The method according to claim 5, wherein the determining, by the CPU core, the message to be sent according to the processing result includes:
the CPU core determines a second type of Ethernet port used for sending the message to be sent according to the processing result, and the second type of Ethernet port is used as a target Ethernet port;
and the CPU core adds remark information to the message to obtain a message to be sent, wherein the remark information comprises the network port identification of the target Ethernet port.
7. The method according to claim 6, wherein the network controller sends the message to be sent in the message sending queue to the third type ethernet port of the switch chip through the ethernet port, further comprising:
the network controller extracts the message to be sent from the message sending queue;
the network controller sends the message to be sent to a third type Ethernet port of the switching chip through an Ethernet port of the network controller;
the exchange chip obtains the network port identification of the target Ethernet port according to the remark information in the message to be sent;
and the switching chip sends the message to be sent with the remark information stripped out from the target Ethernet port corresponding to the network port identifier.
8. A message processing device is characterized by comprising a multi-core CPU and a field programmable gate array FPGA chip; the FPGA chip is maintained with N message receiving queues, and each message receiving queue corresponds to one CPU core in the multi-core CPU;
the FPGA chip is used for receiving a message to be processed, and remark information is added into the message to be processed; based on a built-in message analysis logic, the FPGA chip starts to check bytes from the end of the message to be processed and records the length of the checked bytes until the length of a first byte represented by the checked bytes is equal to the length of the checked bytes plus the length of a second byte, the length of the second byte is a fixed byte length from the beginning of the message without remark information to the length of the message, at the moment, the currently checked byte is considered as the length of the message, the message without remark information is extracted according to the position information, and quintuple information is extracted from the message without remark information according to the fixed position of a quintuple of the message; determining a target message receiving queue matched with the message to be processed from the N message receiving queues according to the extracted quintuple information; and adding the message to be processed to the target message receiving queue so that a CPU core corresponding to the target message receiving queue receives the message to be processed from the target message receiving queue for processing.
9. The apparatus of claim 8, further comprising a switch chip;
the switching chip includes: the first type Ethernet port is used for being connected with the Ethernet port of the FPGA, and the second type Ethernet ports are used for receiving and sending messages;
the switching chip is used for receiving an original message through any second type Ethernet port before the FPGA chip receives a message to be processed; adding remark information to the original message to obtain the message to be processed, wherein the remark information comprises a network port identifier of any one second type Ethernet port; and sending the message to be processed to the FPGA chip through the first type of Ethernet port.
10. The apparatus of claim 9, further comprising a network controller; the switch chip further comprises: the third type Ethernet port is used for being connected with the Ethernet port of the network controller; the network controller maintains N message sending queues; each message sending queue corresponds to one CPU core in the multi-core CPU;
any CPU core in the multi-core CPU is used for acquiring messages from the corresponding message receiving queue; processing the message, and determining a message to be sent according to a processing result; inserting the message to be sent into a message sending queue which is maintained by the network controller and corresponds to the CPU core;
the network controller is configured to send the message to be sent in the message sending queue to a third type ethernet port of the switch chip through an ethernet port;
the switch chip is further configured to send the message to be sent.
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