CN110489355B

CN110489355B - Mapping method and system of logic BRAM

Info

Publication number: CN110489355B
Application number: CN201910765532.7A
Authority: CN
Inventors: 余伟; 余建德
Original assignee: Shanghai Anlogic Information Technology Co ltd
Current assignee: Shanghai Anlu Information Technology Co.,Ltd.
Priority date: 2019-08-19
Filing date: 2019-08-19
Publication date: 2020-12-08
Anticipated expiration: 2039-08-19
Also published as: CN110489355A

Abstract

The application relates to the field of integrated circuits, and discloses a mapping method and a mapping system of a logic BRAM. The method comprises the following steps: determining a mapping area according to the logic BRAM to be mapped; acquiring all applicable types of ERAMs and sets of corresponding working modes thereof according to the mapping areas; and traversing the working modes in the set, and aiming at any traversed working mode: filling the ERAMs in the current working mode along the first direction and the second direction and not exceeding the mapping region, if filling one ERAM and exceeding the mapping region, filling only one ERAM in the direction, traversing and filling the remaining unfilled mapping region in a recursive manner until the area of the mapping region is 0 to obtain a filling result, and updating the optimal filling result according to the filling result; and after traversing, mapping the logic BRAM to be mapped according to the optimal result. According to the implementation mode of the application, the filling requirement of the mapping region of the logic BRAM is met, meanwhile, various types of ERAM resources can be fully and reasonably utilized, and the resource waste is reduced.

Description

Mapping method and system of logic BRAM

Technical Field

The present application relates to the field of integrated circuits, and more particularly, to mapping techniques for logical BRAMs.

Background

In the mapping process of the logic BRAM of the existing FPGA, one or more ERAMs are generally used for filling a single type of ERAM into the mapping area size of the logic BRAM.

However, there may be multiple types of ERAM resources in the FPGA, and when filling is performed only for a single type of ERAM, a filling failure may be caused because the number of any single type of ERAM remaining in the FPGA is not enough to complete filling of the mapping region of the logical BRAM; moreover, even if the number of remaining ERAMs of any single type in the FPGA is sufficient, the result of filling only for the ERAMs of the single type often causes a lot of resource waste.

Disclosure of Invention

The application aims to provide a mapping method and a mapping system of a logic BRAM (broadband remote access management), which can fully and reasonably utilize various types of ERAM (error rate access memory) resources and reduce resource waste while meeting the filling requirement of a mapping area of the logic BRAM.

The application discloses a mapping method of a logic BRAM, which comprises the following steps:

determining a mapping area in advance according to the address depth and the data width of the logic BRAM to be mapped;

acquiring sets of all types of ERAMs applicable to the FPGA and corresponding working modes thereof according to the determined mapping area;

traversing all the working modes in the set, and aiming at any traversed working mode: filling the mapping region along a first direction and a second direction by using an ERAM of a current working mode and not exceeding the mapping region, if filling one ERAM and also exceeding the mapping region, filling only one ERAM in the direction, and performing traversal filling on the remaining unfilled mapping region in a recursive manner until the area of the remaining unfilled mapping region is 0 to obtain a filling result corresponding to the current working mode, and comparing the filling result with an optimal filling result to update the optimal filling result;

and after the traversal is finished, mapping the logic BRAM to be mapped according to the optimal result.

In a preferred embodiment, the filling of the mapping region with ERAMs of the current operation mode in the first direction and the second direction without exceeding the mapping region, if filling an ERAM would also exceed the mapping region, filling only one ERAM in the direction, and performing traversal filling on the remaining unfilled mapping regions in a recursive manner until the area of the remaining unfilled mapping regions is 0, further includes:

filling the mapping area along a first direction and a second direction by using ERAMs of the current working mode without exceeding the mapping area, if filling one ERAM and exceeding the mapping area, filling only one ERAM in the direction to obtain a filling area, and updating the current set according to the rest ERAMs and the working modes thereof;

and segmenting the mapping region according to the shape boundary of the filling region to obtain at least one remaining mapping sub-region, and traversing the current set in a recursive manner to respectively complete filling of the at least one mapping sub-region if the area of the at least one mapping sub-region is not 0.

In a preferred embodiment, the mapping region is a square region, and the at least one mapping sub-region is the remaining 1 or 2 or 3 square regions obtained by dividing the mapping region according to the outline boundary of the filling region.

In a preferred embodiment, when the ERAM using the current operation mode fills the mapping region in the first direction and the second direction and does not exceed the mapping region, the method further includes:

and dynamically updating the remaining number of ERAMs in the set during the filling, if the ERAMs in the current working mode are exhausted and the current row or column is still not filled with the complete current row or column and is the first row or column, keeping the current row or column, and otherwise, removing the current row or column.

using the ERAM of the current working mode to fill the mapping region along the first row or column of the first direction until the residual data width or address depth of the row or column is smaller than the data width or address depth of the ERAM, and then filling the mapping region along the second direction row by row or column until the residual address depth or data width of the current mapping region is smaller than the address depth or data width of the ERAM;

wherein the first direction is a data width direction and the second direction is an address depth direction, or the first direction is an address depth direction and the second direction is a data width direction.

In a preferred embodiment, before traversing all the working modes in the set, the method further includes:

sorting all ERAMs in the set and corresponding working modes thereof from deep to shallow according to address depth; alternatively, the first and second electrodes may be,

and sorting all ERAMs in the set and the corresponding working modes thereof from large to small according to the data width.

In a preferred embodiment, the comparing the filling result corresponding to the current operating mode with the optimal filling result to update the optimal filling result further includes:

if the current working mode is the traversed first working mode, replacing the optimal filling result with the filling result corresponding to the current working mode;

otherwise, calculating a comprehensive evaluation value of the filling result corresponding to the current working mode according to the quantity index containing ERAM and the waste ERAM area index, and comparing the comprehensive evaluation value with the comprehensive evaluation value of the current optimal filling result;

and if the comprehensive evaluation value of the filling result is greater than that of the current optimal filling result, replacing the optimal filling result with the filling result corresponding to the current working mode to update the optimal filling result, and otherwise, keeping the current optimal filling result.

The application also discloses a mapping system of the logic BRAM, which comprises:

the acquisition module is used for determining a mapping area in advance according to the address depth and the data width of the logic BRAM to be mapped and acquiring all types of ERAMs applicable to the FPGA and a set of corresponding working modes thereof according to the determined mapping area;

a traversing module, configured to traverse all the working modes in the set, and for any traversed working mode: filling the mapping region along a first direction and a second direction by using an ERAM of a current working mode and not exceeding the mapping region, if filling one ERAM and also exceeding the mapping region, filling only one ERAM in the direction, and performing traversal filling on the remaining unfilled mapping region in a recursive manner until the area of the remaining unfilled mapping region is 0 to obtain a filling result corresponding to the current working mode, and comparing the filling result with an optimal filling result to update the optimal filling result;

and the mapping module is used for mapping the logic BRAM to be mapped according to the optimal filling result after the traversal is finished.

a memory for storing computer executable instructions; and the number of the first and second groups,

a processor for implementing the steps in the method as described hereinbefore when executing the computer-executable instructions.

The present application also discloses a computer-readable storage medium having stored therein computer-executable instructions which, when executed by a processor, implement the steps in the method as described above.

In the embodiment of the application, a mapping area is determined in advance according to the address depth and the data width of the logic BRAM to be mapped, all types of ERAMs applicable to the FPGA and sets of corresponding working modes of the ERAMs are obtained according to the determined mapping area, and the mapping area is filled based on multiple types of ERAM resources. The method avoids the problem of filling failure caused by the fact that the quantity of any remaining single type of ERAMs in the FPGA is not enough to complete filling of the mapping region of the logic BRAM in the prior art, simultaneously makes up for resource waste caused by filling only aiming at the single type of ERAMs in the prior art, can fully and reasonably utilize multiple types of ERAMs while meeting the filling requirement of the mapping region of the logic BRAM, and reduces resource waste.

Furthermore, the filling process of the ERAM resources can be optimized under different filling scenes, and waste of the ERAM resources is reduced. For example, when the ratio of the depth to the width of the mapping area of the logical BRAM to be mapped is large, all types of ERAMs and corresponding working modes thereof in the set may be sorted according to the address depth of the ERAMs from deep to shallow, and the working modes in the set are traversed based on the sorting result to perform filling work, so that the filling efficiency may be improved. Further, when traversing the set, for any traversed working mode, filling the mapping region in the first direction and the second direction by using the ERAM of the current working mode without exceeding the mapping region, and performing traversal filling on the remaining unfilled mapping regions in a recursive manner until the area of the remaining unfilled mapping regions is 0, thereby optimizing the traversal filling process to the maximum extent.

Further, the higher comprehensive evaluation value is selected as the optimal filling result in consideration of combining the number of consumed ERAMs and the area of wasted ERAMs, which helps to reasonably distribute ERAMs in most circuit scenarios.

The present specification describes a number of technical features distributed throughout the various technical aspects, and if all possible combinations of technical features (i.e. technical aspects) of the present specification are listed, the description is made excessively long. In order to avoid this problem, the respective technical features disclosed in the above summary of the invention of the present application, the respective technical features disclosed in the following embodiments and examples, and the respective technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (which are considered to have been described in the present specification) unless such a combination of the technical features is technically infeasible. For example, in one example, the feature a + B + C is disclosed, in another example, the feature a + B + D + E is disclosed, and the features C and D are equivalent technical means for the same purpose, and technically only one feature is used, but not simultaneously employed, and the feature E can be technically combined with the feature C, then the solution of a + B + C + D should not be considered as being described because the technology is not feasible, and the solution of a + B + C + E should be considered as being described.

Drawings

Fig. 1 is a schematic flow chart of a mapping method of a logical BRAM according to a first embodiment of the present application

Fig. 2 is a schematic diagram of a mapping region of an exemplary logical BRAM to be mapped according to the first embodiment of the present application

FIG. 3 is a filling state diagram for filling the mapping region in the first direction and the second direction using ERAM of the current operation mode according to the first embodiment of the present application

FIG. 4 is a schematic view of a fill area in one instance according to a first embodiment of the present application

FIG. 5 is a schematic view of a fill area in another situation in accordance with the first embodiment of the present application

FIG. 6 is a schematic view of a fill area in another situation in accordance with the first embodiment of the present application

FIG. 7(a) is a schematic view of a filling region in another case according to the first embodiment of the present application

FIG. 7(b) is a schematic view of a filling region in another case according to the first embodiment of the present application

Fig. 8 is a schematic diagram of the remaining 1 square region obtained by slicing the mapping region based on the filling region shown in fig. 7(a) according to the first embodiment of the present application

FIG. 9 is a schematic diagram of the remaining 2 square regions obtained by splitting the mapping region based on the filling region shown in FIG. 6 according to the first embodiment of the present application

FIG. 10 is a flowchart illustrating an example of traversing all the working modes in the set to fill the mapping region to obtain an optimal filling result according to step 103 of the first embodiment of the present application;

fig. 11 is a schematic diagram of a mapping system structure of a logical BRAM according to a second embodiment of the present application

Detailed Description

In the following description, numerous technical details are set forth in order to provide a better understanding of the present application. However, it will be understood by those skilled in the art that the technical solutions claimed in the present application may be implemented without these technical details and with various changes and modifications based on the following embodiments.

Description of partial concepts:

FPGA: field Programmable Gate Array, Field Programmable logic Array. The circuit is used as a semi-custom circuit in the field of application-specific integrated circuits, not only overcomes the defects of a full-custom circuit, but also overcomes the defect that the number of gate circuits of the original programmable logic device is limited.

ERAM: embedded Random Access Memory. A hardware storage resource customized in the FPGA has a fixed size and can be randomly accessed according to an address and a clock.

BRAM: block Random Access Memory. The random access memory built by the ERAM is generally expressed by a logic BRAM and a physical BRAM, wherein the logic BRAM represents the random access memory customized by a user according to circuit requirements, and the physical BRAM represents a physical resource in the FPGA, namely the ERAM.

Mapping: the circuit design is mapped into a process expressed in the form of FPGA hardware resources, and the logical BRAM is mapped to the ERAM, namely, the Mapping process is part of.

HBM: hetero BRAM Mapping, a method for Mapping using various types of ERAMs.

Partition: in the mapping process of the logic BRAM, the logic BRAM is generally required to be segmented, and then each segmented small block is mapped into different ERAMs, and the process of segmenting all types of logic BRAMs is called Partition. "filling" referred to in this application is the inverse operation process corresponding to "slicing".

Working Mode: and (4) working modes. ERAMs often have multiple operating modes, such as single-port or dual-port modes, multiple bit widths and address depths, and the like.

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

The first embodiment of the present application relates to a mapping method of a logical BRAM, as shown in a flowchart in fig. 1, the method includes the following steps 101 to 104:

initially, in step 101: determining a mapping area in advance according to the address depth and the data width of the logic BRAM to be mapped;

then, step 102 is carried out, and a set of ERAMs of all types and corresponding working modes applicable to the FPGA is obtained according to the determined mapping area;

then, step 103 is performed: traversing all the working modes in the set, and aiming at any traversed working mode: filling the mapping region along a first direction and a second direction by using an ERAM of a current working mode and not exceeding the mapping region, if filling one ERAM and also exceeding the mapping region, filling only one ERAM in the direction, and performing traversal filling on the remaining unfilled mapping region in a recursive manner until the area of the remaining unfilled mapping region is 0 to obtain a filling result corresponding to the current working mode, and comparing the filling result with an optimal filling result to update the optimal filling result;

then, step 104 is performed: and after the traversal is finished, mapping the logic BRAM to be mapped according to the optimal result.

The following steps are described in detail:

firstly, in step 101, a mapping area is determined in advance according to the address depth and the data width of the logical BRAM to be mapped.

Optionally, in the step 101, the mapping area is a square area, wherein one side of the square area may correspond to a data width of the logic BRAM to be mapped, and another side of the square area may correspond to an address depth of the logic BRAM to be mapped. For example, fig. 2 shows a mapping region diagram of an exemplary logical BRAM to be mapped.

Secondly, in step 102, a set of ERAMs of all types and corresponding operating modes applicable in the FPGA is obtained according to the determined mapping region.

Specifically, there are various types of ERAMs in the FPGA, and for example, the ERAMs may include an ERAM with a capacity of 9K, an ERAM with a capacity of 32K, and the like. Moreover, each type of ERAM generally has multiple operation modes, for example, the operation mode of an ERAM with a capacity of 9K may include 1kx9, 2kx4, 4kx2, 8kx1, etc., and the operation mode of an ERAM with a capacity of 32K may include 1kx32,2kx16, 4kx4,8kx2, etc. Not all of the modes of operation of all types of ERAMs are suitable for filling the mapping region, e.g., a certain mode of operation of a certain type of ERAM has a data width much larger than the width of the mapping region. Therefore, in step 102, the applicable ERAMs may be selected according to the characteristics (e.g., ratio of data width to address depth, single or double port, etc.) of the logical BRAM to be mapped, so as to determine the set of all types of ERAMs and their corresponding operation modes that are applicable. The specific selection of which is not within the scope of the present discussion.

Then, in step 103, all the working modes in the set are traversed, and for any traversed working mode: filling the mapping region along a first direction and a second direction by using ERAMs of a current working mode and not exceeding the mapping region, if filling one ERAM and also exceeding the mapping region, filling only one ERAM in the direction, and performing traversal filling on the remaining unfilled mapping region in a recursive manner until the area of the remaining unfilled mapping region is 0, obtaining a filling result corresponding to the current working mode, and comparing the filling result with an optimal filling result to update the optimal filling result.

Optionally, traversing all the working modes in the set, performing filling of the ERAM for any traversed working mode to obtain an optimal filling result, and then performing filling of the traversed next working mode, wherein all the types of ERAMs and the corresponding working modes applicable in the set need to be recovered before performing filling of the next working mode.

In step 103, "filling the mapping region with ERAMs of the current operating mode in the first direction and the second direction without exceeding the mapping region, if filling an ERAM would also exceed the mapping region, filling only one ERAM in the direction, and performing traversal filling on the remaining unfilled mapping regions in a recursive manner until the area of the remaining unfilled mapping regions is 0" may further include the following sub-steps a and B:

in the substep A, using ERAMs of the current working mode to fill the mapping region along a first direction and a second direction without exceeding the mapping region, if filling an ERAM and exceeding the mapping region, filling only one ERAM in the direction to obtain a filling region and updating the current set according to the remaining ERAMs and the working modes thereof;

and then performing a substep B, segmenting the mapping region according to the outline boundary of the filling region to obtain at least one remaining mapping sub-region, and traversing the current set in a recursive manner to respectively complete the filling of the at least one mapping sub-region if the area of the at least one mapping sub-region is not 0.

In addition, there are various setting methods of the first direction and the second direction in step 103. Alternatively, the first direction may be a data width direction and the second direction is an address depth direction. Alternatively, the first direction may be an address depth direction and the second direction is a data width direction.

Further, corresponding to the above-mentioned various setting manners of the first direction and the second direction, there are various implementation manners of "filling the mapping region in the first direction and the second direction without exceeding the mapping region using the ERAM of the current operation mode" in step 103. In one embodiment, the first direction is a data width direction and the second direction is an address depth direction, then this is accomplished by: and filling the mapping region by using the ERAM of the current working mode along the first row in the data width direction until the residual data width of the row is smaller than the data width of the ERAM, and filling the mapping region row by row in the address depth direction until the residual address depth of the current mapping region is smaller than the address depth of the ERAM. In another embodiment, the first direction is an address depth direction and the second direction is a data width direction, then the implementation is: and filling the mapping region by using the ERAM of the current working mode along the first row in the address depth direction until the residual address depth of the row is less than the address depth of the ERAM, and filling the mapping region along the data width direction row by row until the residual data width of the current mapping region is less than the data width of the ERAM.

Optionally, in the sub-step a, "filling the mapping region in the first direction and the second direction using the ERAM of the current operation mode without exceeding the mapping region" may further include the following steps:

the remaining number of ERAMs in the set for the current mode of operation is dynamically updated during fill, if the ERAMs are exhausted and the current row or column is not filled completely and the current row or column is the first row or column, the current row or column is retained, otherwise the current row or column is removed.

In order to better understand the process of "filling the mapping region in the first direction and the second direction using ERAM of the current operation mode" in step 103, the following description is given. In this example, the mapping region diagram of the logical BRAM to be mapped is shown in fig. 2, all the working modes in the set are traversed to obtain an ERAM of the current working mode, the logical BRAM is filled from 0 address and 0 data of the mapping region shown in fig. 2 by using the ERAM, the first row in the data width direction is filled to the right until the width of the mapping region is about to exceed, as shown in fig. 3, and then the filling region is filled row by row in the address depth direction. Among them, there may be the following cases during the filling process: for example, fig. 4 shows the fill area schematic in the case where the number of current operating modes is sufficient; or, if it is found that the ERAM resource of the current working mode is exhausted after a certain filling (for example, the remaining number of ERAMs is dynamically updated in the filling process), but the complete current row is not filled yet, the last row is removed, as shown in fig. 5; or, if the ERAM resource of the current working mode is found to be exhausted after a certain filling, but the complete current row is not filled yet and the current row is just the first row, the row is still retained, as shown in fig. 6; alternatively, if even one ERAM exceeds the boundary in the width or depth direction, one remains in that direction, as shown in fig. 7(a) and (b). It should be noted that the details listed in this example are provided primarily for ease of understanding and are not intended to limit the scope of the present application.

Optionally, the at least one mapping sub-region in the sub-step B is the remaining 1 or 2 or 3 square regions obtained by dividing the mapping region according to the outline boundary of the filling region. For example, slicing the map region for the outline boundaries of the fill region of fig. 7(a) may result in 1 square region of the first map subregion as shown in fig. 8. Alternatively, slicing the map region for the outline boundaries of the fill region shown in fig. 6 may result in 2 square regions of the first map subregion and the second map subregion as shown in fig. 9.

Optionally, the step 103 of "traversing all the working modes in the set" may further include: all ERAMs in the set and their corresponding operating modes are ordered. In one embodiment, all ERAMs and their corresponding working modes in the set may be sorted from deep to shallow according to the address depth, and all working modes in the set may be sequentially traversed according to the sorting result. In another embodiment, all ERAMs and their corresponding working modes in the set may be sorted from large to small according to the data width, and all working modes in the set may be sequentially traversed according to the sorting result. Traversing all the working modes in the set in sequence according to the sequencing result can improve the traversing efficiency.

Optionally, in a recursive process of "recursively filling the remaining unfilled mapping regions until the area of the remaining unfilled mapping regions is 0" in step 103, the set traversed by the current recursive layer is dynamically updated according to the filling result of the last recursive layer, that is, ERAM used by the last recursive layer filling is deleted from the current set to update the set traversed by the current recursive layer.

Optionally, the step 103 of "comparing the filling result corresponding to the current operation mode with the optimal filling result to update the optimal filling result" may further include the following sub-steps a and b:

in the substep a, if the current working mode is the traversed first working mode, replacing the optimal filling result with the filling result corresponding to the current working mode, otherwise, calculating the comprehensive evaluation value of the filling result corresponding to the current working mode according to the indexes including ERAM quantity and waste ERAM area, and comparing the comprehensive evaluation value with the comprehensive evaluation value of the current optimal filling result;

and then, performing the substep b, if the comprehensive evaluation value of the filling result corresponding to the current working mode is greater than the comprehensive evaluation value of the current optimal filling result, replacing the optimal filling result with the filling result corresponding to the current working mode to update the optimal filling result, and otherwise, keeping the current optimal filling result.

The comprehensive evaluation value is calculated according to the indexes including the ERAM quantity and the waste ERAM area, and the specific calculation methods are various. Alternatively, the overall evaluation value ═ - (including an ERAM quantity index and a waste ERAM area index). Optionally, -a total evaluation value comprising a weighted sum of an ERAM quantity indicator and a wasted ERAM area indicator. And so on.

Fig. 10 is a flowchart illustrating an embodiment of traversing all the working modes in the set to fill the mapping region to obtain an optimal filling result in step 103. The embodiment specifically comprises the following steps 1001-1010:

starting step 1001, filling the mapping region by using the traversed ERAMs of the current operating mode first along the first row in the data width direction and then along the address depth direction row by row without exceeding the mapping region, and if filling one ERAM would exceed the mapping region, filling only one ERAM in the direction to obtain a filling region.

Then step 1002 is entered, the mapping region is segmented according to the outline boundary of the filling region to obtain at least one remaining mapping sub-region.

Then, the process proceeds to step 1003, where it is determined: is there an area in the at least one mapping sub-region other than 0? If yes, then entering step 1004, and completing the filling of the mapping sub-regions with the areas not being 0 respectively in a recursive manner until whether the area of at least one mapping sub-region is 0, and obtaining a filling result corresponding to the current working mode; otherwise step 1005 is followed.

Proceeding to step 1005 after step 1004, determine: is the current operating mode the first operating mode traversed? If yes, go to step 1006, replace the optimal filling result with the filling result corresponding to the current working mode; otherwise, go to step 1007, compare the filling result corresponding to the current operating mode with the optimal filling result to update the optimal filling result.

After step 1006 or step 1007, step 1008 is entered, and it is determined that: is the traversal complete? If the traversal is finished, entering step 1009 to obtain an optimal filling result; otherwise, step 1010 is entered, after the working mode is changed, step 1001 is returned to and the steps are repeated until the traversal is finished, and the optimal filling result is obtained, wherein after the working mode is changed, all the working modes in the set need to be recovered.

Finally, in step 104, after the traversal of step 103 is finished, the logic BRAM to be mapped is mapped according to the optimal result.

The second embodiment of the present application relates to a mapping system of a logical BRAM, whose structure is shown in fig. 11, and the mapping system of the logical BRAM includes an obtaining module, a traversing module, and a mapping module. The following is specifically described:

the obtaining module is used for determining a mapping area in advance according to the address depth and the data width of the logic BRAM to be mapped, and obtaining all types of ERAMs applicable to the FPGA and sets of corresponding working modes of the ERAMs according to the determined mapping area.

Optionally, the mapping area is a square area, wherein one side of the square area may correspond to a data width of the logical BRAM to be mapped, and another side of the square area may correspond to an address depth of the logical BRAM to be mapped.

Optionally, the obtaining module is further configured to select an applicable ERAM according to characteristics (e.g., a ratio of a data width to an address depth, a single port, a double port, and the like) of the logical BRAM to be mapped, so as to determine a set of all types of ERAMs applicable and corresponding operating modes thereof.

Optionally, the mapping system of the logical BRAM further includes a sorting module, configured to sort all ERAMs in the set and their corresponding operating modes. In one embodiment, the sorting module is configured to sort all ERAMs in the set and corresponding working modes thereof from deep to shallow according to address depths, and sequentially traverse all working modes in the set according to the sorting result. In another embodiment, the sorting module is configured to sort all ERAMs in the set and corresponding working modes thereof from large to small according to data width, and sequentially traverse all working modes in the set according to the sorting result.

Further, the traversing module is configured to traverse all the working modes in the set, and for any traversed working mode: filling the mapping region along a first direction and a second direction by using ERAMs of a current working mode and not exceeding the mapping region, if filling one ERAM and also exceeding the mapping region, filling only one ERAM in the direction, and performing traversal filling on the remaining unfilled mapping region in a recursive manner until the area of the remaining unfilled mapping region is 0, obtaining a filling result corresponding to the current working mode, and comparing the filling result with an optimal filling result to update the optimal filling result.

Optionally, the traversing module is further configured to fill the mapping region along the first direction and the second direction using an ERAM in the current working mode without exceeding the mapping region, if one ERAM is filled and may also exceed the mapping region, fill only one ERAM in the direction to obtain a filled region, update the current set according to the remaining ERAMs and the working modes thereof, divide the mapping region according to the outer boundary of the filled region to obtain at least one remaining mapping sub-region, and if the area of the at least one mapping sub-region is not 0, traverse the current set in a recursive manner to respectively complete filling of the at least one mapping sub-region.

Optionally, the at least one mapping sub-region is the remaining 1, 2 or 3 square regions obtained by dividing the mapping region according to the outline boundary of the filling region.

Alternatively, the first direction and the second direction may be set in various ways. Alternatively, the first direction may be a data width direction and the second direction is an address depth direction. Alternatively, the first direction may be an address depth direction and the second direction is a data width direction.

Optionally, the traversal module is further configured to start filling the mapping region with the ERAM in the current operating mode along a first row in the data width direction until a remaining data width of the row is smaller than a data width of the ERAM, and then fill the mapping region row by row along the address depth direction until a remaining address depth of the current mapping region is smaller than the address depth of the ERAM, where the first direction is the data width direction and the second direction is the address depth direction. Or, the traversal module is further configured to start filling a first column of the mapping region in an address depth direction until a remaining address depth of the column is smaller than the address depth of the ERAM by using the ERAM in the current working mode, and then fill the mapping region in a data width direction column by column until a remaining data width of the current mapping region is smaller than the data width of the ERAM, where the first direction is an address depth direction and the second direction is a data width direction.

Optionally, the traversal module is further configured to dynamically update the remaining number of ERAMs in the set for the current operating mode during filling, and if the ERAMs are exhausted and the current row or column is still not filled with the full current row or column and the current row or column is the first row or column, the current row or column is retained, otherwise, the current row or column is removed.

Optionally, the traversal module is further configured to replace the optimal filling result with the filling result corresponding to the current working mode if the current working mode is the traversed first working mode, otherwise, calculate a comprehensive evaluation value of the filling result corresponding to the current working mode according to an indicator including an ERAM quantity and an ERAM area wasted indicator, compare the comprehensive evaluation value with the comprehensive evaluation value of the current optimal filling result, replace the optimal filling result with the filling result corresponding to the current working mode to update the optimal filling result if the comprehensive evaluation value of the filling result corresponding to the current working mode is greater than the comprehensive evaluation value of the current optimal filling result, and otherwise, retain the current optimal filling result.

The comprehensive evaluation value is calculated according to the indexes including the ERAM quantity and the waste ERAM area, and the specific calculation methods are various. Alternatively, the overall evaluation value ═ - (including an ERAM quantity index and a waste ERAM area index). Optionally, -a composite evaluation value being a weighted sum value containing an ERAM quantity indicator and a wasted ERAM area indicator; and so on.

Further, the mapping module is used for mapping the logic BRAM to be mapped according to the optimal filling result after the traversal of the traversal module is finished. Optionally, the mapping module is further configured to perform net connection on all the ERAMs obtained by mapping, including address, clock, data input and output, and the like.

The first embodiment is a method embodiment corresponding to the present embodiment, and the technical details in the first embodiment may be applied to the present embodiment, and the technical details in the present embodiment may also be applied to the first embodiment.

It should be noted that, as will be understood by those skilled in the art, the implementation functions of the modules shown in the foregoing embodiment of the mapping system of the logical BRAM may be understood by referring to the foregoing description of the mapping method of the logical BRAM. The functions of the modules shown in the embodiment of the mapping system of the logic BRAM can be realized by a program (executable instruction) running on a processor, and can also be realized by a specific logic circuit. The mapping system of the logic BRAM in the embodiment of the present application, if implemented in the form of a software functional module and sold or used as an independent product, may also be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially implemented or portions thereof contributing to the prior art may be embodied in the form of a software product stored in a storage medium, and including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read Only Memory (ROM), a magnetic disk, or an optical disk. Thus, embodiments of the present application are not limited to any specific combination of hardware and software.

Accordingly, the present application also provides a computer-readable storage medium, in which computer-executable instructions are stored, and when the computer-executable instructions are executed by a processor, the computer-executable instructions implement the method embodiments of the present application. Computer-readable storage media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable storage medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.

In addition, the embodiment of the application also provides a mapping system of the logic BRAM, which comprises a memory for storing computer executable instructions and a processor; the processor is configured to implement the steps of the method embodiments described above when executing the computer-executable instructions in the memory. The Processor may be a Central Processing Unit (CPU), other general-purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), or the like. The aforementioned memory may be a read-only memory (ROM), a Random Access Memory (RAM), a Flash memory (Flash), a hard disk, or a solid state disk. The steps of the method disclosed in the embodiments of the present invention may be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules in the processor.

It is noted that, in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the use of the verb "comprise a" to define an element does not exclude the presence of another, same element in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that a certain action is executed according to a certain element, it means that the action is executed according to at least the element, and two cases are included: performing the action based only on the element, and performing the action based on the element and other elements. The expression of a plurality of, a plurality of and the like includes 2,2 and more than 2, more than 2 and more than 2.

All documents mentioned in this application are to be considered as being incorporated in their entirety into the disclosure of this application so as to be subject to modification as necessary. It should be understood that the above description is only a preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of the present disclosure should be included in the scope of protection of one or more embodiments of the present disclosure.

Claims

1. A mapping method of a logic BRAM is characterized by comprising the following steps:

and after the traversal is finished, mapping the logic BRAM to be mapped according to the optimal filling result.

2. The method for mapping of a logical BRAM according to claim 1, wherein the ERAM using the current operation mode fills the mapping region in the first direction and the second direction without exceeding the mapping region, if filling an ERAM would also exceed the mapping region, only one ERAM is filled in the direction, and the remaining unfilled mapping regions are recursively filled until the area of the remaining unfilled mapping regions is 0, further comprising:

3. The mapping method of the logic BRAM according to claim 2, wherein the mapping region is a square region, and the at least one mapping sub-region is the remaining 1 or 2 or 3 square regions obtained by dividing the mapping region according to the outline boundary of the filling region.

4. The method for mapping of logical BRAM according to claim 2, wherein when the ERAM using the current operation mode fills the mapping area in the first direction and the second direction without exceeding the mapping area, further comprising:

and dynamically updating the residual quantity of the ERAMs in the set during filling, if the ERAMs in the current working mode are exhausted and the current row or column is not filled completely and is the first row or column, keeping the current row or column, and otherwise, removing the current row or column.

5. The method for mapping of logical BRAM of claim 2, wherein the filling the mapping area in a first direction and a second direction using ERAM of a current operating mode without exceeding the mapping area further comprises:

6. The method for mapping of a logical BRAM according to claim 1 or 2, wherein before traversing all working modes in the set, further comprising:

7. The method for mapping of the logic BRAM according to claim 1 or 2, wherein the comparing the filling result corresponding to the current operation mode with the optimal filling result to update the optimal filling result, further comprises:

8. A mapping system for a logical BRAM, comprising:

9. A mapping system for a logical BRAM, comprising:

a processor for implementing the steps in the method of any one of claims 1 to 7 when executing the computer-executable instructions.

10. A computer-readable storage medium having stored thereon computer-executable instructions which, when executed by a processor, implement the steps in the method of any one of claims 1 to 7.