CN110416161A - Semiconductor devices and preparation method thereof - Google Patents
Semiconductor devices and preparation method thereof Download PDFInfo
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- CN110416161A CN110416161A CN201810399608.4A CN201810399608A CN110416161A CN 110416161 A CN110416161 A CN 110416161A CN 201810399608 A CN201810399608 A CN 201810399608A CN 110416161 A CN110416161 A CN 110416161A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000002360 preparation method Methods 0.000 title description 4
- 238000009413 insulation Methods 0.000 claims abstract description 161
- 239000000758 substrate Substances 0.000 claims abstract description 101
- 238000005530 etching Methods 0.000 claims abstract description 50
- 238000000137 annealing Methods 0.000 claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 claims abstract description 29
- 239000010410 layer Substances 0.000 claims description 181
- 239000000463 material Substances 0.000 claims description 70
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 20
- 239000011241 protective layer Substances 0.000 claims description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 9
- 239000000126 substance Substances 0.000 claims description 9
- 239000007792 gaseous phase Substances 0.000 claims description 7
- 238000011049 filling Methods 0.000 claims description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 25
- 229910052814 silicon oxide Inorganic materials 0.000 description 16
- 150000002500 ions Chemical class 0.000 description 10
- 238000002955 isolation Methods 0.000 description 6
- 230000005012 migration Effects 0.000 description 6
- 238000013508 migration Methods 0.000 description 6
- 208000027418 Wounds and injury Diseases 0.000 description 4
- 230000006378 damage Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000000835 fiber Substances 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 230000006835 compression Effects 0.000 description 3
- 238000007906 compression Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 208000014674 injury Diseases 0.000 description 3
- 238000006467 substitution reaction Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000007795 chemical reaction product Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Abstract
A kind of semiconductor devices and forming method thereof, wherein the production method of semiconductor devices include: provide include first area and second area substrate, be respectively formed with grid on the substrate of the first area and second area；Form insulation stress layer；Etching removal is located at the insulation stress layer on the substrate of first area and on top portions of gates；The insulation stress layer of the second area is made annealing treatment；The first area substrate exposed described in etching forms first groove；Form the first stressor layers；Etching is located at the insulation stress layer on the second area substrate and on top portions of gates.This invention simplifies processing steps, improve the performance of semiconductor devices.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, in particular to a kind of semiconductor devices and preparation method thereof.
Background technique
In recent years, Metal-oxide-semicondutor (MOS, Metal-Oxide-Semiconductor) field effect transistor
And its ratio that integrated circuit accounts in semiconductor devices and circuit is increasing, the advantages of MOS device is that speed is fast, volume
It is small, convenient for integrated.The performance of MOS device depends on carrier mobility, the saturated velocity of carrier, gate voltage pair in channel
The factors such as the modulation efficiency of channel carrier and device size.
Common MOS device includes NMOS device and PMOS device, and the majority carrier of NMOS device is electronics, PMOS device
The majority carrier of part is hole.In order to improve the carrier mobility of MOS device, stress migration (SM, Stress are generallyd use
Migration) technology, specifically, forming stressor layers on substrate and grid；Then annealing process is carried out to stressor layers, made
It obtains grid and issues the enhancing of channel region internal stress, to improve carrier mobility.
However, the prior art forms the complex process of semiconductor devices and production efficiency is low.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor devices and preparation method thereof, simplifies processing step, avoids carving
Deteriorate wound, improves the performance of semiconductor devices.
To solve the above problems, the present invention provides a kind of production method of semiconductor devices, comprising:
The substrate including first area and second area is provided, the type of the first area is NMOS area or PMOS
Region, the type of the second area are NMOS area or PMOS area, and the type of the first area and second area
Grid is respectively formed on the substrate of difference, the first area and second area；In the top portions of gates and side wall, Yi Jisuo
State formation insulation stress layer on substrate；Etching removal is located at the insulation stress layer on the substrate of first area and on top portions of gates,
The first area substrate surface is exposed, the gate lateral wall in the first area forms the first insulation stress side wall；In shape
After the first insulation stress side wall, the insulation stress layer of the second area is made annealing treatment；It etches described sudden and violent
The first area substrate of exposing, forms first groove in the substrate of first area grid two sides；It is full described to form filling
First stressor layers of first groove；Etching is located at the insulation stress layer on the second area substrate and on top portions of gates, cruelly
Expose the second area substrate surface, forms the second insulation stress side wall in the gate lateral wall of the second area.
Optionally, the first area is PMOS area, and the material of the insulation stress layer is tensile stress material.
Optionally, the tensile stress material is silicon nitride.
Optionally, the insulation stress layer with a thickness of 200-300A.
Optionally, the insulation stress layer is formed using chemical gaseous phase deposition technique.
Optionally, the material of first stressor layers includes SiGe.
Optionally, the first area is NMOS area, and the material of the insulation stress layer is compressive stressed materials.
Optionally, it is initially formed the first groove, carries out the annealing afterwards.
Optionally, before carrying out the annealing, first stressor layers are formed.
Optionally, the annealing temperature used that makes annealing treatment is 1000 DEG C~1200 DEG C.
Optionally, after carrying out the annealing, first stressor layers are formed.
Optionally, it after carrying out the annealing, is formed before first stressor layers, further includes: to described the
One groove starts the cleaning processing.
Optionally, the annealing is first carried out, forms the first groove afterwards.
Optionally, before forming the insulation stress layer, further includes: in the first area, the substrate of second area
Surface and the top portions of gates and sidewall surfaces form protective layer, the material of the material of the protective layer and the insulation stress layer
Material is different.
Optionally, the material of the protective layer includes silica.
Optionally, before the insulation stress layer that etching removal is located on the substrate of first area and on top portions of gates, the
The insulation stress layer surface in two regions forms photoresist layer；Using the photoresist layer as exposure mask；It is located at described the in etching removal
After insulation stress layer on one area substrate and on top portions of gates, the photoresist layer is removed.
Optionally, the removal of using plasma etching technics etching is located on the substrate of first area and on top portions of gates
Insulation stress layer.
The present invention also provides a kind of semiconductor devices, comprising: the substrate including first area and second area, described first
The type in region is that the type of the NMOS area perhaps PMOS area second area is NMOS area or PMOS area, and
The first area is different from the type of second area, has grid on the substrate of the first area and second area；It is located at
First insulation stress side wall of the gate lateral wall of first area；First groove in the substrate of first area grid two sides；
Fill the first stressor layers of the full first groove；Positioned at the second insulation stress side wall of the gate lateral wall of second area.
Optionally, the first area is PMOS area, and the material of the first insulation stress side wall is tensile stress material
Material.
Optionally, the first area is NMOS area, and the material of the first insulation stress side wall is compression stress material
Material.
Compared with prior art, technical solution of the present invention has the advantage that
In the technical solution of the production method of semiconductor devices provided by the invention, first in top portions of gates and side wall and lining
Insulation stress layer is formed on bottom, the insulation stress layer is subsequent to provide stress to the channel region below second area grid；
And also etching removal is located at the insulation stress layer on the substrate of first area and on top portions of gates, the gate lateral wall in first area
The first insulation stress side wall is formed, the first insulation stress side wall provides Process ba- sis to be subsequently formed first groove；In shape
After the first insulation stress side wall, the insulation stress layer of second area is made annealing treatment, so that in insulation stress layer
In channel region below stress migration to second area grid, second area grid underlying channel region internal stress is improved；And in shape
After the first insulation stress side wall, first groove is formed in the substrate of first area grid two sides；Form filling full first
First stressor layers of groove；Etching is located at the insulation stress layer on the second area substrate and on top portions of gates, described
The gate lateral wall of second area forms the second insulation stress side wall.Use insulation stress layer substitution original to form the first insulation sides
Side wall layer needed for wall and the second insulation side wall, forms the first insulation stress side wall and the second insulation stress using insulation stress layer
Side wall, therefore in the technical process for forming the first insulation stress side wall and the second insulation stress side wall, etching eliminates substrate
The insulation stress layer of surface and top portions of gates, thus, it is subsequent after an annealing treatment, without carry out for etching removal substrate on
Insulation stress layer and the etching technics that uses, to simplify processing step, and avoid etching technics bring etching damage
Hurt problem, improves the electric property of the semiconductor devices of formation.
In optinal plan, first area is PMOS area, so that the stress migration in insulation stress layer is to NMOS area grid
In channel region below pole, NMOS area grid underlying channel region internal stress is improved；The material of the insulation stress layer is adopted as
Silicon nitride plays the role of protection and stress release to gate lateral wall；It is initially formed the first groove, is subsequent growth the
One stressor layers provide Process ba- sis, carry out the annealing afterwards.
It in optinal plan, can also be initially formed after the first groove, and after carrying out the annealing, be formed
First stressor layers, have haved the function that stress migration.Simplify processing step.
Detailed description of the invention
Fig. 1 to Fig. 7 is the corresponding the schematic diagram of the section structure of each step of manufacturing method of semiconductor device provided by the invention.
Specific embodiment
It can be seen from background technology that the formation process of semiconductor devices is complicated in the prior art.
It is analyzed now in conjunction with process for fabrication of semiconductor device.The processing step for forming semiconductor devices includes: offer packet
The substrate of PMOS area and NMOS area is included, is formed with grid on the substrate；In the top portions of gates and side wall and substrate
Upper formation mask layer；Mask layer on etching removal PMOS area top portions of gates and substrate, in the PMOS area gate electrode side
It forms the first side wall on wall, and etches the substrate of PMOS area grid two sides, form the in the PMOS area substrate
The step of one groove, the first side wall of formation and first groove, may be simply referred to as PSR technique；It is formed and fills the full first groove
First stressor layers；Mask layer on etching removal NMOS area top portions of gates and substrate, in the NMOS area gate lateral wall
The second side wall of upper formation, and the substrate of NMOS area grid two sides is etched, second is formed in the NMOS area substrate
The step of groove, the second side wall of formation and second groove, may be simply referred to as NSR technique；It is formed and fills the of the full first groove
Two stressor layers；In order to improve stress effect, formed on the top portions of gates and side wall and the substrate of the NMOS area exhausted
Fiber stress layer；The insulation stress layer of the NMOS area is made annealing treatment；Etching removes the insulation stress layer.
So being made annealing treatment to the insulation stress layer of NMOS area, etching is gone after PSR technique and NSR technique
Except the insulation stress layer on substrate.Therefore, above-mentioned processing step is complicated, low efficiency, and etches the insulation stress on removal substrate
The etching technics of layer be easy to cause etching injury problem, and the electric property of semiconductor devices is caused to be affected.
To solve the above problems, the present invention provides a kind of production method of semiconductor devices, by elder generation in top portions of gates and
Form insulation stress layer on side wall and substrate, the insulation stress layer forms the first of the gate lateral wall for being located at first area absolutely
Second insulation stress side wall of fiber stress side wall and the gate lateral wall positioned at second area, use insulation stress layer substitution it is original for
Side wall layer needed for forming the first insulation side wall and the second insulation side wall, simplifies processing step, avoids etching injury, raising is partly led
The performance of body device.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 1 to Fig. 7 is the corresponding the schematic diagram of the section structure of each step of manufacturing method of semiconductor device provided by the invention.
With reference to Fig. 1, the substrate 100 including first area I and second area II is provided, the type of the first area I is
The type of the NMOS area perhaps PMOS area second area II is NMOS area or PMOS area, and firstth area
Domain I is different from the type of second area II, is respectively formed with grid on the substrate 100 of the first area I and second area II
101。
The material of the substrate 100 uses monocrystalline silicon or germanium.The material of the grid 101 uses polysilicon, or
Aluminium, tantalum, tungsten.
In the present embodiment, the first area I is PMOS area, is used to form PMOS device, the second area II is
NMOS area is used to form NMOS device.In other embodiments, the first area may be PMOS area, accordingly
Second area is NMOS area.
In the present embodiment, further include the formation shallow trench isolation regions 102 in the substrate 100, utilize dry etching work
Skill etches to form isolation shallow slot；SiO is deposited in the isolation shallow slot2And fill up the isolation shallow slot, form the shallow ridges
Road isolated area 102.Shallow trench isolation technology is used to constitute the component separation of device, using shallow trench isolation technology strict guarantee
The area of device active region, improves minimum isolating partition and junction capacity, and low temperature process reduces costs.
In the first area I, 100 surface of substrate of second area II and 101 top of the grid and sidewall surfaces
Form protective layer 107.
Extended meeting forms insulation stress layer on substrate 100 and grid 101 afterwards, and there is also etch the insulation stress layer
It acts on, plays the role of etching cutoff layer in the technique of insulation stress layer described in subsequent etching of protective layer 107.
The protective layer 107 with a thickness of 10-30A.The material of the protective layer 107 includes silica.
It should be noted that also forming the first silicon oxide layer 103 in 101 bottom of normal-gate for forming protective layer 107.It is described
First silicon oxide layer 103 is between grid 101 and substrate 100.
The second silicon oxide layer 104, the first silicon nitride layer 105, the second silicon nitride layer 106 are formed after forming grid 101.
Second silicon oxide layer 104 is located at 101 top of grid and sidewall surfaces；First silicon nitride layer 105 is located at the second oxidation
104 top surface of silicon layer；Second silicon nitride layer 106 is located at 105 side wall table of the second silicon oxide layer 104 and the first silicon nitride layer
Face.
Form first silicon oxide layer 103, the second silicon oxide layer 104, the first silicon nitride layer 105, the second silicon nitride layer
106 the step of includes: the shape on substrate 100 before being formed with grid 101 on the substrate 100 of first area I and second area II
At the first silicon oxide layer 103；Grid 101 is formed on the first silicon oxide layer 103；It is formed at 101 top of grid and sidewall surfaces
Second silicon oxide layer 104；The first silicon nitride layer 105 is formed at the top of the second silicon oxide layer 104；In the second silicon oxide layer 104 and
First silicon nitride layer, 105 side wall forms the second silicon nitride layer 106.
Gate oxide of first silicon oxide layer 103 as grid 101, is played exhausted between grid 101 and substrate 100
Edge effect.
Extended meeting afterwards forms the first stressor layers in substrate 101, first silicon nitride layer 105, the second silicon nitride layer 106,
Second silicon oxide layer 104 plays a protective role to grid 101 in the technical process for being subsequently formed the first stressor layers.
First silicon oxide layer 103 is with a thickness of 10-30A；Second silicon oxide layer 104 is with a thickness of 10-30A；Described first
Silicon nitride layer 105 is with a thickness of 200-300A；Second silicon nitride layer 106 is with a thickness of 70-90A.
With reference to Fig. 2, insulation stress layer 108 is formed on 101 top of grid and side wall and the substrate 100.
Specifically, the insulation stress layer 108 is formed on 107 surface of protective layer.
The effect of the insulation stress layer 108 includes: that on the one hand, subsequent etching respectively is answered positioned at the insulation of first area I
Power layer 108 and insulation stress layer 108 positioned at second area II form first absolutely in 101 side wall of first area I grid accordingly
Fiber stress side wall forms the second insulation stress side wall in 101 side wall of second area II grid；On the other hand, subsequent to described
The insulation stress layer 108 of two region II is made annealing treatment, so that the stress migration in insulation stress layer 108 is to second area II
In the channel region of 101 lower section of grid.
In the present embodiment, the material of the insulation stress layer 108 is tensile stress material, and the tensile stress material is nitrogen
SiClx.The thickness 200-300A of the insulation stress layer 108.
The insulation stress layer is formed using chemical gaseous phase deposition technique (CVD, Chemical Vapor Deposition)
108.Gas occurs chemical reaction and forms reaction product, and the reaction product is covered on the grid 101 and substrate 100
On, form the insulation stress layer 108.Chemical gaseous phase deposition technique can accurately control ingredient, and operation is simple, low in cost.
In the present embodiment, the chemical gaseous phase deposition technique is Plasma Enhanced Chemical Vapor depositing technology.Plasma increases
Extensive chemical gaseous phase deposition technique be by rf electric field occur glow discharge formed plasma with enhance chemical reaction, using from
Son enhancing chemical gaseous phase deposition technique has the advantages that depositing temperature is low, uniformity is good.
In other embodiments, first area is NMOS area, and the material of the insulation stress layer is compressive stressed materials.
With reference to Fig. 3, photoresist layer 110 is formed on 108 surface of insulation stress layer of second area II.
The removal of extended meeting etching is located at the insulation stress layer 108 on substrate 100 and on 101 top of grid afterwards；It is gone in etching
Before the insulation stress layer 108 being located on first area I substrate 100 and on 101 top of grid, the photoresist layer is formed
110, exposure mask of the photoresist layer 110 as subsequent etching processes.
With reference to Fig. 4, etching removal is located at the insulation stress layer on first area I substrate 100 and on 101 top of grid
108,100 surface of first area I substrate is exposed, the first insulation is formed in 101 side wall of grid of the first area I and answers
Power side wall 109.
It specifically, is exposure mask with the photoresist layer 110, the etching removal removal is located on first area I substrate 100
And the insulation stress layer 108 on 101 top of grid.
In the present embodiment, the first insulation stress side wall 109 is formed in the 107 side wall table of protective layer of first area I
Face.First insulation stress side wall 109 provides Process ba- sis to be subsequently formed first groove.First exposed described in subsequent etching
Region I substrate 100 forms first groove, the first insulation stress side in the substrate 100 of 101 two sides of first area I grid
Wall 109 plays the protection to grid 101.
The material of the first insulation stress side wall 109 is identical as the material of the insulation stress layer 108.
In the present embodiment, the material of the first insulation stress side wall 109 uses tensile stress material.Other embodiments
In, the material of the first insulation stress side wall uses compressive stressed materials.
The first insulation stress side wall 109 be parallel to 100 surface direction of substrate with a thickness of 200-300A.
Protection when etching removal is located at the insulation stress layer 108 on first area I substrate 100, on the I substrate of first area
Layer 107 plays the role of etching cutoff layer；After etching insulation stress layer 108, etch-protecting layer 107 is also wanted.
The etching removal of using plasma etching technics is on first area I substrate 100 and on 101 top of grid
Insulation stress layer 108.
Specifically, the etching gas used is fluoro-gas, using in gaseous plasma free active group with from
Son is reacted with 108 surface of insulation stress layer, and etching removal is located on the first area I substrate 100 and grid 101
Insulation stress layer 108 on top.
It is located at the insulation stress layer 108 on the first area I substrate 100 and on 101 top of grid in etching removal
Afterwards, the photoresist layer 107 is removed.
With reference to Fig. 5, the first area I substrate 100 exposed described in etching, in 101 two sides of first area I grid
First groove 111 is formed in substrate 100.
It forms first groove 111 and provides Process ba- sis for the first stressor layers of subsequent filling.First groove 111 can be Σ shape
Contoured trench.
When the first area I substrate 100 exposed described in etching, the first insulation stress side wall 109 plays protection grid 101
Effect.
With reference to Fig. 6, the first stressor layers 112 of the full first groove 111 (referring to Fig. 5) of filling are formed.
First stressor layers 112 are used to form the source and drain doping area of first area I.In the present embodiment, described first is answered
It is higher than 100 surface of substrate at the top of power layer 112.In other embodiments, acceptable and substrate at the top of first stressor layers
Surface flushes.
In the present embodiment, the material of first stressor layers 112 includes SiGe.Forming first stressor layers 112
Technical process in, can also to first stressor layers 112 carry out P-type ion doping, the P-type ion be B ion, Ga from
Son or In ion.
In other embodiments, when first area is NMOS area, the material of the first stressor layers may be silicon carbide.In
It is formed in the technical process of first stressor layers, N-type ion doping, the N-type can also be carried out to first stressor layers
Ion is P ion, As ion or Sb ion.
After forming the first insulation stress side wall 109, the insulation stress layer 108 of the second area II is carried out
Annealing.
The insulation stress layer 108 of the second area II is made annealing treatment, the stress in insulation stress layer 108 is moved
It moves in the channel region of 101 lower section of second area II grid, improves 101 underlying channel region internal stress of second area II grid.
Since the material of the insulation stress layer 108 of the second area II is tensile stress material, so that making annealing treatment
Insulation stress layer 108 limits grid 101 and expands upwards during recrystallizing in the process, therefore perpendicular to substrate 100
In surface direction compression can be formed in grid 101；During grid 101 recrystallizes, grid 101 be in the longitudinal direction by
Compression, it is accordingly horizontally stretched, therefore generate tensile stress in the channel region below grid 101, to improve
The carrier mobility of NMOS device channel region.
The annealing temperature that the annealing uses is unsuitable too low, also unsuitable excessively high.If what the annealing used moves back
Fiery temperature is too low, then the trend that grid 101 expands upwards during recrystallizing is too small, accordingly makes below grid 101
Channel region in generate tensile stress it is too small；If the annealing temperature that the annealing uses is excessively high, it be easy to cause in substrate 100
Doped ions spread again.For this purpose, in the present embodiment, the annealing temperature that uses of making annealing treatment is 1000 DEG C~1200
℃。
In the present embodiment, before forming the annealing, first stressor layers 112 are formed.
It should be noted that in other embodiments, can also be initially formed after the first groove, and described in the progress
After annealing, first stressor layers are formed.But due to first being made annealing treatment, it may cause first groove surface and go out
Current bound planar defect or crystal defect hinder the growth of the first stressor layers；In order to remove the boundary defect or crystal defect
The first groove is started the cleaning processing after the annealing process.The cleaning treatment can be used alkaline oxygenated or acidic oxidation
Wet chemical cleans method.
It should also be noted that, in other embodiments, can first carry out the annealing, form first ditch afterwards
Slot and the first stressor layers.
With reference to Fig. 7, etching is located at the insulation stress layer on the second area II substrate 100 and on 101 top of grid
108,100 surface of second area II substrate is exposed, the second insulation is formed in the gate lateral wall of the second area II and answers
Power side wall 113.
In the present embodiment, specifically, the second insulation stress side wall 113 is formed in the protective layer of second area II
107 sidewall surfaces.It is subsequent in substrate 100 formed second groove when, the second insulation stress side wall 113 is played to 101 side of grid
The protective effect of wall.
The second insulation stress side wall 113 is identical as 109 material of the first insulation stress side wall.
In the present embodiment, the material of the second insulation stress side wall 113 is tensile silicon nitride.In other embodiments, the
The material of two insulation stress side walls 113 uses compressive stressed materials.
The second insulation stress side wall 113 be parallel to 100 surface direction of substrate with a thickness of 200-300A.
Manufacturing method of semiconductor device provided by the invention simplifies processing step, substitutes traditional work using insulation stress layer
In skill for formed first insulation side wall and second insulation side wall needed for side wall layer, avoid traditional handicraft after the annealing process into
Behavior etches the insulation stress layer removed on substrate and the etching technics used, simplifies processing step, and the production method
Etching injury caused by etching technics is also avoided, the electric property of semiconductor devices is improved.
The present invention also provides a kind of semiconductor devices made of above-mentioned production method, with reference to Fig. 7, semiconductor devices packet
Include: the substrate 100 including first area I and second area II, the type of the first area I are NMOS area or the area PMOS
Domain, the type of the second area II are NMOS area or PMOS area, and the class of the first area I and second area II
Type is different, has grid 101 on the substrate 100 of the first area I and second area II；Positioned at the grid 101 of first area I
First insulation stress side wall 109 of side wall；First groove 111 in the substrate 100 of 101 two sides of first area I grid；It fills out
The first stressor layers 112 full of the first groove 111；Positioned at the second insulation stress of 101 side wall of grid of second area II
Side wall 113.
Semiconductor devices provided in an embodiment of the present invention is described in detail below with reference to attached drawing.
In the present embodiment, the first area I is PMOS area, the material and second of the first insulation stress side wall 109
The material of insulation stress side wall 113 is identical.The material of the first insulation stress side wall 109 is tensile stress material.
It should be noted that in other embodiments, the first area is NMOS area, first insulation stress side
The material of wall is compressive stressed materials.
In the present embodiment, the material of the substrate 100 uses monocrystalline silicon or germanium.The material of the grid 101 is using more
Crystal silicon, or aluminium, tantalum, tungsten.
The semiconductor devices further include: protective layer 107, the protective layer 107 are located at first area I, second area II
101 sidewall surfaces of grid.
The protective layer 107 with a thickness of 10-30A.The material of the protective layer 107 and the first insulation stress side wall
109 material is different.Specifically, the material of the protective layer 107 includes silica.
The first insulation stress side wall 109 is located at 107 sidewall surfaces of protective layer of first area I.
The first insulation stress side wall 109 plays the protection to grid 101.
The material of the first insulation stress side wall 109 is tensile silicon nitride.The first insulation stress side wall 109 is flat
Row is in 100 surface direction of substrate with a thickness of 200-300A.
It should also be noted that, the first groove 111 is used to fill the first stressor layers of the full first groove 111
112 provide basis.
The first groove 111 can be Σ shape contoured trench.
First stressor layers 112 are for the source and drain doping area as first area I.In the present embodiment, described first is answered
It is higher than 100 surface of substrate at the top of power layer 112.In other embodiments, acceptable and substrate at the top of first stressor layers
Surface flushes.
The material of first stressor layers 112 includes SiGe.In other embodiments, first area is NMOS area
When, the material of the first stressor layers may be silicon carbide.
In the present embodiment, specifically, the second insulation stress side wall 113 is located at the protective layer 107 of second area II
Sidewall surfaces.
It is subsequent in substrate 100 formed second groove when, the second insulation stress side wall 113 is played to 101 side of grid
The protective effect of wall.
In the present embodiment, the material of the second insulation stress side wall 113 is tensile silicon nitride.Second insulation is answered
Power side wall 113 be parallel to 100 surface direction of substrate with a thickness of 200-300A.
Semiconductor devices of the present invention includes the first insulation stress side wall of the gate lateral wall positioned at first area and is located at the
Second insulation stress side wall of the gate lateral wall in two regions forms the first insulation stress side wall and second absolutely using insulation stress layer
Fiber stress side wall, substitution traditional handicraft are side wall layer needed for forming the first insulation side wall and the second insulation side wall.First insulation
Stress side wall, the material of the second insulation stress side wall are identical, are all made of tensile stress material or compressive stressed materials, the first insulation
Stress side wall, the second insulation stress side wall play the protective effect to gate lateral wall.Therefore, semiconductor devices provided by the invention
Electric property is excellent.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of production method of semiconductor devices characterized by comprising
The substrate including first area and second area is provided, the type of the first area is NMOS area or the area PMOS
The type in domain, the second area is NMOS area or PMOS area, and the type of the first area and second area is not
Together, grid is respectively formed on the substrate of the first area and second area；
Insulation stress layer is formed on the top portions of gates and side wall and the substrate；
Etching removal is located at the insulation stress layer on the substrate of first area and on top portions of gates, exposes the first area lining
Bottom surface, the gate lateral wall in the first area form the first insulation stress side wall；
After forming the first insulation stress side wall, the insulation stress layer of the second area is made annealing treatment；
The first area substrate exposed described in etching, forms first groove in the substrate of first area grid two sides；
Form the first stressor layers for filling the full first groove；
Etching is located at the insulation stress layer on the second area substrate and on top portions of gates, exposes the second area lining
Bottom surface forms the second insulation stress side wall in the gate lateral wall of the second area.
2. production method as described in claim 1, which is characterized in that the first area is PMOS area, and the insulation is answered
The material of power layer is tensile stress material.
3. production method as claimed in claim 2, which is characterized in that the tensile stress material is silicon nitride.
4. production method as claimed in claim 2, which is characterized in that the insulation stress layer with a thickness of 200-300A.
5. production method as claimed in claim 2, which is characterized in that form the insulation using chemical gaseous phase deposition technique and answer
Power layer.
6. production method as described in claim 1, which is characterized in that the material of first stressor layers includes SiGe.
7. production method as described in claim 1, which is characterized in that the first area is NMOS area, and the insulation is answered
The material of power layer is compressive stressed materials.
8. production method as described in claim 1, which is characterized in that be initially formed the first groove, carry out the annealing afterwards
Processing.
9. production method as claimed in claim 8, which is characterized in that before carrying out the annealing, form described the
One stressor layers.
10. production method as claimed in claim 9, which is characterized in that the annealing temperature that uses of making annealing treatment is 1000
DEG C~1200 DEG C.
11. production method as claimed in claim 8, which is characterized in that after carrying out the annealing, form described the
One stressor layers.
12. production method as claimed in claim 11, which is characterized in that after carrying out the annealing, described in formation
Before first stressor layers, further includes: started the cleaning processing to the first groove.
13. production method as described in claim 1, which is characterized in that first carry out the annealing, form described first afterwards
Groove.
14. production method as described in claim 1, which is characterized in that before forming the insulation stress layer, further includes:
Protective layer, the guarantor are formed in the first area, the substrate surface of second area and the top portions of gates and sidewall surfaces
The material of sheath is different from the material of the insulation stress layer.
15. production method as claimed in claim 14, which is characterized in that the material of the protective layer includes silica.
16. production method as described in claim 1, which is characterized in that etching removal be located at first area substrate on and
Before insulation stress layer on top portions of gates, photoresist layer is formed in the insulation stress layer surface of second area；With the photoresist
Layer is exposure mask；After the insulation stress layer that etching removal is located on the first area substrate and on top portions of gates, institute is removed
State photoresist layer.
17. production method as described in claim 1, which is characterized in that the etching removal of using plasma etching technics is located at
Insulation stress layer on the substrate of first area and on top portions of gates.
18. a kind of semiconductor devices characterized by comprising
Substrate including first area and second area, the type of the first area are NMOS area or PMOS area, institute
The type for stating second area is NMOS area or PMOS area, and the first area is different from the type of second area, institute
Stating has grid on the substrate of first area and second area；
Positioned at the first insulation stress side wall of the gate lateral wall of first area；
First groove in the substrate of first area grid two sides；
Fill the first stressor layers of the full first groove；
Positioned at the second insulation stress side wall of the gate lateral wall of second area.
19. semiconductor devices as claimed in claim 18, which is characterized in that the first area is PMOS area, described the
The material of one insulation stress side wall is tensile stress material.
20. semiconductor devices as claimed in claim 18, which is characterized in that the first area is NMOS area, described the
The material of one insulation stress side wall is compressive stressed materials.
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| US20090294866A1 (en) * | 2008-05-29 | 2009-12-03 | Manfred Eller | Transistor Fabrication Methods and Structures Thereof |
| CN102292811A (en) * | 2009-01-26 | 2011-12-21 | 格罗方德半导体公司 | Methods for fabricating mos devices having epitaxially grown stress-inducing source and drain regions |
| CN103545257A (en) * | 2012-07-12 | 2014-01-29 | 中芯国际集成电路制造(上海)有限公司 | Production method of Complementary Metal-Oxide-Semiconductor (CMOS) transistor |
| CN103681502A (en) * | 2012-09-18 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Method for forming CMOS transistor |
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| US20090294866A1 (en) * | 2008-05-29 | 2009-12-03 | Manfred Eller | Transistor Fabrication Methods and Structures Thereof |
| CN102292811A (en) * | 2009-01-26 | 2011-12-21 | 格罗方德半导体公司 | Methods for fabricating mos devices having epitaxially grown stress-inducing source and drain regions |
| CN103545257A (en) * | 2012-07-12 | 2014-01-29 | 中芯国际集成电路制造(上海)有限公司 | Production method of Complementary Metal-Oxide-Semiconductor (CMOS) transistor |
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