CN110415751B - Memory built-in self-test circuit capable of being configured in parameterization mode - Google Patents
Memory built-in self-test circuit capable of being configured in parameterization mode Download PDFInfo
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- CN110415751B CN110415751B CN201910720675.6A CN201910720675A CN110415751B CN 110415751 B CN110415751 B CN 110415751B CN 201910720675 A CN201910720675 A CN 201910720675A CN 110415751 B CN110415751 B CN 110415751B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/14—Implementation of control logic, e.g. test mode decoders
Abstract
A parametrically configurable memory built-in self-test circuit includes a signal generation module 101, a data selection module 102, a JTAG module 103, and a main controller 104. The signal generation module 101 and the data selection module 102 are connected with the main controller 104, the data selection module 102 and the JTAG module 103 are connected with the signal generation module 101, the JTAG module 103 is connected with the external TAP controller 105, and the data selection module 102 is connected with the external memory 106 to be tested. Each piece of memory to be tested corresponds to one signal generation module and one data selection module. The invention provides a memory test circuit which can be integrated, programmable and configurable, is easy to integrate and is flexible to use.
Description
Technical Field
The invention relates to the field of memory test, in particular to a memory built-in self-test circuit capable of being configured in a parameterization mode.
Background
Nowadays, the rapid development of the mobile internet of things puts higher and higher requirements on the processing capability of the intelligent mobile device, and the embedded memory represents most embedded electronic devices in a System on Chip (SoC). In 2002, more than 50% of chip area contains memories with various functions, and the SoC chip is shifted from a logic-dominated form to a memory-dominated form to meet application requirements, so that the testing quality of the memories can significantly influence the testability of the whole SoC, and the yield of the memories directly influences the final product quality of the SoC chip.
On one hand, as the memory density and clock speed increase, the high-speed and high-density characteristics of the memory chip are different from those of a common digital chip, and the probability of the memory chip failing is higher due to the increasingly significant name of open circuit failure and capacitive coupling, and the circuit is more "time-critical". On the other hand, the conventional testing method is mainly performed by external ATE equipment, but the controllability and observability of the conventional testing are reduced due to the limited number of pins available for memory testing in the chip. Moreover, the conventional testing method requires a long testing time and a low fault coverage, and it is difficult to meet the testing requirements of high-complexity and high-integration memories, which are generated along with the development of semiconductor technology.
The Memory Test methods are various, such as direct Memory Test, Test by an on-chip microprocessor, Test by an ASIC function, scan register Test, etc., wherein a more mainstream method is Memory Built-In Self-Test (MBIST), which is not limited by the number of chip pins and the storage capacity of a tester, simplifies the generation of Test vectors, supports the addition of a Test algorithm, reduces the dependency on ATE, and greatly saves the Test cost and the Test period.
At present, tools support automatic generation and implantation of an MBIST circuit, although the method can greatly improve the working efficiency of designers, the method is not flexible on the whole, for example, in the aspect of configuration of a self-defined test algorithm, specific test steps in a part of self-defined algorithms cannot be successfully realized, so that the test efficiency is low and even the test result is invalid; for example, in the aspect of automatically generated circuit structure, a part of redundant logic and signals are usually generated, which increases the circuit complexity and chip area overhead.
Therefore, a series of problems related to the memory test needs to be solved.
Disclosure of Invention
The design objective of the invention is as follows: in order to overcome the problems in the prior art, the invention provides a memory built-in self-test circuit which is low in cost, easy to integrate and flexible and configurable.
A kind of memory built-in self-test circuit that can be disposed parametrically, including signal generation module, data selection module, JTAG module and master controller, characterized by that:
the signal generation module is connected with the data selection module, the JTAG module and the main controller, and the main controller is connected with the data selection module;
the JTAG module is connected with an external TAP controller, and the data selection module is connected with an external memory to be tested;
the main controller transmits signals to the data selection module in a single direction, and the other connection modes are bidirectional signal transmission;
each piece of memory to be tested corresponds to one signal generation module and one data selection module.
Furthermore, the main controller comprises a test state control module, a mode register circuit, a storage unit selection module, an algorithm control module and a test vector generation module;
the mode register circuit, the storage unit selection module, the algorithm control module and the test vector generation module are all connected with the test state control module;
the mode register circuit, the algorithm control module and the test vector generation module are all connected with the storage unit selection module;
the mode register circuit is connected with the algorithm control module;
the test state control module and the test vector generation module transmit signals to the storage unit selection module in a single direction, and the rest of connection modes are bidirectional signal transmission.
Furthermore, the mode register circuit comprises a mode register, which is configured at the beginning stage of the test and is a set of readable and writable data registers, the bit length of which is at least 15 bits, and the length is determined by the number of memory chips to be tested;
the 0 th bit of the mode register represents an indication signal when the test is completed; the 1 st bit represents a master controller enable signal; bits 2 to 5 represent configurable selection signals of 4 custom algorithms; bit 6 represents a wait or pause enable signal during the test; bit 7 represents an indication signal when a fault is detected during the test; bit 8 represents a debug mode select signal; bits 9 to 12 represent the data vector applied in the event of a detected fault; bits 13 and 14 represent the selected ports in the event of a detected fault; the 15 th bit represents a chip selection signal of the memory to be tested;
wherein, the 9 th bit to the 14 th bit are read-only and non-writable, and the rest bits are all readable and writable.
Furthermore, the test state control module is used for controlling the operation of the memory test algorithm, including the selective use of ports and test vectors, and controlling the normal operation of each sub-module; the mode register circuit is used for initializing and configuring the mode register and indicating the working state of the whole circuit; the storage unit selection module is used for selecting a storage which is to run the current algorithm and judging the running condition of the storage according to the signal output by the signal generation module; the algorithm control module controls the operation of built-in four self-defined algorithms through a state machine and simultaneously provides test segment descriptors to the signal generation module; the test vector generation module is used for generating a data test vector and loading the vector to the signal generation module.
Furthermore, the signal generation module comprises a read-write control module, an address generation module and a data generation module;
the address generation module and the data generation module are connected with the read-write control module; the address generation module is also connected with the data generation module;
the signal transmission among the read-write control module, the address generation module and the data generation module is a bidirectional channel.
The invention has the beneficial effects that: the invention can support the test of various and multi-chip memories such as SRAM, CAM, Cache and the like, and also support the At-Speed test; two selectable test modes and four configurable self-defined test algorithms are adopted, so that the test efficiency and the flexibility are improved. The invention is a digital logic module which can be synthesized, programmed and configured based on the MBIST principle, so that the module can be integrated when in the RTL synthesis stage in the actual design, and the integrity and the testability of the circuit are enhanced. For designers in the field, the invention provides a memory testing means which is low in cost, easy to integrate, flexible and configurable.
Drawings
Fig. 1 is a schematic diagram of an overall circuit structure according to an embodiment of the present invention.
FIG. 2 is a functional diagram of a mode register according to an embodiment of the present invention.
FIG. 3 is a block diagram of test segment descriptor code according to an embodiment of the present invention.
FIG. 4 is a schematic diagram of an overall simulation waveform for generating a test result according to an embodiment of the present invention.
FIG. 5 is a schematic diagram of a simulation waveform of local detail of a test result generated in an embodiment of the present invention.
FIG. 6 is a diagram illustrating state transitions of a top state machine according to an embodiment of the present invention.
Detailed Description
The technical scheme of the invention is further explained in detail by combining the drawings in the specification.
A parametrically configurable memory built-in self-test circuit includes a signal generation module 101, a data selection module 102, a JTAG module 103, and a main controller 104. The signal generation module 101 is connected to the data selection module 102, the JTAG module 103, and the main controller 104, while the main controller 104 is connected to the data selection module 102. The JTAG module 103 is connected to an external TAP controller 105, and the data selection module 102 is connected to an external memory under test 106.
The main controller 104 transmits signals to the data selection module 102 in a single direction, and the other connection modes are bidirectional signal transmission.
Each piece of memory to be tested 106 corresponds to one signal generation module 101 and one data selection module 102.
The signal generation module 101 includes a read/write control module 121, an address generation module 122, and a data generation module 123. The address generation module 122 and the data generation module 123 are both connected to the read-write control module 121; the address generation module 122 is also connected to the data generation module 123. The signal transmission among the read-write control module 121, the address generation module 122, and the data generation module 123 is a bidirectional channel.
The read-write control module 121 is used for controlling the read/write state of the memory; the address generating module 122 is configured to generate a test address signal of the memory; the data generating module 123 is configured to generate data and compare the data, and output a comparison result to indicate a memory test result.
The JTAG module 103 supports the IEEE 1149.1 protocol standard for enabling communication between the overall circuit module and an external TAP controller.
The main controller 104 includes a test state control block 111, a mode register circuit 112, a memory cell selection block 113, an algorithm control block 114, and a test vector generation block 115.
The mode register circuit 112, the memory cell selection module 113, the algorithm control module 114 and the test vector generation module 115 are all connected to the test state control module 111. The mode register circuit 112, the algorithm control module 114, and the test vector generation module 115 are all connected to the memory cell selection module 113. The mode register 112 circuitry is coupled to an algorithm control module 114.
The test state control module 111 and the test vector generation module 115 transmit signals to the storage unit selection module 113 in a single direction, and the other connection modes are bidirectional signal transmission.
The test state control module 111 is used for controlling the operation of the memory test algorithm, including the selective use of ports and test vectors, and controlling the normal operation of each sub-module; mode register circuitry 112 is used for initial configuration of the mode register and to indicate the operational status of the overall circuit; the storage unit selection module 113 is used for selecting a storage unit which is to run the current algorithm, and judging the running condition according to the signal output by the signal generation module; the algorithm control module 114 controls the operation of the built-in four self-defined algorithms through a state machine, and simultaneously provides test segment descriptors to the signal generation module 101; the test vector generation module 115 is used to generate a data test vector and load the vector to the signal generation module 101.
The mode register circuit 112 includes a mode register, as shown in fig. 2, which is a functional diagram of the mode register according to the embodiment of the present invention. The mode register is an important part of the main controller 104, is used to control the operation of the MBIST and display its operation status, is configured in the beginning stage of the test, and is a set of readable and writable data registers, the bit length of which is at least 15 bits, and is specifically determined by the number of memory chips to be tested.
FIG. 3 is a block diagram of test segment descriptor code according to an embodiment of the present invention. Preferably, in this embodiment, the test SEGMENT description signal is defined as SEGMENT, which has 5 bits in total, and the initialization configuration value is 0. Bit 0 represents the type (1 or 0) of the access element within the test segment; the 1 st bit represents the address traversal direction (either ↓or ↓); bit 2 indicates the type of read or write operation within the test segment; together, bits 3 and 4 indicate the number of elements in the test segment, e.g., binary number 11 indicates a maximum of 4 elements in a test segment. Preferably, ALGORITHM defined in this embodiment is used to describe the currently selected ALGORITHM, and has 4 bits in total; and the CURRENT defined to record the test segment of the CURRENT algorithm, 3 bits in total. Preferably, the four custom algorithms in this embodiment are shown in the following table, and the respective selection signals respectively correspond to bits 2 to 5 of the mode register:
note that only a few of the test steps of the above algorithm are shown in fig. 3, the primary purpose being to illustrate the Verilog code writing method of testing segment descriptors.
Fig. 4 is a schematic diagram of an overall simulation waveform for generating a test result according to an embodiment of the present invention. Preferably, in this embodiment, a single-port SRAM is tested, the test algorithm adopted is March LR, and the following table specifically describes:
according to the difference between the value of the read data signal and the value of the reference data signal, the memory to be tested in the embodiment has a fault. Fig. 5 is a schematic diagram of a simulation waveform of the local detail in the box of fig. 4. The memory address signals change in descending order over two test clock cycles within one address signal. In the first clock cycle, the write-in enabling signal of the memory is pulled high, and the memory reads out 0; in the second clock period, the memory write enable signal is pulled low, the memory is written into 1, and the combination shows that the second test step in the MarchLR algorithm is successfully executed
Fig. 6 is a schematic diagram of state transition of a top state machine according to an embodiment of the present invention. The top state machine is used for maintaining the correctness of the selection of the algorithm, the port and the test vector and controlling the normal operation among all the sub-modules based on the elements. All states of the top state machine include: an idle state (3b '000), an algorithm detect state (3 b' 001), a test vector load state (3b '010), a custom test vector load state (3 b' 011), an algorithm run state (3b '100), an increment parameter state (3 b' 101), a mode register waiting reload state (3b '110), and a test algorithm waiting restart state (3 b' 111).
The above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above embodiment, but equivalent modifications or changes made by those skilled in the art according to the present disclosure should be included in the scope of the present invention as set forth in the appended claims.
Claims (4)
1. A kind of memory built-in self-test circuit that can be disposed parametrically, including signal generation module, data selection module, JTAG module and master controller, characterized by that:
the signal generation module is connected with the data selection module, the JTAG module and the main controller, and the main controller is connected with the data selection module;
the JTAG module is connected with an external TAP controller, and the data selection module is connected with an external memory to be tested;
the main controller comprises a test state control module, a mode register circuit, a storage unit selection module, an algorithm control module and a test vector generation module;
the mode register circuit, the storage unit selection module, the algorithm control module and the test vector generation module are all connected with the test state control module; the mode register circuit, the algorithm control module and the test vector generation module are all connected with the storage unit selection module; the mode register circuit is connected with the algorithm control module; the test state control module and the test vector generation module transmit signals to the storage unit selection module in a single direction, and the rest connection modes are bidirectional signal transmission;
the test state control module is used for controlling the operation of a memory test algorithm, including the selective use of ports and test vectors, and controlling the normal operation of each submodule; the test vector generation module is used for generating a data test vector and loading the vector to the signal generation module;
the algorithm control module controls the operation of the built-in four self-defined algorithms through a state machine and simultaneously provides a test section description signal to the signal generation module;
the signal generation module comprises a read-write control module, an address generation module and a data generation module; the read-write control module, the address generation module and the data generation module are connected with each other in pairs;
the test SEGMENT description signal is defined as SEGMENT, the total number of bits is 5, and the initialization configuration value is 0; bit 0 represents the class of the access element within the test segment; the 1 st bit represents the address traversal direction; the 2 nd bit represents the read-write operation type in the test section; the 3 rd bit and the 4 th bit represent the number of elements in the test segment through binary numbers;
the main controller transmits signals to the data selection module in a single direction, and the other connection modes are bidirectional signal transmission;
each piece of memory to be tested corresponds to one signal generation module and one data selection module.
2. The parametrically configurable memory built-in self-test circuit of claim 1, wherein: the mode register circuit comprises a mode register which is configured at the beginning stage of testing and is a group of readable and writable data registers, and the bit length of the data registers is determined by the number of the memory chips to be tested;
the 0 th bit of the mode register represents an indication signal when the test is completed; the 1 st bit represents a master controller enable signal; bits 2 to 5 represent configurable selection signals of 4 custom algorithms; bit 6 represents a wait or pause enable signal during the test; bit 7 represents an indication signal when a fault is detected during the test; bit 8 represents a debug mode select signal; bits 9 to 12 represent the data vector applied in the event of a detected fault; bits 13 and 14 represent the selected ports in the event of a detected fault; the 15 th bit represents a chip selection signal of the memory to be tested;
wherein, the 9 th bit to the 14 th bit are read-only and non-writable, and the rest bits are all readable and writable.
3. The parametrically configurable memory built-in self-test circuit of claim 2, wherein: the mode register circuit is used for initializing and configuring the mode register and indicating the working state of the whole circuit; the storage unit selection module is used for selecting a storage which is to run the current algorithm and judging the running condition of the storage according to the signal output by the signal generation module; the algorithm control module controls the operation of the built-in four self-defined algorithms through a state machine and provides a test section description signal to the signal generation module at the same time.
4. The parametrically configurable memory built-in self-test circuit of claim 2, wherein: the address generation module and the data generation module are connected with the read-write control module; the address generation module is also connected with the data generation module; the signal transmission among the read-write control module, the address generation module and the data generation module is a bidirectional channel.
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