CN110399331A - The method of clock signal noise is reduced in SOC chip and SOC chip - Google Patents
The method of clock signal noise is reduced in SOC chip and SOC chip Download PDFInfo
- Publication number
- CN110399331A CN110399331A CN201910724592.4A CN201910724592A CN110399331A CN 110399331 A CN110399331 A CN 110399331A CN 201910724592 A CN201910724592 A CN 201910724592A CN 110399331 A CN110399331 A CN 110399331A
- Authority
- CN
- China
- Prior art keywords
- clock
- clock signal
- soc chip
- source
- receiving unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000002955 isolation Methods 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 8
- 238000005516 engineering process Methods 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 4
- 230000009467 reduction Effects 0.000 claims description 2
- 238000004590 computer program Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 230000006870 function Effects 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/7817—Specially adapted for signal processing, e.g. Harvard architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7828—Architectures of general purpose stored program computers comprising a single central processing unit without memory
- G06F15/7832—Architectures of general purpose stored program computers comprising a single central processing unit without memory on one IC chip (single chip microprocessors)
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Signal Processing (AREA)
- Computing Systems (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a kind of methods that clock signal noise is reduced in SOC chip and SOC chip, it is internal in SOC chip that there is clock source, the method that clock signal noise is reduced in SOC chip comprises determining that the output end of clock source to the clock signal for needing individually to handle transmitted between the clock signal input terminal of clock signal receiving unit, and the clock line of clock signal is separated from clock path；Determine that clock source is transmitted to the clock driver cell that the clock signal input terminal of clock signal receiving unit passes through；The relative placement position of the clock line of the clock signal individually handled as needed connected clock source and clock signal receiving unit in a chip layout, divides the individual region for placing clock driver cell, and clock driver cell is placed in individual region.Whereby, the method that clock signal noise is reduced in SOC chip of the invention, effectively reduces interference of the chip power noise to clock signal.
Description
Technical field
The present invention relates to SOC chip IC design, especially with regard to being reduced in a kind of SOC chip and SOC chip
The method of clock signal noise.
Background technique
With the increase of integrated chip scale, speed is getting faster, and the influence of noise of chip is widely paid close attention to,
As problem very important in IC design.The data transmission of portion's each unit is pressed by the same clock source in the chip
The multipath clock signal that as requested generates different frequency synchronizes control, and multipath clock signal is interweaved on cabling one
It rises, and the driving unit in each road clock signal is dispersed in entire chip range, is powered by electric power network, due to electricity
The coupling of the unstable and power supply and high frequency skip signal line in source leads on the VDD and GND of power supply that there are high frequency jumps
Noise, electric power network easily become the communication media of noise, other regions are diffused into from the one of power supply, for some quicker
Sense clock signal is easier to be influenced by other signals and noise, to influence the work and performance of entire circuit.
In existing design, same layer isolation is carried out mainly for the cabling of clock signal for the noise for reducing clock,
Namely clock line uses a certain layer metal, and shielding wire is also isolated using same layer metal in clock line two sides, when to connection
Buffer power supply on the region and cabling of clock cabling is not handled individually, is placed on one with the logic unit of other function
It rises.
The information disclosed in the background technology section is intended only to increase the understanding to general background of the invention, without answering
When being considered as recognizing or imply that the information constitutes the prior art already known to those of ordinary skill in the art in any form.
Summary of the invention
The purpose of the present invention is to provide a kind of method that clock signal noise is reduced in SOC chip and SOC chip, energy
Enough effectively reduce interference of the chip power noise to clock signal.
To achieve the above object, the present invention provides a kind of method that clock signal noise is reduced in SOC chip, SOC cores
It is internal in piece that there is clock signal unit, and there is clock source in clock signal unit, clock signal noise is reduced in SOC chip
Method comprise determining that the output end of clock source to the needs transmitted between the clock signal input terminal of clock signal receiving unit
The clock signal individually handled, and the clock line of clock signal is separated from clock path；It determines and needs individually processing
Clock signal be transmitted to clock signal receiving unit clock signal input terminal pass through clock driver cell；It is single as needed
The relative placement of the clock line of the clock signal for reason of staying alone connected clock source and clock signal receiving unit in a chip layout
Position divides the individual region for placing clock driver cell, and clock driver cell is placed in individual region；In single area
Individual power supply is created in domain, and the power input of power supply and clock driver cell is electrically connected；By clock source
Output end and clock signal receiving unit clock signal input terminal between clock driver cell clock line metal wire
It is attached；And shielding isolation is carried out to the clock line for the clock signal for needing individually to handle using same layer side isolation technology
Processing.
In a preferred embodiment, clock driver cell is clock buffer or phase inverter.
In a preferred embodiment, the supply voltage of the power supply in individual region is 1.1V.
In a preferred embodiment, the quantity of clock line is at least two, and the quantity of clock driver cell is at least
One.
Compared with prior art, the method that clock signal noise is reduced in SOC chip and SOC chip according to the present invention,
The reliability for increasing sensitive clock signal, using independent power supply to the clock signal of special sensitivity and its transmission when
Clock driving unit is powered, and effectively reduces interference of the chip power noise to clock signal, while the cabling of clock signal
Region is physically realized with chip interior other modules to be isolated.
Detailed description of the invention
Fig. 1 is the process signal for the method that clock signal noise is reduced in SOC chip according to an embodiment of the present invention
Figure.
Fig. 2 is the structure line frame graph of SOC chip according to an embodiment of the present invention.
Main appended drawing reference explanation:
1- clock source, 2- clock line, 3- clock driver cell, 4- clock signal receiving unit, 5- individual region.
Specific embodiment
With reference to the accompanying drawing, specific embodiments of the present invention will be described in detail, it is to be understood that guarantor of the invention
Shield range is not limited by the specific implementation.
Unless otherwise explicitly stated, otherwise in entire disclosure and claims, term " includes " or its change
Changing such as "comprising" or " including " etc. will be understood to comprise stated element or component, and not exclude other members
Part or other component parts.
As shown in Figure 1 to Figure 2, Fig. 1 is reduction clock signal noise in SOC chip according to an embodiment of the present invention
The flow diagram of method；Fig. 2 is the structure line frame graph of SOC chip according to an embodiment of the present invention.
The method for reducing clock signal noise in a kind of SOC chip of a preferred embodiment according to the present invention, SOC chip
Middle inside has clock signal unit, and has clock source 1 in clock signal unit, reduces clock signal noise in SOC chip
Method comprise determining that the output end of clock source 1 to the need transmitted between the clock signal input terminal of clock signal receiving unit 4
The clock signal individually to handle, and the clock line of clock signal 2 is separated from clock path；It determines and needs individually place
The clock signal of reason is transmitted to the clock driver cell 3 that the clock signal input terminal of clock signal receiving unit 4 passes through；According to need
The phase of the clock line 2 for the clock signal individually to handle connected clock source 1 and clock signal receiving unit 4 in a chip layout
To placement position, the individual region 5 for placing clock driver cell 3 is divided, and clock driver cell 3 is placed on individual region 5
It is interior；Individual power supply is created in individual region 5, and the power input of power supply and clock driver cell 3 is electrical
Connection；By the clock driver cell 3 between the output end of clock source 1 and the clock signal input terminal of clock signal receiving unit 4
Clock line 2 be attached with metal wire；And using same layer side isolation technology to the clock signal for needing individually to handle
Clock line 2 carries out shielding isolation processing；Clock driver cell 3 is clock buffer or phase inverter.
In a preferred embodiment, the supply voltage of the power supply in individual region 5 is 1.1V；Clock line 2
Quantity is at least two, and the quantity of clock driver cell 3 is at least one.
A kind of SOC chip of another preferred embodiment according to the present invention, including clock source 1, individual region 5, clock letter
Number receiving unit 4 and multiple clock driver cells 3.Clock source 1 is to generate clock signal；Individual region 5 has power supply electricity
Source；Clock signal receiving unit 4 is electrically connected by clock line 2 and clock source 1；And multiple clock driver cells 3 are set respectively
It is placed on clock line 2 and is electrically connected with clock line 2, and multiple clock driver cells 3 are located in individual region 5；Wherein, it powers
Power supply with multiple clock driver cells 3 to be electrically connected respectively；Wherein, the output end of clock source 1 and clock signal receive single
The clock line 2 of clock driver cell 3 between the clock signal input terminal of member 4 is attached with metal wire；Wherein, using same layer
Side isolation technology carries out shielding isolation processing to clock line 2.
In practical applications, the method for clock signal noise is reduced in SOC chip of the invention with four clock lines 2 and three
For a clock driver cell 3, however, the present invention is not limited thereto.It is single to determine that output end to the clock signal of clock source 1 receives first
The clock signal for needing individually to handle transmitted between the clock signal input terminal of member 4, and by four clock lines 2 of clock signal
It is separated from clock path；Determine that the clock signal for needing individually to handle is transmitted to the clock of clock signal receiving unit 4
Three clock driver cells 3 that signal input part passes through；The clock line 2 of clock signal individually handled as needed be connected when
The relative placement position of clock source 1 and clock signal receiving unit 4 in a chip layout divides and places three clock driver cells 3
Individual region 5, and three clock driver cells 3 are placed in individual region 5 according to the requirement of a fixed spacing；In single area
The individual power supply (creating individual electric power network) of creation in domain 5, and power supply and three clock driver cells 3
Power input is electrically connected；It will be between the output end of clock source 1 and the clock signal input terminal of clock signal receiving unit 4
Four clock lines 2 of three clock driver cells 3 are attached with metal wire, and to four clock lines, 2 shielding processing, according to existing
Four clock lines 2 are isolated in some same layer sides isolation technology.By above method, the clock in individual region 5 is driven
Moving cell 3 has independent supply network, effectively avoids interference of the noise of other regions of chip interior generation to it.
In short, the method for reducing clock signal noise in SOC chip of the invention, increases the reliable of sensitive clock signal
Property, the clock signal of special sensitivity and its clock driver cell of transmission are powered using independent power supply, effectively
Interference of the chip power noise to clock signal is reduced, while the routing region of clock signal and other modules of chip interior exist
Physically realize isolation.
It should be understood by those skilled in the art that, embodiments herein can provide as method, system or computer program
Product.Therefore, complete hardware embodiment, complete software embodiment or reality combining software and hardware aspects can be used in the application
Apply the form of example.Moreover, it wherein includes the computer of computer usable program code that the application, which can be used in one or more,
The computer program implemented in usable storage medium (including but not limited to magnetic disk storage, CD-ROM, optical memory etc.) produces
The form of product.
The application is referring to method, the process of equipment (system) and computer program product according to the embodiment of the present application
Figure and/or block diagram describe.It should be understood that every one stream in flowchart and/or the block diagram can be realized by computer program instructions
The combination of process and/or box in journey and/or box and flowchart and/or the block diagram.It can provide these computer programs
Instruct the processor of general purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to produce
A raw machine, so that being generated by the instruction that computer or the processor of other programmable data processing devices execute for real
The device for the function of being specified in present one or more flows of the flowchart and/or one or more blocks of the block diagram.
These computer program instructions, which may also be stored in, is able to guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works, so that it includes referring to that instruction stored in the computer readable memory, which generates,
Enable the manufacture of device, the command device realize in one box of one or more flows of the flowchart and/or block diagram or
The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device, so that counting
Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, thus in computer or
The instruction executed on other programmable devices is provided for realizing in one or more flows of the flowchart and/or block diagram one
The step of function of being specified in a box or multiple boxes.
The aforementioned description to specific exemplary embodiment of the invention is in order to illustrate and illustration purpose.These descriptions
It is not wishing to limit the invention to disclosed precise forms, and it will be apparent that according to the above instruction, can much be changed
And variation.The purpose of selecting and describing the exemplary embodiment is that explaining specific principle of the invention and its actually answering
With so that those skilled in the art can be realized and utilize a variety of different exemplary implementation schemes of the invention and
Various chooses and changes.The scope of the present invention is intended to be limited by claims and its equivalents.
Claims (10)
1. a kind of method for reducing clock signal noise in SOC chip, internal in SOC chip to have clock source, which is characterized in that
The method of reduction clock signal noise includes: in the SOC chip
Determine that the output end of the clock source needs list to what is transmitted between the clock signal input terminal of clock signal receiving unit
The clock signal for reason of staying alone, and the clock line of the clock signal is separated from clock path；
Determine that the clock signal for needing individually to handle is transmitted to the clock signal input terminal of the clock signal receiving unit
The clock driver cell of process；
The connected clock source of the clock line of the clock signal individually handled as needed and the clock signal
The relative placement position of receiving unit in a chip layout, divides the individual region for placing the clock driver cell, and by institute
Clock driver cell is stated to be placed in the individual region；
Individual power supply, and the power supply of the power supply and the clock driver cell are created in the individual region
Input terminal is electrically connected.
2. reducing the method for clock signal noise in SOC chip as described in claim 1, which is characterized in that further include:
Shielding isolation processing is carried out to the clock line using same layer side isolation technology.
3. reducing the method for clock signal noise in SOC chip as described in claim 1, which is characterized in that the clock drives
Moving cell is clock buffer or phase inverter.
4. reducing the method for clock signal noise in SOC chip as described in claim 1, which is characterized in that the single area
The supply voltage of the power supply in domain is 1.1V.
5. reducing the method for clock signal noise in SOC chip as described in claim 1, which is characterized in that the clock line
Quantity be at least two, the quantity of the clock driver cell is at least one.
6. reducing the method for clock signal noise in SOC chip as described in claim 1, which is characterized in that the clock source
Output end and the clock signal receiving unit clock signal input terminal between the clock driver cell it is described when
Clock line is metal wire.
7. a kind of SOC chip characterized by comprising
Clock source, to generate clock signal；
Clock signal receiving unit is electrically connected by clock line and the clock source；And
Individual region, including power supply and multiple clock driver cells；
Multiple clock driver cells are respectively arranged on the clock line and are electrically connected with the clock line；
The power supply, to be electrically connected respectively with the multiple clock driver cell；
Wherein, the output end of the clock source to the signal transmitted between the clock signal input terminal of clock signal receiving unit is
The clock signal for needing individually to handle.
8. SOC chip as claimed in claim 7 characterized by comprising
The clock between the output end of the clock source and the clock signal input terminal of the clock signal receiving unit drives
The clock line of moving cell is metal wire.
9. SOC chip as claimed in claim 7 characterized by comprising
Shielding isolation processing is carried out to the clock line using same layer side isolation technology in advance.
10. SOC chip as claimed in claim 7, which is characterized in that further comprise:
Other logic units are electrically connected with the clock source, the clock signal generated for receiving the clock source.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910724592.4A CN110399331A (en) | 2019-08-07 | 2019-08-07 | The method of clock signal noise is reduced in SOC chip and SOC chip |
| PCT/CN2020/102871 WO2021022995A1 (en) | 2019-08-07 | 2020-07-17 | Soc chip, and method for reducing clock signal noise in soc chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910724592.4A CN110399331A (en) | 2019-08-07 | 2019-08-07 | The method of clock signal noise is reduced in SOC chip and SOC chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110399331A true CN110399331A (en) | 2019-11-01 |
Family
ID=68327639
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910724592.4A Pending CN110399331A (en) | 2019-08-07 | 2019-08-07 | The method of clock signal noise is reduced in SOC chip and SOC chip |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN110399331A (en) |
| WO (1) | WO2021022995A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021022995A1 (en) * | 2019-08-07 | 2021-02-11 | 北京智芯微电子科技有限公司 | Soc chip, and method for reducing clock signal noise in soc chip |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07282585A (en) * | 1994-04-06 | 1995-10-27 | Hitachi Ltd | Semiconductor device |
| US20030156462A1 (en) * | 2002-02-18 | 2003-08-21 | Lim Hyun-Wook | Memory devices having power supply routing for delay locked loops that counteracts power noise effects |
| US20100201454A1 (en) * | 2009-02-09 | 2010-08-12 | Yi-Tzu Chen | VDD-Independent Oscillator Insensitive to Process Variation |
| US20150048873A1 (en) * | 2013-08-16 | 2015-02-19 | Apple Inc. | Power Source for Clock Distribution Network |
| CN104977977A (en) * | 2014-04-02 | 2015-10-14 | 联发科技股份有限公司 | Clock tree circuit and memory controller |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8775700B2 (en) * | 2011-09-29 | 2014-07-08 | Intel Corporation | Issuing requests to a fabric |
| CN106777437B (en) * | 2015-11-24 | 2020-05-19 | 龙芯中科技术有限公司 | Clock system construction method and device and clock system |
| US10164599B2 (en) * | 2016-09-06 | 2018-12-25 | Mediatek Singapore Pte. Ltd. | Circuitry with a noise attenuation circuit to reduce noise generated by an aggressor circuit |
| CN107918596B (en) * | 2017-11-14 | 2023-09-05 | 上海坤锐电子科技有限公司 | SOC chip and radio frequency signal processing method |
| CN109597476B (en) * | 2018-12-20 | 2023-11-10 | 广州智慧城市发展研究院 | Power management system of information sensing SOC (system on chip) chip of Internet of things |
| CN110399331A (en) * | 2019-08-07 | 2019-11-01 | 北京智芯微电子科技有限公司 | The method of clock signal noise is reduced in SOC chip and SOC chip |
-
2019
- 2019-08-07 CN CN201910724592.4A patent/CN110399331A/en active Pending
-
2020
- 2020-07-17 WO PCT/CN2020/102871 patent/WO2021022995A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07282585A (en) * | 1994-04-06 | 1995-10-27 | Hitachi Ltd | Semiconductor device |
| US20030156462A1 (en) * | 2002-02-18 | 2003-08-21 | Lim Hyun-Wook | Memory devices having power supply routing for delay locked loops that counteracts power noise effects |
| US20100201454A1 (en) * | 2009-02-09 | 2010-08-12 | Yi-Tzu Chen | VDD-Independent Oscillator Insensitive to Process Variation |
| US20150048873A1 (en) * | 2013-08-16 | 2015-02-19 | Apple Inc. | Power Source for Clock Distribution Network |
| CN104977977A (en) * | 2014-04-02 | 2015-10-14 | 联发科技股份有限公司 | Clock tree circuit and memory controller |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021022995A1 (en) * | 2019-08-07 | 2021-02-11 | 北京智芯微电子科技有限公司 | Soc chip, and method for reducing clock signal noise in soc chip |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2021022995A1 (en) | 2021-02-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8482114B2 (en) | Impedance optimized chip system | |
| US9448947B2 (en) | Inter-chip memory interface structure | |
| US8797096B2 (en) | Crosstalk compensation for high speed, reduced swing circuits | |
| US20190220560A1 (en) | Die resistance-capacitance extraction and validation | |
| CN110619136A (en) | Method for optimizing voltage drop of wire bonding packaging chip and application | |
| EP3239865A1 (en) | Method for analyzing ir drop and electromigration of ic | |
| US8735184B2 (en) | Equalization in proximity communication | |
| CN110399331A (en) | The method of clock signal noise is reduced in SOC chip and SOC chip | |
| CN103999010B (en) | Distributed electrostatic discharge protection equipment, system and tablet computing device | |
| US10169527B2 (en) | Accurate statistical timing for boundary gates of hierarchical timing models | |
| CN105425898A (en) | Low-power embedded system | |
| CN107817477B (en) | A kind of signal source system and implementation method of Radar Displaying Console System | |
| KR20120021782A (en) | Burn-in test apparatus for the transmission of high speed signal and burn-in board therefor and method for the transmission of high speed signal | |
| US10665515B1 (en) | Selective per die performance binning | |
| US10528698B2 (en) | Enhancing integrated circuit noise performance | |
| CN104115086B (en) | The non-linear termination of input/output architecture on packaging part | |
| EP4105762A1 (en) | Supply voltage control systems and methods for integrated circuits | |
| CN109375757A (en) | Circuit, computing equipment and task processing system | |
| US11632103B2 (en) | High-speed voltage clamp for unterminated transmission lines | |
| US6721931B2 (en) | System and method for simplifying clock construction and analysis | |
| Cheng et al. | Two Optimization Ways of DDR3 Transmission Line Equal-Length Wiring Based on Signal Integrity | |
| US20150161067A1 (en) | Reduced-area architecture for asymmetric interconnect | |
| US20230131938A1 (en) | Techniques For Accessing Memory Circuits | |
| US20210305142A1 (en) | Packaged integrated device | |
| CN105870118A (en) | Distributed type electrostatic discharge protection for input/output framework on packaging body |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20191101 |