CN110362521B - MCU + FPGA architecture two-way serial data communication system and method - Google Patents
MCU + FPGA architecture two-way serial data communication system and method Download PDFInfo
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- G06F13/38—Information transfer, e.g. on bus
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- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
The invention provides a two-way serial data communication system based on an MCU + FPGA architecture, which comprises an MCU, an FPGA, a first serial communication peripheral and a second serial communication peripheral; the MCU and the FPGA are in DATA communication in a parallel bus mode, signals between the MCU and the FPGA comprise a clock CLK, a reset RESETn, a chip selection signal CSn, a read signal XRDn, a write signal XWEn, a 7-bit ADDRESS bus ADDRESS [6 ] and a 16-bit DATA bus DATA [15 ].
Description
Technical Field
The invention relates to the technical field of electric data transmission, in particular to a two-way serial data communication system and a two-way serial data communication method based on an MCU + FPGA architecture.
Background
An FPGA (Field-Programmable gate array) internally includes three parts, namely a Configurable Logic Block (CLB), an Input/Output Block (IOB) and an Interconnect (Interconnect), and has the characteristics of shortest design cycle, lowest development cost, minimum risk and the like, and is widely applied to the fields of high-speed interface circuit design, digital signal processing and the like of communication equipment. In many application occasions, the FPGA needs to be designed and applied in combination with an MCU (Micro Controller Unit), the MCU is mainly used for system flow control and specific algorithm operation, and the FPGA can be used for extending and supporting peripherals, such as serial peripherals. The parallel data communication has the characteristic of high transmission efficiency, so the parallel data communication is often applied to the data communication between the FPGA and the MCU.
In some application occasions, a combination control system such as an MCU + FPGA is required to support different serial peripherals in different application scenarios, and if software programs of the MCU and the FPGA are required to be modified to adapt to peripherals with different communication protocols, the workload is undoubtedly increased and the process is complicated.
Disclosure of Invention
The invention aims to provide a two-way serial data communication system and a two-way serial data communication method based on an MCU + FPGA architecture.
The first technical scheme for realizing the purpose of the invention is as follows: a two-way serial data communication system based on an MCU + FPGA architecture comprises an MCU, an FPGA, a first serial communication peripheral and a second serial communication peripheral; the MCU and the FPGA are in DATA communication in a parallel bus mode, signals between the MCU and the FPGA comprise a clock CLK, a reset RESETn, a chip selection signal CSn, a read signal XRDn, a write signal XWEn, a 7-bit ADDRESS bus ADDRESS [6 ] and a 16-bit DATA bus DATA [15 ].
By adopting the system, at one end of the MCU, the file main.c declares and defines a variable Flag _ firstIn at a variable initialization part of a main function main () to indicate whether to enter or call a function GetDevice () for the first time, declares and defines a pointer variable Initial, the pointer points to an address space where the peripheral FPGA is located, the Initial value is given to be a variable DeviceType and is used for initializing and selecting a currently effective serial communication peripheral number, and the function GetDevice () is defined to realize parallel data communication between the MCU and the FPGA.
By adopting the system, a tri-state gate is arranged in front of each serial communication peripheral and a file module SerialCom is arranged at the rear end of each serial communication peripheral; the data flow and port mapping of the two-way serial communication system are described as follows, wherein Device1 is a first serial communication peripheral, and Device2 is a second serial communication peripheral:
(1) When the Device _ type =1, the DATA bus DATA value is transmitted to the signal Device1_ dataIn through the tri-state gate K1, and the signal Device1_ dataIn is mapped to the port Device1_ dataIn of the module Device1; the module Device1 receives and judges the value of the port Device1_ dataIn, stores the corresponding instruction data into the signal tx1_ buffer, and sends the signal tx1 to the port sout1, and the port sout1 is mapped with the port of the signal sout1 of the file module SerialCom; the signal sout1 of the module SerialCom is mapped with the port sout, and the module Device1 instruction data is sent to the peripheral system through the port sout;
(2) When Device _ type =1, the signal sin1 of the module SerialCom is port-mapped with the port sin, and the signal sin1 is port-mapped with the port sin1 of the module Device1, and the SerialCom module receives data of the peripheral system through the port sin; a module Device1 port sin1 stores data of the peripheral system into a signal rx1_ buffer, and port Device1_ dataOut is subjected to port mapping with a signal Device1_ dataOut of a SerialCom module; the signal device1_ dataOut transfers the DATA of the peripheral system to the DATA bus DATA through the tri-state gate k 1;
(3) When Device _ type =2, the DATA bus DATA value is transmitted to the signal Device2_ dataIn through the tri-state gate K2, and the signal Device2_ dataIn is mapped with the port Device2_ dataIn of the module Device 2; the module Device2 receives and judges the value of the port Device2_ dataIn, stores the corresponding instruction data into the signal tx2_ buffer, and sends the signal tx2_ buffer to the port sout2, and the port sout2 is mapped with the signal sout2 of the file module SerialCom; the signal sout2 of the module SerialCom is mapped with the port sout, and the module Device2 instruction data is sent to the peripheral system through the port sout;
(4) When Device _ type =2, the signal sin2 of the module SerialCom is mapped with the port sin and the signal sin2 is mapped with the port sin2 of the module Device2, and the SerialCom module receives data of the peripheral system through the port sin; a module Device2 port sin2 stores data of the peripheral system into a signal rx2_ buffer, and port Device2_ dataOut is subjected to port mapping with a signal Device2_ dataOut of a SerialCom module; the signal device2_ dataOut passes the DATA of the peripheral system to the DATA bus DATA through the tri-state gate k 2.
The second technical scheme for realizing the aim of the invention is as follows: a data communication method according to the above-mentioned system, the first serial communication peripheral sends the order to the peripheral through Process11 and Process12, receive the peripheral data through Process13 and Process 14; wherein
(1) The execution flow of the Process11 is as follows:
a1, detecting whether a rising edge event of a clock CLK, namely rising _ edge (CLK), if so, sequentially executing steps B1, C1 and D1;
b1, judging whether device1_ dataIn is 1, if so, giving instruction data cmd1 to a signal tx1_ buffer, setting a sending state flag tx1_ rdy to 1, and then executing a step D1; if not, sequentially executing the steps C1 and D1 in sequence;
c1, judging whether device1_ dataIn is 2, if so, giving instruction data cmd2 to a signal tx1_ buffer, setting a sending state flag tx1_ rdy to 1, and then executing the step D1; if not, executing the step D1;
d1, judging whether the signal tx1_ rdy is 1, and if so, setting the signal tx1_ rdy to 0;
(2) The execution flow of the Process12 is as follows:
and A2, detecting whether a clock CLK rising edge event exists, and if so, executing the step B2.
B2, detecting whether a signal tx1_ rdy rising edge event exists, and if so, sending data of the signal tx1_ buffer to a port sout1;
(3) The execution flow of the Process13 is as follows:
and A3, detecting whether a rising edge event of the clock CLK, namely rising _ edge (CLK), and if so, sequentially executing the steps B3 and C3.
B3, detecting whether a data frame receiving start signal start falling edge event exists, if so, receiving the data of the port sin1 into a signal rx1_ buffer, setting the signal rx1_ rdy to be 1, and then executing the step (3); if not, step C3 is executed.
C3, judging whether the signal rx1_ rdy is 1, if so, setting the signal rx1_ rdy to 0;
(4) The execution flow of the Process14 is as follows:
a4, detecting whether a clock CLK rising edge event exists or not, and if so, executing a step B4;
b4, detecting whether a signal rx1_ rdy rising edge event exists, and if so, transmitting data of the signal rx1_ buffer to a port device1_ dataOut;
the second serial communication peripheral sends an instruction to the peripheral through a Process21 and a Process22, and receives peripheral data through a Process23 and a Process 24; wherein
(5) The execution flow of the Process21 is as follows:
and A5, detecting whether a clock CLK rising edge event exists or not, and if so, sequentially executing the steps B5, C5 and D5 in sequence.
B5, judging whether the device2_ dataIn is 1, if so, giving instruction data cmd3 to a signal tx2_ buffer, setting a sending state flag tx2_ rdy to be 1, and then executing a step D5; if not, the steps C5 and D5 are sequentially executed in sequence.
C5, judging whether the device2_ dataIn is 2, if so, giving an instruction data cmd4 to a signal tx2_ buffer, setting a sending state flag tx2_ rdy to be 1, and then executing a step D5; if not, executing the step D5;
d5, judging whether the signal tx2_ rdy is 1 or not, and if so, setting the signal tx2_ rdy to be 0;
(6) The execution flow of the Process22 is as follows:
and A6, detecting whether a clock CLK rising edge event exists, and if so, executing the step B6.
And B6, detecting whether the signal tx2_ rdy has a rising edge event, and if so, sending the data of the signal tx2_ buffer to the port sout2.
(7) The execution flow of the Process23 is as follows:
and A7, detecting whether a rising edge event of the clock CLK, namely rising _ edge (CLK), and if so, sequentially executing the steps B7 and C7 in sequence.
B7, detecting whether there is a data frame receiving start signal start falling edge event, if yes, receiving the data of port sin2 into signal rx2_ buffer, and setting signal rx2_ rdy to 1, then executing step C7; if not, step C7 is performed.
And C7, judging whether the signal rx2_ rdy is 1, and if so, setting the signal rx2_ rdy to be 0.
(8) The execution flow of the Process24 is as follows:
a8 detects whether a clock CLK rising edge event exists, and if so, step B8 is executed.
B8 detects whether there is a rising edge event of the rx2 rdy signal, and if so, transmits the data of the rx2 buffer to the port device2_ dataOut.
The invention can conveniently select and configure serial peripheral serial numbers, and saves the workload of adapting peripheral protocols by modifying software programs. The invention has clear software architecture and clear data flow, and is easy to expand and support more peripherals.
The invention is further described in the following with reference to the drawings.
Drawings
Fig. 1 is an electrical connection diagram of a two-way serial communication system.
Fig. 2 is a diagram illustrating a reference data frame format.
Fig. 3 is a schematic diagram of a transmitting and receiving mechanism of MCU command data.
Fig. 4 is a schematic diagram of the FPGA serial communication peripheral module 1.
Fig. 5 is a schematic diagram of the FPGA serial communication peripheral module 2.
Fig. 6 is a schematic diagram of FPGA data transceiving and serial peripheral port mapping.
Fig. 7 is a schematic diagram of data flow and port mapping for a two-way serial communication system.
Detailed Description
As shown in fig. 1, the circuit system according to the present invention includes a micro control unit MCU, an FPGA, a first serial peripheral Device1 and a second serial peripheral Device2. The micro control unit MCU and the FPGA are in DATA communication in a parallel bus mode, and signals between the MCU and the FPGA comprise a clock CLK, a reset RESETn, a chip selection signal CSn, a read signal XRDn, a write signal XWEn, a 7-bit ADDRESS bus ADDRESS [6 ] and a 16-bit DATA bus DATA [ 0]. The FPGA carries out data communication with the first serial peripheral Device1 and the second serial peripheral Device2 in a serial bus mode, received data are represented by RD, and sent data are represented by TD.
As shown in fig. 2, it is assumed that the serial communication data Frame format in the present invention is 18bit/Frame, and includes 1 Start code, 3 Sink codes, 2 Frame codes, 3 Device addresses, 5 Command codes, 3 CRC codes, and 1 Stop code.
As shown in fig. 3, at the micro control unit MCU side, the file main.c lists the partial contents and implementation of the main function main (). A unit type variable Flag _ firstIn is declared and defined in the variable initialization part, with an initial value of 0, the function of this variable being to indicate whether it is the first entry or call to the function GetDevice (). And declaring and defining a pointer variable Initial, wherein the pointer points to an address space where the peripheral FPGA is located, an Initial value is given as a variable DeviceType, and the Initial value is used for initializing and selecting the currently valid serial communication peripheral serial number, namely the FPGA is set to be in communication with the serial peripheral Device1 or in communication with the serial peripheral Device2.
The setting of the variable DeviceType can be realized by a system human-computer interaction unit (such as a key and a liquid crystal display), and the content of the part is not described here.
A function GetDevice () is defined, the type of the return value is void, and the parameter is void. Assuming that a pointer variable DeviceAddress is defined before, the pointer points to an address space where the peripheral FPGA is located, and the variable Cmd is a data request instruction sent by the MCU to the FPGA. It is assumed that a pointer variable Devicedata is defined before, the pointer points to the address space where the peripheral FPGA is located, and the variable ReadData is used for storing data in the address Devicedata where the peripheral FPGA is located.
The execution flow of the function GetDevice () is as follows:
(1) Sending a data request command Cmd to the address DeviceAddress where the peripheral FPGA is located;
(2) Judging whether to enter or call a function GetDevice () for the first time, if so, setting a state Flag _ firstIn to 1 and exiting the function GetDevice (); if not, reading Devicedata of the address of the peripheral FPGA and saving the Devicedata to a variable ReadData.
As shown in fig. 4, the peripheral module Device1 includes a Process1, a Process2, a Process3 and a Process4, all driven by a clock CLK event, the processes Process1 and Process2 Process transmission of peripheral instructions, and the processes Process3 and Process4 Process reception of peripheral data.
The execution flow of the Process1 is as follows:
(1) detecting whether a rising edge event of a clock CLK, namely rising _ edge (CLK), and if so, sequentially executing the steps (2), (3) and (4).
(2) Judging whether device1_ dataIn is 1, if so, giving instruction data cmd1 to a signal tx1_ buffer (tx 1_ buffer < = cmd 1), setting a transmission status flag tx1_ rdy to 1 (tx 1_ rdy < = '1'), and then executing the step (4); if not, the steps (3) and (4) are sequentially executed in sequence.
(3) Judging whether the device1_ dataIn is 2, if so, giving instruction data cmd2 to a signal tx1_ buffer (tx 1_ buffer < = cmd 2), setting a sending status flag tx1_ rdy to 1 (tx 1_ rdy < = '1'), and then executing the step (4); if not, step (4) is performed.
(4) And judging whether the signal tx1_ rdy is 1, and if so, setting the signal tx1_ rdy to 0, namely tx1_ rdy < = '0'.
The execution flow of the Process2 is as follows:
(1) Whether a rising edge event of the clock CLK, namely rising _ edge (CLK), exists is detected, and if so, step (2) is executed.
(2) Whether a signal tx1_ rdy rising edge event, namely rising _ edge (tx 1_ rdy), exists or not is detected, and if yes, the data of the signal tx1_ buffer is sent to the port sout1.
The execution flow of the Process3 is as follows:
(1) detecting whether a rising edge event of a clock CLK (namely rising _ edge (CLK) exists, and if yes, sequentially executing the steps (2) and (3) in sequence.
(2) Detecting whether a data frame receiving start signal start falling edge event, namely falling _ edge (start), exists, if so, receiving data of the port sin1 into a signal rx1_ buffer (rx 1_ buffer < = sin 1), setting the signal rx1_ rdy to 1 (rx 1_ rdy < = '1'), and then executing the step (3); if not, step (3) is executed.
(3) It is determined whether the rx1_ rdy signal is 1, and if so, the rx1_ rdy signal is set to 0, i.e., rx1_ rdy < = '0'.
The execution flow of the Process4 is as follows:
(1) Whether a rising edge event of the clock CLK, namely rising _ edge (CLK), exists is detected, and if so, step (2) is executed.
(2) Detecting whether there is a rising edge event of the rx1_ rdy signal, namely rising _ edge (rx 1_ rdy), if yes, sending the data of the rx1_ buffer signal to the port device1_ dataOut.
As shown in fig. 5, the peripheral module Device2 includes a Process1, a Process2, a Process3 and a Process4, all driven by a clock CLK event, the processes Process1 and Process2 Process transmission of peripheral instructions, and the processes Process3 and Process4 Process reception of peripheral data.
The execution flow of the Process1 is as follows:
(1) detecting whether a rising edge event of a clock CLK, namely rising _ edge (CLK), and if so, sequentially executing the steps (2), (3) and (4).
(2) Judging whether device2_ dataIn is 1, if so, giving instruction data cmd3 to a signal tx2_ buffer (tx 2_ buffer < = cmd 3), setting a transmission status flag tx2_ rdy to 1 (tx 2_ rdy < = '1'), and then executing the step (4); if not, the steps (3) and (4) are sequentially executed in sequence.
(3) Judging whether the device2_ dataIn is 2, if so, giving instruction data cmd4 to a signal tx2_ buffer (tx 2_ buffer < = cmd 4), setting a sending status flag tx2_ rdy to 1 (tx 2_ rdy < = '1'), and then executing the step (4); if not, step (4) is performed.
(4) And judging whether the signal tx2_ rdy is 1, and if so, setting the signal tx2_ rdy to 0, namely tx2_ rdy < = '0'.
The execution flow of the Process2 is as follows:
(1) Whether a rising edge event of the clock CLK, namely rising _ edge (CLK), exists is detected, and if so, step (2) is executed.
(2) Whether a signal tx2_ rdy rising edge event, namely rising _ edge (tx 2_ rdy), exists is detected, and if yes, the data of the signal tx2_ buffer is sent to the port sout2.
The execution flow of the Process3 is as follows:
(1) detecting whether a rising edge event of a clock CLK, namely rising _ edge (CLK), and if so, sequentially executing the steps (2) and (3).
(2) Detecting whether a falling edge event of a start signal start of data frame reception exists, namely falling _ edge (start), if so, receiving data of a port sin2 into a signal rx2_ buffer (rx 2_ buffer < = sin 2), setting the signal rx2_ rdy to 1 (rx 2_ rdy < = '1'), and then executing the step (3); if not, step (3) is executed.
(3) It is determined whether the signal rx2_ rdy is 1, and if so, the signal rx2_ rdy is set to 0, i.e., rx2_ rdy < = '0'.
The execution flow of the Process4 is as follows:
(1) Whether a rising edge event of the clock CLK, namely rising _ edge (CLK), exists is detected, and if so, step (2) is executed.
(2) Whether a rising edge event of the rx2_ rdy signal, namely rising _ edge (rx 2_ rdy), occurs is detected, and if so, data of the rx2_ buffer signal is transmitted to the port device2_ dataOut.
Vhd is a top-level file module in FPGA software, including Process1, process2, process3, component Device1 and instantiation, and component Device2 and instantiation, as shown in fig. 6. Wherein:
the driving events of the Process1 are a chip selection signal CSn and a write signal XWEn, and the execution flow is as follows:
(1) detecting whether the chip select signal CSn AND the write signal XWEn are simultaneously low level, namely CSn = '0' AND XWEn = '0', if yes, executing the steps (2), (3) AND (4) in sequence;
(2) Judging whether the value of the ADDRESS bus is a variable Initial value, namely ADDRESS = Initial, if so, assigning the value of the DATA bus to a signal device _ type (device _ type < = DATA), setting the signal flag _ type to 1 (flag _ type < = 1'), then exiting the Process1, and if not, sequentially executing the steps (3) and (4) in sequence.
The signal Device _ type is used for indicating the serial peripheral serial number mapped and communicated with the FPGA currently, the value of the signal can be 1 or 2, and when the value of the signal is 1, the signal indicates that the Device mapped and communicated with the FPGA currently is a peripheral Device1; otherwise, when the signal value is 2, it indicates that the Device2 is currently mapped and communicated with the FPGA. The signal flag _ type is used for indicating whether an MCU setting selection current peripheral number instruction is received currently, and when the flag _ type is 1, the MCU setting selection current peripheral number instruction is received.
(3) And (4) judging whether the value of the signal device _ type is 1, if so, giving the value of the data bus to the signal device1_ dataIn and exiting the Process1, and if not, executing the step (4).
(4) And judging whether the value of the signal device _ type is 2 or not, if so, giving the value of the data bus to the signal device2_ dataIn and exiting the Process1.
The driving events of the Process2 are a chip select signal CSn and a write signal XRDn, and the execution flow is as follows:
(1) detecting whether the chip select signal CSn AND the write signal XRDn are simultaneously low, i.e., CSn = '0' AND XRDn = '0', AND if so, sequentially performing steps (2) AND (3).
(2) And (3) judging whether the value of the signal device _ type is 1, if so, giving the value of the signal device1_ dataOut to the DATA bus DATA, exiting the Process2, and if not, executing the step (3).
(3) And judging whether the value of the signal device _ type is 2 or not, if so, giving the value of the signal device2_ dataOut to the DATA bus DATA, and exiting the Process2.
The driving event of the Process3 is a status signal flag _ type, and the execution flow is as follows:
(1) detecting whether a flag _ type rising edge event, namely, rising _ edge (flag _ type) exists, and if so, sequentially executing the steps (2), (3) and (4) in sequence.
(2) Judging whether the value of the signal device _ type is 1, if so, mapping the signal sout1 to the port sout, mapping the signal sin1 to the port sin, and executing the step (4); if not, executing the steps (3) and (4).
(3) It is determined whether the value of the signal device _ type is 2, and if so, the signal sout2 is mapped to the port sout, the signal sin2 is mapped to the port sin, and step (4) is performed.
(4) The signal flag _ type is assigned to 0, i.e., flag _ type < = '0'.
Component Device1 and instantiation, port sin1 mapped to signal sin1 of SerialCom, port sout1 mapped to signal sout1 of SerialCom, port Device1_ dataIn mapped to signal Device1_ dataIn of SerialCom, port Device1_ dataOut mapped to signal Device1_ dataOut of SerialCom, port CLK mapped to port CLK of SerialCom, and port RESETn mapped to port RESETn of SerialCom.
Component Device2 and instantiation, port sin2 mapped to signal sin2 of SerialCom, port sout2 mapped to signal sout2 of SerialCom, port Device2_ dataIn mapped to signal Device2_ dataIn of SerialCom, port Device2_ dataOut mapped to signal Device2_ dataOut of SerialCom, port CLK mapped to port CLK of SerialCom, and port RESETn mapped to port RESETn of SerialCom.
As shown in fig. 7, the diagram describes the data flow and port mapping of the two-way serial communication system of the present invention, which is specifically described as follows:
when the value of the signal Device _ type is equal to 1, that is, device _ type =1, the tri-state gate k1 is in the bidirectional conducting state, the DATA bus DATA value is stored in the signal Device1_ dataIn, and the signal Device1_ dataIn is port-mapped with the port Device1_ dataIn of the module Device 1. The module Device1 receives and judges the value of the port Device1_ dataIn, stores the corresponding instruction data into the signal tx1_ buffer, and sends the signal tx1 to the port sout1, and the port sout1 performs port mapping with the signal sout1 of the top-level file module SerialCom. Since Device _ type =1, the signal sout1 of the module SerialCom is port-mapped with the port sout, and Device1 instruction data is transmitted to the peripheral system through the port sout.
When Device _ type =1, the signal sin1 of the module SerialCom is port mapped with the port sin and the signal sin1 is port mapped with the port sin1 of the module Device1, the SerialCom module receiving data of the peripheral system through the port sin. The module Device1 port sin1 stores data of the peripheral system into the signal rx1_ buffer, and the port Device1_ dataOut is port-mapped with the signal Device1_ dataOut of the SerialCom module. The signal device1_ dataOut passes the DATA of the peripheral system to the DATA bus DATA through the tri-state gate k 1.
When the value of the signal Device _ type is equal to 2, i.e., device _ type =2, the tri-state gate k2 is in the bidirectional conducting state, the DATA bus DATA value is stored in the signal Device2_ dataIn, and the signal Device2_ dataIn is port-mapped with the port Device2_ dataIn of the module Device2. The module Device2 receives and judges the value of the port Device2_ dataIn, stores the corresponding instruction data into the signal tx2_ buffer, and sends the signal tx2_ buffer to the port sout2, and the port sout2 performs port mapping with the signal sout2 of the top-level file module SerialCom. Since Device _ type =2, the signal sout2 of the module SerialCom is port-mapped with the port sout, and Device2 instruction data is transmitted to the peripheral system through the port sout.
At Device _ type =2, the signal sin2 of the module SerialCom is port mapped with the port sin and the signal sin2 is port mapped with the port sin2 of the module Device2, and the SerialCom module receives data of the peripheral system through the port sin. The module Device2 port sin2 stores data of the peripheral system into the signal rx2_ buffer, and the port Device2_ dataOut is port-mapped with the signal Device2_ dataOut of the SerialCom module. The signal device2_ dataOut passes the DATA of the peripheral system to the DATA bus DATA through the tri-state gate k 2.
The data flow of the invention is clear and definite, and more peripheral protocols can be supported according to the mechanism extension.
Claims (3)
1. A two-way serial data communication system based on an MCU + FPGA architecture is characterized by comprising an MCU, an FPGA, a first serial communication peripheral and a second serial communication peripheral; wherein
DATA communication between the MCU and the FPGA is performed in the form of a parallel bus, and signals between them include a clock CLK, reset RESETn, a chip select signal CSn, a read signal XRDn, a write signal XWEn, a 7-bit ADDRESS bus ADDRESS [6 ] and a 16-bit DATA bus DATA [15,
the FPGA carries out data communication with the first communication peripheral and the second communication peripheral in a serial bus mode;
a tri-state gate is arranged in front of each serial communication peripheral, and a file module SerialCom is arranged at the rear end of each serial communication peripheral; the data flow and port mapping of the two-way serial communication system are described as follows, wherein Device1 is a first serial communication peripheral Device, and Device2 is a second serial communication peripheral Device:
(1) When the Device _ type =1, the DATA bus DATA value is transmitted to the signal Device1_ dataIn through the tri-state gate K1, and the signal Device1_ dataIn is mapped with the port Device1_ dataIn of the module Device1; the module Device1 receives and judges the value of the port Device1_ dataIn, stores the corresponding instruction data into the signal tx1_ buffer, and sends the signal tx1 to the port sout1, and the port sout1 is mapped with the port of the signal sout1 of the file module SerialCom; a signal sout1 of the module SerialCom is mapped with a port sout, and the module Device1 instruction data is sent to an external system through the port sout;
(2) When Device _ type =1, the signal sin1 of the module SerialCom is port-mapped with the port sin, and the signal sin1 is port-mapped with the port sin1 of the module Device1, and the SerialCom module receives data of the peripheral system through the port sin; a module Device1 port sin1 stores data of the peripheral system into a signal rx1_ buffer, and port Device1_ dataOut is subjected to port mapping with a signal Device1_ dataOut of a SerialCom module; the signal device1_ dataOut transfers the DATA of the peripheral system to the DATA bus DATA through the tri-state gate k 1;
(3) When Device _ type =2, the DATA bus DATA value is transmitted to the signal Device2_ dataIn through the tri-state gate K2, and the signal Device2_ dataIn is mapped to the port Device2_ dataIn of the module Device 2; the module Device2 receives and judges the value of the port Device2_ dataIn, stores the corresponding instruction data into the signal tx2_ buffer, and sends the signal tx2_ buffer to the port sout2, and the port sout2 is mapped with the signal sout2 port of the file module SerialCom; a signal sout2 of the module SerialCom is mapped with a port sout, and the module Device2 instruction data is sent to an external system through the port sout;
(4) When Device _ type =2, the signal sin2 of the module SerialCom is port-mapped with the port sin, and the signal sin2 is port-mapped with the port sin2 of the module Device2, and the SerialCom module receives data of the peripheral system through the port sin; a module Device2 port sin2 stores data of the peripheral system into a signal rx2_ buffer, and port Device2_ dataOut is subjected to port mapping with a signal Device2_ dataOut of a SerialCom module; the signal device2_ dataOut passes the DATA of the peripheral system to the DATA bus DATA through the tri-state gate k 2.
2. The system of claim 1, wherein, at the MCU side,
the file main.c is declared at the main function main () variable initialization part and defines a variable Flag _ firstIn for indicating whether the function GetDevice () is first entered or called,
declaring and defining a pointer variable Initial, wherein the pointer points to the address space where the peripheral FPGA is located, the Initial value is given as a variable DeviceType, the pointer variable Initial is used for initializing and selecting the currently effective serial communication peripheral number,
and defining a function GetDevice () to realize parallel data communication between the MCU and the FPGA.
3. A data communication method according to the system of claim 1, wherein the first serial communication peripheral device sends an instruction to the peripheral device through the Process11 and the Process12, and receives peripheral data through the Process13 and the Process 14; wherein
(1) The execution flow of the Process11 is as follows:
a1, detecting whether a rising edge event of a clock CLK, namely rising _ edge (CLK), if so, sequentially executing steps B1, C1 and D1;
b1, judging whether device1_ dataIn is 1, if so, giving instruction data cmd1 to a signal tx1_ buffer, setting a sending state flag tx1_ rdy to 1, and then executing a step D1; if not, sequentially executing the steps C1 and D1 in sequence;
c1, judging whether device1_ dataIn is 2, if so, giving instruction data cmd2 to a signal tx1_ buffer, setting a sending state flag tx1_ rdy to 1, and then executing the step D1; if not, executing the step D1;
d1, judging whether the signal tx1_ rdy is 1, and if so, setting the signal tx1_ rdy to 0;
(2) The execution flow of the Process12 is as follows:
a2, detecting whether a clock CLK rising edge event exists, and if so, executing a step B2;
b2, detecting whether a signal tx1_ rdy rising edge event exists, and if so, sending data of the signal tx1_ buffer to a port sout1;
(3) The execution flow of the Process13 is as follows:
a3, detecting whether a rising edge event of a clock CLK, namely rising _ edge (CLK), if so, sequentially executing steps B3 and C3;
b3, detecting whether a data frame receiving start signal start falling edge event exists, if so, receiving the data of the port sin1 into a signal rx1_ buffer, setting the signal rx1_ rdy to be 1, and then executing the step (3); if not, executing the step C3;
c3, judging whether the signal rx1_ rdy is 1, if so, setting the signal rx1_ rdy to 0;
(4) The execution flow of the Process14 is as follows:
a4, detecting whether a clock CLK rising edge event exists or not, and if so, executing a step B4;
b4, detecting whether a signal rx1_ rdy rising edge event exists, and if so, transmitting data of the signal rx1_ buffer to a port device1_ dataOut;
the second serial communication peripheral sends an instruction to the peripheral through a Process21 and a Process22, and receives peripheral data through a Process23 and a Process 24; wherein
(5) The execution flow of the Process21 is as follows:
a5, detecting whether a clock CLK rising edge event exists, and if so, sequentially executing steps B5, C5 and D5;
b5, judging whether the device2_ dataIn is 1, if so, giving the instruction data cmd3 to a signal tx2_ buffer, setting a sending state flag tx2_ rdy to 1, and then executing the step D5; if not, sequentially executing the steps C5 and D5 in sequence;
c5, judging whether the device2_ dataIn is 2, if so, giving the instruction data cmd4 to a signal tx2_ buffer, setting a sending state flag tx2_ rdy to 1, and then executing the step D5; if not, executing the step D5;
d5, judging whether the signal tx2_ rdy is 1, and if so, setting the signal tx2_ rdy to 0;
(6) The execution flow of the Process22 is as follows:
a6, detecting whether a clock CLK rising edge event exists, and if so, executing a step B6;
b6, detecting whether a signal tx2_ rdy rising edge event exists, and if so, sending data of the signal tx2_ buffer to a port sout2;
(7) The execution flow of the Process23 is as follows:
a7, detecting whether a rising edge event of a clock CLK (namely rising _ edge (CLK)) exists, and if yes, sequentially executing the steps B7 and C7 in sequence;
b7, detecting whether there is a data frame reception start signal start falling edge event, if yes, receiving the data of the port sin2 into the signal rx2_ buffer, setting the signal rx2_ rdy to 1, and then executing step C7; if not, executing the step C7;
c7, judging whether the signal rx2_ rdy is 1, and if so, setting the signal rx2_ rdy to 0;
(8) The execution flow of the Process24 is as follows:
a8, detecting whether a clock CLK rising edge event exists or not, and if so, executing a step B8;
b8 detects whether there is a rising edge event of the rx2 rdy signal, and if so, transmits the data of the rx2 buffer to the port device2_ dataOut.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7525360B1 (en) * | 2006-04-21 | 2009-04-28 | Altera Corporation | I/O duty cycle and skew control |
| CN101867452A (en) * | 2010-06-10 | 2010-10-20 | 国网电力科学研究院 | Communication method of serial real-time bus special in electricity |
| CN102760111A (en) * | 2012-06-27 | 2012-10-31 | 浙江大学 | FPGA-based (Field Programmable Gate Array) extended multi-serial port device and data receiving-transmitting method thereof |
| CN102831090A (en) * | 2012-05-07 | 2012-12-19 | 中国科学院空间科学与应用研究中心 | Address line for space-borne DSP (Digital Signal Processor) and FPGA (Field Programmable Gate Array) communication interfaces and optimization method for address line |
| WO2018018978A1 (en) * | 2016-07-25 | 2018-02-01 | 深圳市中兴微电子技术有限公司 | Universal serial bus controller verification method, system and device |
| CN109656856A (en) * | 2018-11-23 | 2019-04-19 | 中国船舶重工集团公司第七0七研究所 | Multiplex bus and multiplex bus interconnect device and method are realized using FPGA |
| CN109857685A (en) * | 2018-12-06 | 2019-06-07 | 积成电子股份有限公司 | A kind of implementation method of MPU and FPGA expanding multiple serial ports |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5407633B2 (en) * | 2008-07-28 | 2014-02-05 | 株式会社リコー | Communication apparatus, communication system having the same, and communication method |
-
2019
- 2019-06-30 CN CN201910581913.XA patent/CN110362521B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7525360B1 (en) * | 2006-04-21 | 2009-04-28 | Altera Corporation | I/O duty cycle and skew control |
| CN101867452A (en) * | 2010-06-10 | 2010-10-20 | 国网电力科学研究院 | Communication method of serial real-time bus special in electricity |
| CN102831090A (en) * | 2012-05-07 | 2012-12-19 | 中国科学院空间科学与应用研究中心 | Address line for space-borne DSP (Digital Signal Processor) and FPGA (Field Programmable Gate Array) communication interfaces and optimization method for address line |
| CN102760111A (en) * | 2012-06-27 | 2012-10-31 | 浙江大学 | FPGA-based (Field Programmable Gate Array) extended multi-serial port device and data receiving-transmitting method thereof |
| WO2018018978A1 (en) * | 2016-07-25 | 2018-02-01 | 深圳市中兴微电子技术有限公司 | Universal serial bus controller verification method, system and device |
| CN109656856A (en) * | 2018-11-23 | 2019-04-19 | 中国船舶重工集团公司第七0七研究所 | Multiplex bus and multiplex bus interconnect device and method are realized using FPGA |
| CN109857685A (en) * | 2018-12-06 | 2019-06-07 | 积成电子股份有限公司 | A kind of implementation method of MPU and FPGA expanding multiple serial ports |
Non-Patent Citations (1)
| Title |
|---|
| 基于FPGA和FIFO技术的多串口系统设计与实现;陈标龙等;《计算机测量与控制》;20131025(第10期);第2835-2837页 * |
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