CN110351509B - Multi-channel high-bandwidth data exchange method based on FPGA (field programmable Gate array) stack - Google Patents
Multi-channel high-bandwidth data exchange method based on FPGA (field programmable Gate array) stack Download PDFInfo
- Publication number
- CN110351509B CN110351509B CN201810290500.1A CN201810290500A CN110351509B CN 110351509 B CN110351509 B CN 110351509B CN 201810290500 A CN201810290500 A CN 201810290500A CN 110351509 B CN110351509 B CN 110351509B
- Authority
- CN
- China
- Prior art keywords
- data
- unit
- fpga
- slice
- serdes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/60—Network structure or processes for video distribution between server and client or between remote clients; Control signalling between clients, server and network components; Transmission of management data between server and client, e.g. sending from server to client commands for recording incoming content stream; Communication details between server and client
- H04N21/63—Control signaling related to video distribution between client, server and network components; Network processes for video distribution between server and clients or between remote clients, e.g. transmitting basic layer and enhancement layers over different transmission paths, setting up a peer-to-peer communication via Internet between remote STB's; Communication protocols; Addressing
- H04N21/643—Communication protocols
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/80—Generation or processing of content or additional data by content creator independently of the distribution process; Content per se
- H04N21/83—Generation or processing of protective or descriptive data associated with content; Content structuring
- H04N21/845—Structuring of content, e.g. decomposing content into time segments
- H04N21/8456—Structuring of content, e.g. decomposing content into time segments by decomposing the content in the time domain, e.g. in time segments
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The invention provides a multi-channel high-bandwidth data exchange method based on FPGA (field programmable gate array) stacking, wherein the used equipment comprises a switching board card, M input board cards, K output board cards and a synchronous control board card, and the method specifically comprises the following steps: 1) each data packaging unit in the M input board cards packages and packs the data stream of each path of data input signal according to a data packaging protocol; 2) the data slicing and distributing unit is used for dividing each data packet sent by the data packaging unit into N parts and respectively transmitting the N parts to the N FPGA data slicing and exchanging units; … …, respectively; 5) and the data sending unit removes the encapsulation information including the message header from the data packet sent by the data slice recombining unit and restores the data packet into the original data signal for output according to the same data encapsulation protocol as the input board card. The data exchange method breaks through the bottleneck that the total port scale is limited due to the limitation of the single-chip port scale, has a simple and reasonable structure, and greatly improves the bandwidth and the transmission efficiency of the single port.
Description
Technical Field
The invention belongs to the technical field of video processing, and particularly relates to a multi-channel high-bandwidth data exchange method based on FPGA (field programmable gate array) stacking.
Background
With the continuous progress of science and technology, especially in the field of professional audio and video, with the popularization and explosive growth of the application of high-data volume services such as high-definition, ultra-high-definition and very-high-definition videos, higher demands are made on the bandwidth and the scale of a high-speed data exchange matrix in the market. Conventional switching matrices are extremely challenging both in scale and bandwidth.
The conventional data exchange methods are roughly classified into the following 3 types: 1) based on dedicated ASIC switching chips, such as Crosspoint series chips from Mindspeed (later purchased by MACOM). The switching scale can be from 16 × 16 to 288 × 288, and the single-path bandwidth can be varied from 3.2Gbps to 12.8 Gbps. A larger scale can be achieved with a single chip or by stacking multiple chips; 2) based on PCI-E structure, for example, the invention "CN 201621394802 is a PCI-E matrix-based network high-speed data transmission system architecture"; 3) packet switched over ethernet or the like. However, the prior art has the disadvantages that: 1) a solution based on a dedicated ASIC switching chip. If a single chip solution is adopted, the size of the chip itself is limited, for example, the maximum size can only be 288 × 288. If a multi-chip stacking scheme is adopted, the cost is high, and the hardware design is complex. In addition, the number of suppliers for producing the ultra-large-capacity private exchange chip is limited, which easily causes difficulty in purchasing or price risk; 2) a solution based on the PCI-E architecture. Capacity is limited by the size of the switch chip itself. b. All input output ports share the internal bus bandwidth. When the total port number reaches a certain degree, the bandwidth of a single port is obviously reduced, and the bandwidth of each port is difficult to guarantee; 3) packet switched over ethernet or the like. As with the PCI-E architecture, sharing internal bus bandwidth, transmission delay is large and not fixed. There is a risk of packet loss when the throughput of the exchanged data is high.
In the prior art, a data exchange system based on an FPGA architecture exists, for example, the invention "CN 201320825955 digital video exchange system", the disclosed technical scheme is based on a single FPGA architecture, the total capacity and the single port bandwidth are limited by the technology and process of the FPGA, the requirement of ultra-large scale and ultra-high single port bandwidth is difficult to be simultaneously met, and the system is mainly used for small-scale data exchange. Although the document also mentions that a plurality of digital video switching systems can form a larger-scale data switching system, the document does not disclose a specific structure of the digital video switching system with a plurality of single FPGA architectures, and the multi-system overlapping manner certainly has the problems of complex and repeated structure, low transmission efficiency and low fault tolerance rate, and does not provide a specific data switching method.
Disclosure of Invention
The invention aims to provide a multi-channel high-bandwidth data exchange method based on FPGA (field programmable gate array) stacking, which breaks through the bottleneck that the total port scale is limited due to the limitation of the single-chip port scale, has a simple and reasonable structure, and greatly improves the single-port bandwidth and the transmission efficiency.
The invention has the specific technical scheme that the multichannel high-bandwidth data exchange method based on FPGA stacking is characterized in that equipment used by the method comprises a switching board card, M input board cards, K output board cards and a synchronous control board card, wherein the switching board card is used for carrying out exchange transmission on input video signals and comprises N FPGA data slice exchange units, each FPGA data slice exchange unit is provided with M SERDES receiving ports and K SERDES sending ports, the input board card comprises a data slice and distribution unit and N data encapsulation units respectively connected with the data slice and distribution unit, each data encapsulation unit is connected with one path of data input signals, each data slice and distribution unit is provided with N SERDES sending ports respectively connected with the N FPGA data slice exchange units through a transmission line SERDES, and the output board card comprises a data slice recombination unit and N data sending ports respectively connected with the data slice recombination unit Each data sending unit is used for outputting a path of data signal, the data slice recombining unit is provided with N SERDES receiving ports which are respectively connected with N FPGA data slice exchanging units through an SERDES transmission line, the synchronous control board card comprises a synchronous unit and a control unit which are respectively connected with each FPGA data slice exchanging unit, the data slice and distributing unit and the data slice recombining unit,
the method specifically comprises the following steps:
1) each data packaging unit in the M input board cards packages and packs the data stream of each path of data input signal according to a data packaging protocol, and then transmits the data stream to a corresponding data slicing and distributing unit;
2) the data slicing and distributing unit is used for dividing each data packet sent by the data packaging unit into N parts and respectively transmitting the N parts to the N FPGA data slicing and exchanging units, and the data slicing and distributing unit receives a periodic synchronous signal for synchronously controlling the board card and aligns SERDES data sent to the FPGA data slicing and exchanging units according to the signal;
3) the N FPGA data slice switching units receive periodic synchronous signals of the synchronous control board card and determine slice positions in an SERDES data stream according to the signals, then switching transmission of video signals is completed according to a unified switching table configured by the control unit, and the video signals are recombined into the SERDES data stream to be sent to an output board card;
4) each data slice recombination unit in the K output board cards receives N paths of SERDES data from N FPGA data slice exchange units, slice positions in an SERDES data stream are determined according to periodic synchronous signals of the synchronous control board cards, the data slice recombination units recombine the N data slices into data packets, and then the recombined data packets are sent to corresponding data sending units;
5) and the data sending unit removes the encapsulation information including the message header from the data packet sent by the data slice recombining unit and restores the data packet into the original data signal for output according to the same data encapsulation protocol as the input board card.
Further, the data encapsulation protocol in step 1) adopts a CPRI protocol.
Furthermore, the control unit is connected with the upper computer, and can modify the switching table.
Furthermore, when M is equal to K, the functions of the pair of input board card and the output board card may be implemented by using the same input/output board card, where the input/output board card includes a slicing and recombining unit having functions of a data slicing and distributing unit and a data slicing and recombining unit, and a packaging and sending unit connected to the slicing and recombining unit and having functions of a data packaging unit and a data sending unit.
Further, the data input signal includes video, audio, control data, infrared, serial port, switching value, ethernet, optical fiber, HDBaseT, mouse keyboard or USB2.0 signal.
Furthermore, the FPGA chip in the FPGA data slice exchanging unit is a Virtex UltraScale + XCVU7P model chip of XILINX corporation or a stratx 10GX1650 model chip of Intel corporation.
Furthermore, the data slice and distribution unit and the data slice recombination unit adopt a Kintex-7XC7K160T model chip of XILINX company or an Arria 10GX160 model chip of Intel company.
Furthermore, the data packaging unit and the data sending unit adopt a Kintex-7XC7K160T model chip of XILINX company or an Arria 10GX160 model chip of Intel company.
The invention has the advantages that 1) the multichannel high-bandwidth data exchange method based on FPGA stacking can be suitable for a plurality of pieces of FPGA stacking as the core device combination of data exchange, can realize parallel slice transmission of high-speed data signal flow under the control of a synchronous signal, and can realize high-speed data signal switching under the condition of not reducing the bandwidth of any port at any end; 2) the CPRI protocol is adopted to slice the data stream, so that parallel transmission and alignment are convenient, the input and output bandwidth of the switching matrix can be expanded by adopting the stacking of a plurality of simple FPGA, and the problems of bandwidth limitation and signal delay of the existing switching method are effectively solved; 3) the input/output board card and the multiple FPGA stacked data exchange core devices applicable to the method have simple connection structure, reasonable optimization, high transmission efficiency, low power, environmental protection and energy conservation; 4) The data exchange method can be suitable for a bidirectional exchange mode shared by the input and output board cards, a unidirectional exchange mode separated by the input and output board cards and an asymmetric exchange mode with unequal input channels and output channels; 5) the data exchange system applicable to the method can adopt common FPGA devices in the market, and is convenient to purchase and stock. No risk is caused by the change of a single supplier. The multi-channel high-bandwidth data switching method based on FPGA stacking can realize matrix switching with switching scale of 640 multiplied by 640 or more and single-port bandwidth of 12.5Gbps or more.
Drawings
FIG. 1 is a flow chart of the multi-channel high-bandwidth data exchange method based on FPGA stacking of the present invention;
FIG. 2 is a schematic structural diagram of a data exchange system to which the multi-channel high-bandwidth data exchange method based on FPGA stacking of the present invention is applied;
fig. 3 is a schematic structural diagram of a 320 × 320 bidirectional switching matrix applicable to the FPGA stacking-based multi-channel high-bandwidth data exchange method of the present invention.
Detailed Description
The technical scheme of the invention is further described in the following with the accompanying drawings of the specification.
As shown in fig. 1, the method for exchanging multi-channel high-bandwidth data based on FPGA stacking of the present invention specifically includes the following steps:
1) each data packaging unit in the M input board cards packages and packs the data stream of each path of data input signal and transmits the data stream to a corresponding data slicing and distributing unit according to a data packaging protocol which adopts a CPRI protocol;
2) the data slicing and distributing unit is used for dividing each data packet sent by the data packaging unit into N parts and respectively transmitting the N parts to the N FPGA data slicing and exchanging units, and the data slicing and distributing unit receives a periodic synchronous signal for synchronously controlling the board card and aligns SERDES data sent to the FPGA data slicing and exchanging units according to the signal;
3) the N FPGA data slice switching units receive periodic synchronous signals of the synchronous control board card and determine slice positions in an SERDES data stream according to the signals, then complete switching transmission of video signals according to a unified switching table configured by the control unit, and recombine the video signals into the SERDES data stream to be sent to the output board card, and the control unit is connected with an upper computer and can modify the switching table;
4) each data slice recombination unit in the K output board cards receives N paths of SERDES data from N FPGA data slice exchange units, slice positions in an SERDES data stream are determined according to periodic synchronous signals of the synchronous control board cards, the data slice recombination units recombine the N data slices into data packets, and then the recombined data streams are sent to corresponding data sending units;
5) and the data sending unit removes the encapsulation information including the message header from the data packet sent by the data slice recombining unit and restores the data packet into the original data signal for output according to the same data encapsulation protocol as the input board card.
As shown in fig. 2, the data exchange system applicable to the multi-channel high-bandwidth data exchange method based on FPGA stacking of the present invention includes a switch board, 80 input boards, 80 output boards, and a synchronization control board.
The switching board card is used for carrying out switching transmission on input video signals and comprises 8 FPGA data slice switching units, and each FPGA data slice switching unit is provided with 80 SERDES receiving ports and 80 SERDES sending ports. The FPGA chip in the FPGA data slice exchange unit is a Virtex UltraScale + XCVU7P model chip of XILINX company or a Stratix10GX1650 model chip of Intel company.
The input board card comprises a data slicing and distributing unit and 8 data packaging units respectively connected with the data slicing and distributing unit, each data packaging unit is connected with one path of data input signal, and the data slicing and distributing unit is provided with 8 SERDES transmitting ports respectively connected with 8 FPGA data slicing exchange units through an SERDES transmission line. The data input signal comprises video, audio, control data, infrared, serial ports, switching value, Ethernet, optical fiber, HDBaseT, mouse keyboard or USB2.0 signal.
The output board card comprises a data slice recombination unit and 8 data transmitting units respectively connected with the data slice recombination unit, each data transmitting unit is used for outputting a path of data signal, and the data slice recombination unit is provided with 8 SERDES receiving ports respectively connected with 8 FPGA data slice exchange units through SERDES transmission lines.
The data slicing and distributing unit and the data slicing and recombining unit adopt a Kintex-7XC7K160T model chip of XILINX company or an Arria 10GX160 model chip of Intel company. The data packaging unit and the data sending unit adopt a Kintex-7XC7K160T model chip of XILINX company or an Arria 10GX160 model chip of Intel company, and the packaging protocol is CPRI.
The synchronous control board card comprises a synchronous unit and a control unit which are respectively connected with each FPGA data slice exchange unit, each data slice and distribution unit and each data slice recombination unit.
The synchronization unit and the control unit adopt Zynq-7000 XC7Z015 model chips of XILINX company.
As shown in fig. 3, the functions of the pair of input board card and output board card can be implemented by using the same input/output board card, where the input/output board card includes a slicing and recombining unit having the functions of a data slicing and distributing unit and a data slicing and recombining unit, and a packaging and sending unit connected to the slicing and recombining unit and having the functions of a data packaging unit and a data sending unit. Thus, 40 input/output boards and 8 switching boards are provided. The switching output of 320 x 320 paths of signals can be realized.
The hardware switching system applicable to the multi-channel high-bandwidth data exchange method based on FPGA stacking can also be applied to data transmission and exchange of the following processing method. For example, all video data are sent to the 1 st data slice exchange unit through the 1 st SERDES, all audio is sent to the 2 nd data slice exchange unit through the 2 nd SERDES, all USB2.0 data are sent to the 3 rd data slice exchange unit through the 3 rd SERDES, and so on, and the 8 th data type is sent to the 8 th data slice exchange unit through the 8 th SERDES. And different types of data are respectively exchanged through the data slice exchange units connected with the data slice exchange units and then are sent to the data slice recombination unit of the output card. The switching tables on the data slice switching unit are configured by the upper computer through the control unit, and the 8 switching tables can be the same or completely different, namely, the video data is provided with the video switching table, the audio data is provided with the audio switching table, and the USB2.0 data is provided with the USB2.0 switching table. And the data recombination unit on the output card receives the data from different data slice exchange units, performs repackaging and outputs the data. Through the exchange mode, different types of data such as video, audio or USB2.0 can be independently switched respectively, and then flexible combination of data types such as video sources and audio sources is carried out again. Namely, the function of the common audio and video mixing processing matrix in the market is completed.
Claims (7)
1. A multi-channel high-bandwidth data exchange method based on FPGA stacking is characterized in that equipment used by the method comprises a switching board card, M input board cards, K output board cards and a synchronous control board card, wherein the switching board card is used for carrying out exchange transmission on input video signals and comprises N FPGA data slice exchange units, each FPGA data slice exchange unit is provided with M SERDES receiving ports and K SERDES sending ports, the input board card comprises a data slice and distribution unit and N data encapsulation units respectively connected with the data slice and distribution unit, each data encapsulation unit is connected with a path of data input signal, the data slice and distribution unit is provided with N SERDES sending ports respectively connected with the N FPGA data slice exchange units through an SERDES transmission line, the output board card comprises a data slice recombination unit and N data sending units respectively connected with the data slice recombination unit, each data transmitting unit is used for outputting a path of data signal, the data slice recombining unit is provided with N SERDES receiving ports which are respectively connected with N FPGA data slice exchanging units through an SERDES transmission line, the synchronous control board card comprises a synchronous unit and a control unit which are respectively connected with each FPGA data slice exchanging unit, the data slice and distributing unit and the data slice recombining unit,
the method specifically comprises the following steps:
1) each data packaging unit in the M input board cards packages and packs the data stream of each path of data input signal according to a data packaging protocol, and then transmits the data stream to a corresponding data slicing and distributing unit;
2) the data slicing and distributing unit is used for dividing each data packet sent by the data packaging unit into N parts and respectively transmitting the N parts to the N FPGA data slicing and exchanging units, and the data slicing and distributing unit receives a periodic synchronous signal for synchronously controlling the board card and aligns SERDES data sent to the FPGA data slicing and exchanging units according to the signal;
3) the N FPGA data slice switching units receive periodic synchronous signals of the synchronous control board card and determine slice positions in an SERDES data stream according to the signals, then switching transmission of video signals is completed according to a unified switching table configured by the control unit, and the video signals are recombined into the SERDES data stream to be sent to an output board card;
4) each data slice recombination unit in the K output board cards receives N paths of SERDES data from N FPGA data slice exchange units, slice positions in an SERDES data stream are determined according to periodic synchronous signals of the synchronous control board cards, the data slice recombination units recombine the N data slices into data packets, and then the recombined data streams are sent to corresponding data sending units;
5) and the data sending unit removes the encapsulation information including the message header from the data packet sent by the data slice recombining unit and restores the data packet into the original data signal for output according to the same data encapsulation protocol as the input board card.
2. The method for multi-channel high-bandwidth data exchange based on FPGA stacking as claimed in claim 1, wherein the data encapsulation protocol in step 1) is CPRI protocol.
3. The method as claimed in claim 2, wherein the control unit is connected to an upper computer, and can modify the switching table.
4. The method as claimed in claim 1, wherein the data input signal comprises video, audio, control data, infrared, serial port, switching value, ethernet, optical fiber, HDBaseT, mouse keyboard or USB2.0 signal.
5. The method as claimed in claim 1, wherein the FPGA chip in the FPGA data slice switching unit is a Virtex UltraScale + XCVU7P model chip from XILINX or a Stratix10GX1650 model chip from Intel.
6. The method as claimed in claim 1, wherein the data slicing and distributing unit and the data slicing and recombining unit are respectively a chip model of Kintex-7XC7K160T from XILINX or a chip model of Arria 10GX160 from Intel.
7. The method as claimed in claim 1, wherein the data encapsulation unit and the data transmission unit use a chip model of Kintex-7XC7K160T from XILINX or a chip model of Arria 10GX160 from Intel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810290500.1A CN110351509B (en) | 2018-04-03 | 2018-04-03 | Multi-channel high-bandwidth data exchange method based on FPGA (field programmable Gate array) stack |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810290500.1A CN110351509B (en) | 2018-04-03 | 2018-04-03 | Multi-channel high-bandwidth data exchange method based on FPGA (field programmable Gate array) stack |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110351509A CN110351509A (en) | 2019-10-18 |
| CN110351509B true CN110351509B (en) | 2021-12-14 |
Family
ID=68172734
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810290500.1A Active CN110351509B (en) | 2018-04-03 | 2018-04-03 | Multi-channel high-bandwidth data exchange method based on FPGA (field programmable Gate array) stack |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110351509B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110971545A (en) * | 2019-11-29 | 2020-04-07 | 中国电子科技集团公司第五十四研究所 | Design method of multichannel ultra-large capacity data exchange architecture |
| CN114884903B (en) * | 2022-04-29 | 2023-06-02 | 绿盟科技集团股份有限公司 | Data processing method, field programmable gate array chip and network security device |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60230782A (en) * | 1984-04-10 | 1985-11-16 | ピエール ソルリオ | Exchange system having video exchange matrix |
| CN102223490A (en) * | 2011-06-22 | 2011-10-19 | 上海博康智能网络科技有限公司 | Digital switching matrix supporting synchronic switching and synchronic switching method of digital image |
| CN103220473A (en) * | 2012-01-20 | 2013-07-24 | 北京凯新创达科技发展有限公司 | Stackable high-definition video matrix |
| CN203645775U (en) * | 2013-12-13 | 2014-06-11 | 杭州中威电子股份有限公司 | Digital video exchange system |
| CN104010140A (en) * | 2014-05-29 | 2014-08-27 | 杭州中威电子股份有限公司 | Real-time high bandwidth video exchange system and method |
| CN204350147U (en) * | 2015-01-26 | 2015-05-20 | 深圳市创维群欣安防科技有限公司 | Mixed video control device and display device |
| CN105721795A (en) * | 2016-01-21 | 2016-06-29 | 西安诺瓦电子科技有限公司 | Video matrix stitching device and switching bottom plate thereof |
| CN205584346U (en) * | 2015-12-31 | 2016-09-14 | 大连捷成科技有限公司 | Be applied to audio matrix device of many forms matrix |
| TWM535913U (en) * | 2016-09-26 | 2017-01-21 | 宏正自動科技股份有限公司 | Video matrix controller |
| CN107707841A (en) * | 2017-06-16 | 2018-02-16 | 深圳朗田亩半导体科技有限公司 | A kind of matrix switcher |
| WO2018193750A1 (en) * | 2017-04-18 | 2018-10-25 | 国立研究開発法人産業技術総合研究所 | Video conferencing system |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6721312B2 (en) * | 2001-06-01 | 2004-04-13 | Pluris, Inc. | Method and apparatus for improving data transmission in router fabric cards through pseudo-synchronous data switching |
| JP5604827B2 (en) * | 2009-08-21 | 2014-10-15 | ソニー株式会社 | Transmitting apparatus, receiving apparatus, program, and communication system |
| US8503539B2 (en) * | 2010-02-26 | 2013-08-06 | Bao Tran | High definition personal computer (PC) cam |
| CN107105229B9 (en) * | 2011-04-14 | 2020-03-31 | 杜比实验室特许公司 | Image decoding method, video decoder, and non-transitory computer-readable storage medium |
| JP6467680B2 (en) * | 2014-01-10 | 2019-02-13 | パナソニックＩｐマネジメント株式会社 | File generation method and file generation apparatus |
| CN104065948A (en) * | 2014-06-19 | 2014-09-24 | 杭州立体世界科技有限公司 | Programmable logic device special for high-definition naked eye portable three-dimensional film-television player |
| CN204887266U (en) * | 2015-08-25 | 2015-12-16 | 深圳市智敏科技有限公司 | Can input security protection device of multichannel TVI signal |
-
2018
- 2018-04-03 CN CN201810290500.1A patent/CN110351509B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60230782A (en) * | 1984-04-10 | 1985-11-16 | ピエール ソルリオ | Exchange system having video exchange matrix |
| CN102223490A (en) * | 2011-06-22 | 2011-10-19 | 上海博康智能网络科技有限公司 | Digital switching matrix supporting synchronic switching and synchronic switching method of digital image |
| CN103220473A (en) * | 2012-01-20 | 2013-07-24 | 北京凯新创达科技发展有限公司 | Stackable high-definition video matrix |
| CN203645775U (en) * | 2013-12-13 | 2014-06-11 | 杭州中威电子股份有限公司 | Digital video exchange system |
| CN104010140A (en) * | 2014-05-29 | 2014-08-27 | 杭州中威电子股份有限公司 | Real-time high bandwidth video exchange system and method |
| CN204350147U (en) * | 2015-01-26 | 2015-05-20 | 深圳市创维群欣安防科技有限公司 | Mixed video control device and display device |
| CN205584346U (en) * | 2015-12-31 | 2016-09-14 | 大连捷成科技有限公司 | Be applied to audio matrix device of many forms matrix |
| CN105721795A (en) * | 2016-01-21 | 2016-06-29 | 西安诺瓦电子科技有限公司 | Video matrix stitching device and switching bottom plate thereof |
| TWM535913U (en) * | 2016-09-26 | 2017-01-21 | 宏正自動科技股份有限公司 | Video matrix controller |
| WO2018193750A1 (en) * | 2017-04-18 | 2018-10-25 | 国立研究開発法人産業技術総合研究所 | Video conferencing system |
| CN107707841A (en) * | 2017-06-16 | 2018-02-16 | 深圳朗田亩半导体科技有限公司 | A kind of matrix switcher |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110351509A (en) | 2019-10-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11070437B2 (en) | Network interconnect as a switch | |
| US8971321B2 (en) | System and method for accelerating and decelerating packets | |
| US9609400B2 (en) | Reconfigurable and variable-rate shared multi-transponder architecture for flexible ethernet-based optical networks | |
| US10313768B2 (en) | Data scheduling and switching method, apparatus, system | |
| JP5859002B2 (en) | Scalable interconnect module with flexible channel coupling | |
| CN108307129A (en) | A kind of multi-channel optical fibre video switching system based on FC-AV agreements | |
| CN102098453A (en) | Video streaming control system of multi-screen processor cascading extended system | |
| CN110351509B (en) | Multi-channel high-bandwidth data exchange method based on FPGA (field programmable Gate array) stack | |
| CN102318283A (en) | A method of data delivery across a network fabric in a router or Ethernet bridge | |
| CN104780333A (en) | High-bandwidth video source interface adaptation device based on FPGA (Field Programmable Gate Array) | |
| RU2007111857A (en) | RING NETWORK, COMMUNICATION DEVICE AND OPERATIONAL MANAGEMENT METHOD USED FOR THE RING NETWORK AND COMMUNICATION DEVICE | |
| CN103490961A (en) | Network equipment | |
| CN103530245A (en) | SRIO interconnection exchanging device based on field programmable gate array (FPGA) | |
| CN108809642A (en) | A kind of encryption certification high-speed transfer implementation method of multi-channel data 10,000,000,000 based on FPGA | |
| WO2013159501A1 (en) | Data transmission system, data interface device and data transmission method used among multiple servers | |
| CN104918024B (en) | Crosspoint matrix systems and its data processing method | |
| CN102308538B (en) | Message processing method and device | |
| CN209151300U (en) | A kind of T-type distribution Ethernet line concentrator | |
| CN102655470B (en) | The method and system of traffic scheduling is realized at optical transfer network interior joint | |
| CN116055425B (en) | Internet of things hardware platform | |
| WO2023283893A1 (en) | Data exchange device and method | |
| WO2014198156A1 (en) | Method, device and system for sharing optical module | |
| CN106227155B (en) | A kind of satellite antenna servo controller Multi-serial port real-time communication control system and method | |
| CN215121003U (en) | 4K four-in four-out HDMI matrix system | |
| WO2023060604A1 (en) | Exchange apparatus, exchange method, and exchange device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |