CN110333965B - Solid state disk controller device and solid state disk data verification method - Google Patents
Solid state disk controller device and solid state disk data verification method Download PDFInfo
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- CN110333965B CN110333965B CN201910461738.0A CN201910461738A CN110333965B CN 110333965 B CN110333965 B CN 110333965B CN 201910461738 A CN201910461738 A CN 201910461738A CN 110333965 B CN110333965 B CN 110333965B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention provides a solid state disk controller device and a solid state disk data verification method, wherein the verification method comprises the following steps: in the running process of the solid state disk, the controller monitors the bit error number of the effective information area of the solid state disk; reducing the length of an effective information area mapped by an ECC area by a preset step length when the controller determines that the bit error number reaches an error-correcting number threshold corresponding to a preset ECC algorithm; the controller shifts the data of the effective information area according to the length of the effective information area mapped by each reduced ECC area, adds the ECC area newly and recalculates the check value of each ECC area. According to the invention, the length of the effective information area is reduced, the ECC error correction capability is improved, and the service life of the solid state disk is prolonged.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a solid state disk controller device and a solid state disk data verification method.
Background
Solid state disks are gradually replacing mechanical hard disks due to high-speed reading and writing performance and low failure rate, and become mainstream storage devices. The solid state disk mainly corrects errors of stored data through an error checking and correcting (Error Correcting Code, ECC) module, the error rate of the stored data gradually rises along with the increase of the service time of the solid state disk, and when the bit number of the errors exceeds the ECC error correction capability, uncorrectable errors occur, so that the solid state disk cannot be used any more.
Chinese patent CN105280239B discloses a method for dynamically implementing an ECC check code of a solid state disk, which presets a multi-level ECC check code rate for the solid state disk, and increases the first-level ECC check code rate in an ECC check code rate table when an uncorrectable ECC error occurs or when a condition that one ECC check code rate unit is changed triggers as the working time of the solid state disk increases, so as to perform addition/check of the ECC check code.
In theory, the above patent can exchange for a longer service life of the solid state disk with a certain storage capacity loss by increasing the check code length in multiple stages. However, a high requirement is put forward on the controller of the solid state disk, especially for the content of the ECC module in the form of firmware, the implementation logic is not too complex, the hardware overhead for implementing the multi-level check code is very high, and if the method provided in chinese patent CN105280239B is implemented, the controller needs to be modified in a complex manner.
Disclosure of Invention
Therefore, the present invention provides a solid state disk controller device and a method for verifying data of a solid state disk, so as to solve or at least alleviate at least one of the above problems.
According to an aspect of the embodiment of the present invention, there is provided a method for verifying data of a solid state disk, which is suitable for being executed in a computing device, and the method includes:
in the running process of the solid state disk, the controller monitors the bit error number of the effective information area of the solid state disk;
reducing the length of an effective information area mapped by an ECC area by a preset step length when the controller determines that the bit error number reaches an error-correcting number threshold corresponding to a preset ECC algorithm;
the controller shifts the data of the effective information area according to the length of the effective information area mapped by each reduced ECC area, adds the ECC area newly and recalculates the check value of each ECC area.
Preferably, the method further comprises:
the method comprises the steps of calculating a preset step length according to a preset hard disk working bit error formula and a preset time interval between two reduction step lengths, wherein the hard disk working bit error formula records the relation between various hard disk use parameters such as hard disk writing times, storage time and the like and hard disk bit error digits, and is used for calculating a change value of the number of hard disk bit error digits corresponding to the time interval between the preset two reduction step lengths after setting the parameters such as the writing times, the storage time and the like of a hard disk in the time interval between the preset two reduction step lengths, and calculating the preset step length according to the change value of the number of hard disk bit error digits and an error-correctable digit threshold corresponding to an ECC algorithm.
Preferably, the method further comprises:
the controller calculates the number of the newly-increased ECC areas after reducing the length of the effective information area mapped by each ECC area by a preset step length in advance according to the current solid state disk capacity, the length of the effective information area mapped by each ECC area and the preset step length;
calculating reserved space for the newly added ECC area according to the number of the newly added ECC areas and the preset ECC area length;
and when reporting the available space to an upper layer application, reporting the numerical value obtained by subtracting the reserved space for the newly added ECC area from the current solid state disk capacity to the upper layer application.
Preferably, recalculating the check value of each ECC region includes:
and after 0 or 1 of the preset step number is supplemented for each effective information area, calculating the check value of each corresponding ECC area.
Preferably, the method further comprises:
if the check value of each ECC area is calculated after the 0 of the preset step number is supplemented for each effective information area, the 0 of the preset step number is supplemented for each effective information area in the data check period;
and if the check value of each corresponding ECC area is calculated after the 1 s of the preset step number are supplemented for each effective information area, supplementing the 1 s of the preset step number for each effective information area during data check.
Preferably, the method further comprises:
the controller maintains a record table comprising the bit error bit number and the length of the effective information area of a plurality of blocks or pages in a cache, and when the controller determines that the bit error bit number reaches the threshold of the error-correctable bit number corresponding to the preset ECC algorithm, the controller performs the operation of reducing the length of the effective information area mapped by the ECC area by a preset step length in the block or page where the bit error bit number reaches the threshold of the error-correctable bit number corresponding to the preset ECC algorithm.
Preferably, the method further comprises:
when the controller writes data into any block or page, acquiring the record of the effective information area length in the record table, supplementing 0 or 1 of the corresponding number according to the record of the effective information area length in the record table, and calculating the check value of the corresponding ECC area;
and when checking any block or page, the controller acquires the record of the length of the effective information area in the record table, supplements 0 or 1 of the corresponding number according to the record of the length of the effective information area in the record table, and checks the effective information area.
Preferably, the controller pre-calculates the space for the newly added ECC area within each block or page; when reporting the available space to the upper layer application, the values obtained by subtracting the space for the newly added ECC area from the capacity in each block or page are summed and reported to the upper layer application.
According to an aspect of an embodiment of the present invention, there is provided a solid state disk controller device including:
the monitoring unit is used for monitoring bit error bits of the effective information area of the solid state disk in the running process of the solid state disk;
the length control unit is used for reducing the length of the effective information area mapped by the ECC area by a preset step length whenever the bit error number reaches the threshold of the error-correctable number corresponding to the preset ECC algorithm;
and the operation unit is used for shifting the data of the effective information area according to the length of the effective information area mapped by each reduced ECC area, adding an ECC area newly and recalculating the check value of each ECC area.
Preferably, the length control unit is configured to, when determining the preset step size, specifically:
the method comprises the steps of calculating a preset step length according to a preset hard disk working bit error formula and a preset time interval between two reduction step lengths, wherein the hard disk working bit error formula records the relation between various hard disk use parameters such as hard disk writing times, storage time and the like and hard disk bit error digits, and is used for calculating a change value of the number of hard disk bit error digits corresponding to the time interval between the preset two reduction step lengths after setting the parameters such as the writing times, the storage time and the like of a hard disk in the time interval between the preset two reduction step lengths, and calculating the preset step length according to the change value of the number of hard disk bit error digits and an error-correctable digit threshold corresponding to an ECC algorithm.
Preferably, the method further comprises:
the capacity calculation unit is used for calculating the number of the newly-added ECC areas after the length of the effective information area mapped by each ECC area is reduced by a preset step length according to the current solid state disk capacity, the length of the effective information area mapped by each ECC area and the preset step length in advance;
calculating reserved space for the newly added ECC area according to the number of the newly added ECC areas and the preset ECC area length;
and when reporting the available space to an upper layer application, reporting the numerical value obtained by subtracting the reserved space for the newly added ECC area from the current solid state disk capacity to the upper layer application.
Preferably, when the operation unit is configured to recalculate the check value of each ECC area, the operation unit includes:
and after 0 or 1 of the preset step number is supplemented for each effective information area, calculating the check value of each corresponding ECC area.
Preferably, the operation unit is further configured to:
if the check value of each ECC area is calculated after the 0 of the preset step number is supplemented for each effective information area, the 0 of the preset step number is supplemented for each effective information area in the data check period;
and if the check value of each corresponding ECC area is calculated after the 1 s of the preset step number are supplemented for each effective information area, supplementing the 1 s of the preset step number for each effective information area during data check.
Preferably, the method further comprises:
a maintenance unit for maintaining a record table including the number of bit errors and the length of the effective information area of a plurality of blocks or pages in a buffer; the length control unit reduces the length of an effective information area mapped by an ECC area by a preset step length according to blocks or pages of which the bit error number reaches an error correction number threshold corresponding to a preset ECC algorithm; the operation unit shifts the data of the effective information area according to the length of the effective information area mapped by each reduced ECC area for the block or page with the bit error number reaching the threshold of the error correction number corresponding to the preset ECC algorithm, newly adds the ECC area and recalculates the check value of each ECC area.
Preferably, when writing data into any block or page, the operation unit acquires the record of the effective information area length in the record table, supplements 0 or 1 of the corresponding number according to the record of the effective information area length in the record table, and calculates the check value of the corresponding ECC area; and when any block or page is verified, acquiring the record of the length of the effective information area in the record table, supplementing 0 or 1 corresponding to the record of the length of the effective information area in the record table, and verifying the effective information area.
Preferably, the capacity calculation unit is further configured to calculate in advance a space for the newly added ECC area within each block or page; when reporting the available space to the upper layer application, the values obtained by subtracting the space for the newly added ECC area from the capacity in each block or page are summed and reported to the upper layer application.
According to the invention, the verification capability is improved by shortening the length of the effective information area and increasing the number of ECC verification areas, so that the service life of the solid state disk is prolonged; compared with the prior art, the ECC check code length is increased, the mode of setting the multi-stage check code is adopted, the ECC check module is not required to be obviously changed, the implementation is simpler, and the hardware cost is lower.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
FIG. 1 is a schematic flow chart of a method for verifying data of a solid state disk according to the present invention;
FIG. 2 is a schematic diagram of a method for verifying data of a solid state disk according to the present invention;
fig. 3 shows a schematic structural diagram of a solid state disk controller device according to the present invention.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will be more clearly understood, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description. It should be noted that, in the case of no conflict, the embodiments of the present application and the features in the embodiments may be combined with each other.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those described herein, and therefore the scope of the present invention is not limited to the specific embodiments disclosed below.
As shown in fig. 1, a method for verifying data of a solid state disk according to an embodiment of the present invention includes:
s110, in the running process of the solid state disk, the controller monitors the bit error number of the effective information area of the solid state disk;
s120, reducing the length of an effective information area mapped by an ECC area by a preset step length when the controller determines that the bit error number reaches an error correction number threshold corresponding to a preset ECC algorithm;
s130, the controller shifts the data of the effective information area according to the length of the effective information area mapped by each reduced ECC area, adds the ECC area newly and recalculates the check value of each ECC area.
The data area of the solid state disk is divided into two areas, one of which is an effective information area for storing information symbols including various systems and user data, and the other is an ECC area for storing check symbols for checking the information symbols of the effective information area. In the checking process, the controller finds and records the bit error number, namely the bit error number appearing in a corresponding section of effective information area checked by a section of ECC area.
In step S110, during the running process of the solid state disk, the controller monitors the bit error number of the effective information area of the solid state disk. Specifically, when the controller reads data, the controller can record the bit error number of the verified effective information area, and can randomly select the effective information area to verify and record the bit error number in the idle period of the hard disk.
In step S120, each time the controller determines that the number of bit errors reaches the threshold of the error correctable number corresponding to the preset ECC algorithm, the length of the effective information area mapped by the ECC area is reduced by a preset step, for example, the step may be 50, 100, 150 bytes. The specific step size value should be calculated in combination with the hard disk working bit error formula such that the time interval between the two reduced steps is equal to the preset time interval. The time interval between the two narrowing steps is not too short, as the overhead of data migration and recomputing the check is increased by the narrowing step. For example, the preset time interval may be 3 months. The hard disk working bit error formula records the relation between various hard disk use parameters such as hard disk writing times, storage time and the like and hard disk bit error bit numbers, and is determined through multiple tests in advance, and the formulas of different manufacturers and different hard disk product tests are different. After setting parameters such as the writing times and the storage time of the hard disk in the next appointed time, the corresponding change of the bit error number of the hard disk in the next appointed time can be calculated, and then the corresponding step value is calculated according to the change of the bit error number of the hard disk, so that after the step is reduced, the bit error number of the effective information area of the hard disk in the preset time interval does not exceed the threshold of the error correction bit number corresponding to the length of the ECC area. For example: according to the hard disk working bit error formula, the writing times and the storage time in the next three months are input, the bit error number is calculated to be increased from 60 to 90 in the next three months, the increasing number is 30, the increasing rate is 50%, the effective information area length is 1041 bytes, the ECC check threshold is 60, and then the step size of reducing the effective information area length is 1041 (1-60/90) =347.
The threshold number of error-correctable bits corresponding to the ECC algorithm is determined by a preset ECC algorithm and the length of the ECC area, and common ECC algorithms include BCH (Bose, ray-chaudhuri, hocquenghem), LPDC (Low Density Parity Check, low density check code), and the like. For example, the currently used ECC algorithm can correct errors of 100 bits of the effective information area at maximum, and then the threshold of the number of error-correctable bits is 100 bits. The verification performance can be improved by increasing the length of the verification code of the ECC algorithm, namely the length of the ECC area, but the controller supporting the dynamic ECC verification code is complex to realize, so the method is not adopted, the length of the effective information area mapped by the ECC area is reduced by a preset step length, and the verification performance is improved by reducing the length of the effective information area.
In step S130, the controller shifts the effective information area data according to the length of the effective information area mapped by each ECC area after shrinking, newly adds an ECC area, and recalculates the check value of each ECC area. When the length of the effective information area is reduced, more ECC areas are filled in each page and each block, so that the data are completely shifted, and the check value of the ECC area corresponding to the shifted effective information area needs to be recalculated.
When the effective information area data is shifted in step S130, it is necessary to ensure that the hard disk has a sufficient space. For example, if 10M of ECC area is newly added, the hard disk should reserve 10M of free area for writing no data. Because the step length of reducing the length of the effective information area mapped by the ECC area is predetermined, correspondingly, the space required by the newly added ECC area can be calculated in advance, and the controller reserves the corresponding space which does not allow the upper layer application to write data, thereby avoiding the condition of losing in the data displacement process.
Specifically, to ensure that the hard disk reserves enough space for adding a new ECC area, the following steps are performed before step S110: the controller calculates the number of the newly-increased ECC areas after reducing the length of the effective information area mapped by each ECC area by a preset step length in advance according to the current solid state disk capacity, the length of the effective information area mapped by each ECC area and the preset step length; calculating reserved space for the newly added ECC area according to the number of the newly added ECC areas and the preset ECC area length; and when reporting the available space to an upper layer application, reporting the numerical value obtained by subtracting the reserved space for the newly added ECC area from the current solid state disk capacity to the upper layer application.
In step S130, the check value of each ECC area is recalculated, including: and after 0 or 1 of the preset step number is supplemented for each effective information area, calculating the check value of each corresponding ECC area. If the check value of each ECC area is calculated after the 0 of the preset step number is supplemented for each effective information area, the 0 of the preset step number is supplemented for each effective information area in the data check period; and if the check value of each corresponding ECC area is calculated after the 1 s of the preset step number are supplemented for each effective information area, supplementing the 1 s of the preset step number for each effective information area during data check.
As shown in fig. 2, as time increases, the effective information area length is continuously reduced, the ECC area length is unchanged, and the number is increased, so that the verification performance is improved without obviously modifying the ECC module of the controller.
When the service life of the hard disk is prolonged by improving the verification means in the prior art, the aim of improvement is to process the whole disk, and the invention also provides a verification mode aiming at pages or blocks, namely a controller monitors the bit error bit number of the effective information area of each page or block of the solid state disk; reducing the length of an effective information area mapped by an ECC area of a page or a block by a preset step length when the controller determines that the bit error number of the page or the block reaches the threshold of the error correction bit number corresponding to a preset ECC algorithm; the controller shifts the effective information area data according to the length of the effective information area mapped by each reduced ECC area, newly adds an ECC area, and recalculates the check value of each ECC area of a page or block.
In order to implement the method, the solid state disk reserves enough redundant bits for each page or block for writing in the newly added ECC area.
The record table maintained by the controller not only records the bit error number of the effective information area of a plurality of blocks or pages, but also records the length of the effective information area for each page or block respectively, or directly records the bit number to be filled when the controller performs ECC check.
For example: for some blocks, the length of the effective information area is reduced twice, and 0 or 1 of twice step size is needed to be supplemented during ECC check; for some blocks, the length of the effective information area is not reduced, and the verification is still performed according to the initial situation, and 0 or 1 is not required to be supplemented.
In fact, the aging speeds of all flash memory units in the solid state disk are not consistent, so that the invention proposes to use different effective information area lengths for checking each page and each block for distinguishing processing, and can maximally utilize the capacity of the solid state disk and maximally ensure the checking speed of the solid state disk.
As shown in fig. 3, the present invention further provides a solid state disk controller device, including:
the monitoring unit 210 is configured to monitor a bit error number of the effective information area of the solid state disk during the operation process of the solid state disk;
a length control unit 220, configured to reduce the length of the effective information area mapped by the ECC area by a preset step length whenever it is determined that the number of bit errors reaches the threshold of the number of bits that can be corrected corresponding to the preset ECC algorithm;
an operation unit 230, configured to shift the effective information area data according to the length of the effective information area mapped by each ECC area after shrinking, newly add an ECC area, and recalculate the check value of each ECC area.
Preferably, the method further comprises:
the capacity calculation unit is used for calculating the number of the newly-added ECC areas after the length of the effective information area mapped by each ECC area is reduced by a preset step length according to the current solid state disk capacity, the length of the effective information area mapped by each ECC area and the preset step length in advance;
calculating reserved space for the newly added ECC area according to the number of the newly added ECC areas and the preset ECC area length;
and when reporting the available space to an upper layer application, reporting the numerical value obtained by subtracting the reserved space for the newly added ECC area from the current solid state disk capacity to the upper layer application.
Preferably, when the operation unit is configured to recalculate the check value of each ECC area, the operation unit includes:
and after 0 or 1 of the preset step number is supplemented for each effective information area, calculating the check value of each corresponding ECC area.
Preferably, the operation unit is specifically configured to:
if the check value of each ECC area is calculated after the 0 of the preset step number is supplemented for each effective information area, the 0 of the preset step number is supplemented for each effective information area in the data check period;
and if the check value of each corresponding ECC area is calculated after the 1 s of the preset step number are supplemented for each effective information area, supplementing the 1 s of the preset step number for each effective information area during data check.
Preferably, the method further comprises:
a maintenance unit for maintaining a bit error number record table including an effective information area of a block or page; the length control unit reduces the length of an effective information area mapped by an ECC area by a preset step length according to blocks or pages of which the bit error number reaches an error correction number threshold corresponding to a preset ECC algorithm; the operation unit shifts the data of the effective information area according to the length of the effective information area mapped by each reduced ECC area for the block or page with the bit error number reaching the threshold of the error correction number corresponding to the preset ECC algorithm, newly adds the ECC area and recalculates the check value of each ECC area.
Those of ordinary skill in the art will appreciate that all or part of the steps of the various methods of the above embodiments may be implemented by a program that instructs associated hardware, the program may be stored in a computer readable storage medium including Read-Only Memory (ROM), random access Memory (Random Access Memory, RAM), programmable Read-Only Memory (Programmable Read-Only Memory, PROM), erasable programmable Read-Only Memory (Erasable Programmable Read Only Memory, EPROM), one-time programmable Read-Only Memory (OTPROM), electrically erasable programmable Read-Only Memory (EEPROM), compact disc Read-Only Memory (Compact Disc Read-Only Memory, CD-ROM) or other optical disk Memory, magnetic disk Memory, tape Memory, or any other medium that can be used for carrying or storing data that is readable by a computer.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A method for verifying data of a solid state disk is characterized in that,
comprising the following steps: in the running process of the solid state disk, the controller monitors the bit error number of the effective information area of the solid state disk; reducing the length of an effective information area mapped by an ECC area by a preset step length when the controller determines that the bit error number reaches an error-correcting number threshold corresponding to a preset ECC algorithm; the controller shifts the data of the effective information area according to the length of the effective information area mapped by each reduced ECC area, newly adds the ECC area and recalculates the check value of each ECC area;
the step of determining the preset step length comprises the following steps: and calculating the preset step length according to a preset hard disk working bit error formula and a time interval between preset two reduction step lengths, wherein the hard disk working bit error formula records the relation between the hard disk writing times and the storage time and the hard disk bit error number and is used for calculating the change value of the corresponding hard disk bit error number in the time interval between the preset two reduction step lengths after setting the writing times and the storage time parameters of the hard disk in the time interval between the preset two reduction step lengths and calculating the preset step length according to the change value of the hard disk bit error number and the error-correctable bit number threshold corresponding to the ECC algorithm.
2. The method as recited in claim 1, further comprising: the controller calculates the number of the newly-increased ECC areas after reducing the length of the effective information area mapped by each ECC area by a preset step length in advance according to the current solid state disk capacity, the length of the effective information area mapped by each ECC area and the preset step length; calculating reserved space for the newly added ECC area according to the number of the newly added ECC areas and the preset ECC area length; and when reporting the available space to an upper layer application, reporting the numerical value obtained by subtracting the reserved space for the newly added ECC area from the current solid state disk capacity to the upper layer application.
3. The method of claim 1, wherein the recalculating the check value for each ECC region comprises: and after 0 or 1 of the preset step number is supplemented for each effective information area, calculating the check value of each corresponding ECC area.
4. A method as recited in claim 3, further comprising: if the check value of each ECC area is calculated after the 0 of the preset step number is supplemented for each effective information area, the 0 of the preset step number is supplemented for each effective information area in the data check period; and if the check value of each corresponding ECC area is calculated after the 1 s of the preset step number are supplemented for each effective information area, supplementing the 1 s of the preset step number for each effective information area during data check.
5. The method as recited in claim 1, further comprising: the controller maintains a record table comprising the bit error bit number and the length of the effective information area of a plurality of blocks or pages in a cache, and when the controller determines that the bit error bit number reaches the threshold of the error-correctable bit number corresponding to the preset ECC algorithm, the controller performs the operation of reducing the length of the effective information area mapped by the ECC area by a preset step length in the block or page where the bit error bit number reaches the threshold of the error-correctable bit number corresponding to the preset ECC algorithm.
6. The method as recited in claim 5, further comprising: when the controller writes data into any block or page, acquiring the record of the effective information area length in the record table, supplementing 0 or 1 of the corresponding number according to the record of the effective information area length in the record table, and calculating the check value of the corresponding ECC area; and when checking any block or page, the controller acquires the record of the length of the effective information area in the record table, supplements 0 or 1 of the corresponding number according to the record of the length of the effective information area in the record table, and checks the effective information area.
7. The method of claim 6, wherein the controller pre-calculates a space for the newly added ECC area within each block or page; when reporting the available space to the upper layer application, the values obtained by subtracting the space for the newly added ECC area from the capacity in each block or page are summed and reported to the upper layer application.
8. A solid state disk controller device, comprising: the monitoring unit is used for monitoring bit error bits of the effective information area of the solid state disk in the running process of the solid state disk; the length control unit is used for reducing the length of the effective information area mapped by the ECC area by a preset step length whenever the bit error number reaches the threshold of the error-correctable number corresponding to the preset ECC algorithm; an operation unit, configured to shift the effective information area data according to the length of the effective information area mapped by each reduced ECC area, newly add an ECC area, and recalculate a check value of each ECC area;
the method comprises the steps of calculating a preset step length according to a preset hard disk working bit error formula and a preset time interval between two reduction step lengths, recording relations between various hard disk using parameters and hard disk bit error digits of hard disk writing times and storage time according to the preset hard disk working bit error formula, calculating a change value of the number of hard disk bit error digits corresponding to the preset time interval between two reduction step lengths after setting the writing times and the storage time parameters of a hard disk in the preset time interval between two reduction step lengths, and calculating the preset step length according to the change value of the number of hard disk bit error digits and an error-correctable digit threshold corresponding to an ECC algorithm.
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