CN110309678B - Memory scrambling method - Google Patents
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- CN110309678B CN110309678B CN201910583472.7A CN201910583472A CN110309678B CN 110309678 B CN110309678 B CN 110309678B CN 201910583472 A CN201910583472 A CN 201910583472A CN 110309678 B CN110309678 B CN 110309678B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1408—Protection against unauthorised use of memory or access to memory by using cryptography
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
- G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
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Abstract
The embodiment of the invention relates to a memory scrambling method, which comprises the following steps: generating a scrambling key; acquiring a write-in address and writing in an original text; pre-scrambling the scrambling key to generate a first scrambling factor; pre-scrambling the write address to generate a second scrambling factor; pre-scrambling the written text to generate a third scrambling factor; according to the first, second and third scrambling factors, carrying out memory write scrambling processing to generate a write data scrambling code; and writing the generated write data scrambling code at the write address of the memory. A method of memory descrambling, comprising: acquiring a read address; pre-scrambling the scrambling key to generate a fourth scrambling factor; pre-scrambling the read address to generate a fifth scrambling factor; acquiring data bytes from a read address of a memory to generate read data; descrambling after memory reading is carried out according to the read data, the fourth scrambling factor and the fifth scrambling factor to generate temporary decoding data; and performing pre-disturbance removal processing on the temporary decoding data to generate a read original text.
Description
Technical Field
The invention relates to the technical field of single-chip microcomputers, in particular to a memory scrambling method.
Background
The attack object aiming at the single-chip microcomputer memory intrusive attack is the stored data of the memory, and the data text in the storage unit can be directly obtained by detecting the attack equipment. Once the data in the memory is illegally monitored, stolen or tampered by the intervention attack, the risk of data leakage can occur in the service process of the upper system of the single chip microcomputer, and even the application security monitoring means of the upper system can be disabled.
Disclosure of Invention
The present invention aims at the technical defects, and provides a memory scrambling method, which is used for scrambling and packaging original data once when data is written into a memory, otherwise, a descrambling operation is required to be added to obtain the data original text when the data is obtained from a memory address.
In order to achieve the above object, the present invention provides a method for memory scrambling, which includes:
the single chip microcomputer acquires the scrambling code status word and generates a scrambling key according to the scrambling code status word;
the single chip microcomputer acquires a write-in address and writes in an original text;
the single chip microcomputer carries out pre-scrambling processing on the scrambling key to generate a first scrambling factor;
the singlechip performs pre-scrambling processing on the written address to generate a second scrambling factor;
the single chip microcomputer carries out pre-scrambling processing on the written original text to generate a third scrambling factor;
the single chip microcomputer performs memory write scrambling processing according to the first scrambling factor, the second scrambling factor and the third scrambling factor to generate a write data scrambling code;
and the single chip microcomputer writes the write-in data scrambling code in the write-in address of the memory according to the write-in data scrambling code.
Further, the acquiring, by the single chip microcomputer, the scrambling code status word, and generating the scrambling key according to the scrambling code status word specifically include:
the single chip microcomputer acquires the scrambling code status word;
when the value of the scrambling code state word is zero, the singlechip calls a true random number generator to generate a first temporary scrambling key and stores the first temporary scrambling key in a scrambling key storage area, the scrambling key is generated according to the first temporary scrambling key, and the value of the scrambling code state word is set to be 1;
and when the value of the scrambling code state word is 1, the singlechip acquires a second temporary scrambling key from the scrambling key storage area to generate the scrambling key.
Further, the pre-scrambling processing is performed on the scrambling key by the single chip microcomputer to generate a first scrambling factor, which specifically includes:
and the singlechip performs full-byte negation processing on the scrambling key to generate the first scrambling factor.
Further, the pre-scrambling processing is performed on the write address by the single chip microcomputer to generate a second scrambling factor, which specifically includes:
and the singlechip performs full-byte negation processing on the write-in address to generate the second scrambling factor.
Further, the pre-scrambling processing is performed on the written-in original text by the single chip microcomputer to generate a third scrambling factor, which specifically includes:
and the single chip microcomputer performs full-byte negation processing on the written original text to generate the third scrambling factor.
Further, the single chip microcomputer performs memory write scrambling processing according to the first scrambling factor, the second scrambling factor and the third scrambling factor to generate a write data scrambling, and the method specifically includes:
the single chip microcomputer generates first temporary data according to the result of the XOR between the first scrambling factor and the second scrambling factor;
and the singlechip generates a write-in data scrambling code according to the XOR result of the first temporary data and the third scrambling code factor.
The invention also provides a memory descrambling method, which comprises the following steps:
the single chip microcomputer obtains the scrambling key;
the single chip microcomputer obtains a read address;
the single chip microcomputer carries out pre-scrambling processing on the scrambling key to generate a fourth scrambling factor;
the single chip microcomputer carries out pre-scrambling processing on the read address to generate a fifth scrambling factor;
the single chip microcomputer acquires data bytes from the read address of the memory to generate read data;
the single chip microcomputer performs descrambling processing after memory reading according to the read data, the fourth scrambling factor and the fifth scrambling factor to generate temporary decoding data;
and the singlechip is used for carrying out pre-disturbance removal processing on the temporary decoding data to generate a read original text.
Further, the single chip microcomputer performs descrambling processing after memory reading according to the read data, the fourth scrambling factor and the fifth scrambling factor to generate temporary decoded data, and the method specifically includes:
the single chip microcomputer generates second temporary data according to the result of the coincidence of the read data and the fourth scrambling code factor;
and the singlechip generates the temporary decoding data according to the result of the coincidence of the second temporary data and the fifth scrambling factor.
Further, the single chip microcomputer performs pre-disturbance removing processing on the temporary decoded data to generate a read-out original text, and specifically includes:
and the singlechip performs full-byte negation processing on the temporary decoding data to generate the read original text.
In the method for scrambling the memory provided by the embodiment of the invention, a scrambling key is generated by a true random number generator after a single reset is carried out on a single chip microcomputer every time; when the system writes the memory address with the scrambling requirement, the singlechip carries out XOR calculation on the written address, the written data and the scrambling key in sequence after the pre-scrambling is finished, and the calculated result is used as scrambled data and is written in the written address by the singlechip; in the method for descrambling the memory provided by the embodiment of the invention, when the system reads the memory address with the scrambling requirement, the singlechip carries out one-time synchronization or calculation on the read data, the scrambling key subjected to the pre-scrambling treatment and the read address in sequence, and the calculated result is used as the descrambled data by the singlechip.
Drawings
Fig. 1 is a schematic diagram of an operation of a memory scrambling method according to an embodiment of the present invention.
Fig. 2 is a schematic diagram illustrating an operation of a method for descrambling a memory according to a second embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be described in further detail with reference to the accompanying drawings, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In an embodiment of the present invention, as shown in fig. 1, which is a working schematic diagram of a memory scrambling method provided in the first embodiment of the present invention, the method includes the following steps:
the method specifically comprises the following steps: step 111, the singlechip acquires the scrambling code status word,
here, the scrambling key used by the memory scrambling is different in value in each power-on period, but should not change in the current power-on period, so the system provides a scrambling code status word as an identifier for whether the scrambling key is currently generated, if the value is zero, it is indicated that the scrambling key is not generated in the power-on period this time, if the value is 1, it is indicated that the scrambling key is generated in the power-on period this time, the single chip microcomputer stores the scrambling key in a specific position in the memory, the scrambling key storage position adopts a plaintext storage mode instead of a scrambling code storage mode, and the scrambling key does not distinguish read-write operations;
step 112, the value of the scrambling code status word is zero, the singlechip calls the true random number generator to generate a scrambling key,
here, the generated random number length as the scramble key is a fixed random number length, assuming 4 bytes, and assuming that the current random number output is a hexadecimal random number 0x1297F3 AB;
and step 113, setting the value of the scrambling code status word to 1 by the singlechip.
it is assumed here that the write address is hexadecimal data 0x010203040506 and the write text is hexadecimal data 0x 1122334455.
the method specifically comprises the following steps: the single chip microcomputer performs full byte negation processing on the scrambling key to generate a first scrambling factor,
here, if the data length of the scrambling key is smaller than the length of the written original text, an upper byte complement operation (the complement is a fixed byte code, such as 0x00, 0xFF, etc.) is required to be performed on the scrambling key before negation, so that the data length of the scrambling key is equal to the length of the written original text; if the data length of the scrambling key is larger than the length of the written original text, the scrambling key needs to be subjected to high-order byte code interception operation before negation, and the data length after code interception is equal to the length of the written original text: in this example, the length of the scrambling key is 4 bytes, the length of the written original text is 5 bytes, then a complement is required, assuming that the complement rule is 0xFF complement, the calculation data for the negation calculation is changed from 0x1297F3AB to 0xFF1297F3AB, and the value of the first scrambling factor generated by performing full byte negation 0xFF1297F3AB is: 0x00ED680C 54.
the method specifically comprises the following steps: the singlechip performs full byte negation processing on the written address to generate a second scrambling factor,
here, if the data length of the write address is smaller than the length of the original text to be written, an upper byte complement operation (the complement is a fixed byte code, such as 0x00, 0xFF, etc., in hexadecimal) is required to be performed on the write address before negation, so that the data length of the write address is equal to the length of the original text to be written; if the data length of the write address is larger than the length of the write-in original text, the high-order byte code cutting operation needs to be carried out on the write address before negation, and the data length after code cutting is equal to the length of the write-in original text: in this example, the write address length is 6 bytes, the write-in original text length is 5 bytes, and high-order code truncation is required, so that the calculation data for negation calculation is changed from 0x010203040506 to 0x0203040506, and the value of the second scrambling factor generated by performing full-byte negation calculation on 0x0203040506 is: 0xFDFCFBFAF 9.
the method specifically comprises the following steps: the single chip microcomputer performs full byte negation processing on the written original text to generate a third scrambling factor,
here, the value of the third scrambling factor generated by performing a full byte negation calculation on the written text 0x1122334455 is: 0 xeeddcbbaa.
the method specifically comprises the following steps: 161, the single chip generates a first temporary data according to the result of the xor between the first scrambling factor and the second scrambling factor,
here, the xor calculation is performed by the first scrambling factor 0x00ED680C54 and the second scrambling factor 0 xfdffbfaf 9, and the value of the generated first temporary data is: 0xFD1193F6 AD;
step 162, the single chip generates a write-in data scrambling code according to the result of the XOR between the first temporary data and the third scrambling code factor,
here, the xor calculation is performed on the first temporary data 0xFD1193F6AD and the third scrambling factor 0 xeeddcbbaa, and the value of the generated data scrambling code is: 0x13CC5F4D 07.
here, the one-chip microcomputer writes data at a location where the memory address is 0x010203040506, and the value of the written data is the data scrambling code 0x13CC5F4D 07.
Therefore, after the single chip microcomputer is successfully processed through the process from step 11 to step 17, the scrambling writing of the heap memory is completed according to the scrambling mode provided by the method, and the written data can be seen to have no correlation with the original text, so that the real meaning of the written data cannot be analyzed even if the written data is acquired by an illegal user.
In the second embodiment of the present invention, as shown in fig. 2, which is a working schematic diagram of a method for descrambling a memory provided in the second embodiment of the present invention, the method includes the following steps:
here, when the single chip microcomputer descrambles the memory, because the scrambling key is already generated, the single chip microcomputer can directly acquire the scrambling key from the storage area for storing the scrambling key, 4 bytes are assumed in the calculation, and the random number output this time is assumed to be a hexadecimal random number 0x1297F3 AB.
here, it is assumed that the read address is 0x010203040506 of hexadecimal data, and since the allocation of memory space on a single chip is clearly specified at the time of system initialization, the length of stored data corresponding to the memory address is also fixed, and assuming that the data length of the address is 5 bytes, the read data length should be 5 bytes.
the method specifically comprises the following steps: the singlechip performs full byte negation processing on the scrambling key to generate a fourth scrambling factor,
here, if the data length of the scrambling key is smaller than the read data length, an upper byte complement operation (the complement is a fixed byte code, such as 0x00, 0xFF, etc.) is required to be performed on the scrambling key before negation, so that the data length is equal to the read data length; if the data length of the scrambling key is larger than the read data length, the scrambling key needs to be subjected to high-order byte code interception before negation, and the data length after code interception is equal to the read data length: in this example, the length of the scrambling key is 4 bytes, the length of the written original text is 5 bytes, then a complement is required, assuming that the complement rule is 0xFF complement, the calculation data for the negation calculation is changed from 0x1297F3AB to 0xFF1297F3AB, and the value of the fourth scrambling factor generated by performing full byte negation 0xFF1297F3AB is: 0x00ED680C 54.
the method specifically comprises the following steps: the singlechip performs full byte negation processing on the read address to generate a fifth scrambling factor,
here, if the data length of the read address is smaller than the read data length, an upper byte complement operation (the complement is a fixed byte code, such as 0x00, 0xFF, etc., in hexadecimal) is required on the read address before negation, so that the data length is equal to the read data length; if the data length of the read address is larger than the read data length, the read address needs to be subjected to high-order byte code-cutting operation before negation, and the data length after code cutting is equal to the read data length: in this example, the read address length is 6 bytes, the read data length is 5 bytes, and high-order code truncation is required, so that the calculation data for the negation calculation is changed from 0x010203040506 to 0x0203040506, and the value of the fifth scrambling factor generated by performing the full-byte negation calculation on 0x0203040506 is: 0xFDFCFBFAF 9.
here, it is assumed that the data value read from the memory address 0x010203040506 is: 0x13CC5F4D 07.
the method specifically comprises the following steps: step 261, the single chip generates second temporary data according to the result of the coincidence of the read data and the fourth scrambling factor,
here, the read data 0x13CC5F4D07 is subjected to the same or calculation as the fourth scrambling factor 0x00ED680C54, and the value of the generated second temporary data is 0x 1321374153:
step 262, the single chip generates temporary decoding data according to the result of the coincidence of the second temporary data and the fifth scrambling factor,
here, the value 0 xeeddcbbaa of the temporary decoded data is generated by performing the same or calculation of the second temporary data 0x1321374153 and the fifth scrambling factor 0x0 xfdffbfaf 9.
the method specifically comprises the following steps: the singlechip performs full byte negation processing on the temporary decoding data to generate a read original text,
here, the value of the read original generated by performing the all-byte inversion calculation on the provisionally decoded data 0 xeeddcbbaa is: 0x 1122334455.
Therefore, after the single chip is successfully processed through the process from step 21 to step 27, the scrambling method provided by the method of the present invention completes descrambling and reading the data which is scrambled and stored in the memory, the processing is also the reverse processing of scrambling and writing, and the scrambled code read by the single chip without the processing part cannot be normally used by the system program.
In the method for scrambling the memory provided by the embodiment of the invention, a scrambling key is generated by a true random number generator after a single reset is carried out on a single chip microcomputer every time; when the system writes a memory address with a scrambling function, the singlechip performs XOR calculation on the write-in address, the write-in data and the scrambling key once, and the calculated result is used as scrambled data and is written in the write-in address by the singlechip; when the system reads the memory address with scrambling function, the single chip microcomputer processes the read data, the scrambling key and the read address once or calculates, and the calculated result is used as the descrambled data by the single chip microcomputer. By using the method of the invention, the memory data can be effectively prevented from being monitored and damaged by the outside in an intervention detection mode.
Those of skill would further appreciate that the various illustrative components and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied in hardware, a software module executed by a processor, or a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (6)
1. A method for memory scrambling, the method comprising:
the single chip microcomputer acquires the scrambling code status word and generates a scrambling key according to the scrambling code status word;
the single chip microcomputer acquires a write-in address and writes in an original text;
the single chip microcomputer carries out pre-scrambling processing on the scrambling key to generate a first scrambling factor;
the singlechip performs pre-scrambling processing on the written address to generate a second scrambling factor;
the single chip microcomputer carries out pre-scrambling processing on the written original text to generate a third scrambling factor;
the single chip microcomputer performs memory write scrambling processing according to the first scrambling factor, the second scrambling factor and the third scrambling factor to generate a write data scrambling code;
the single chip microcomputer writes the write-in data scrambling code in the write-in address of the memory according to the write-in data scrambling code;
the method includes the steps that the single chip microcomputer obtains scrambling code status words and generates scrambling keys according to the scrambling code status words, and the method specifically includes the following steps:
the single chip microcomputer acquires the scrambling code status word;
when the value of the scrambling code state word is zero, the singlechip calls a true random number generator to generate a first temporary scrambling key and stores the first temporary scrambling key in a scrambling key storage area, the scrambling key is generated according to the first temporary scrambling key, and the value of the scrambling code state word is set to be 1;
when the value of the scrambling code status word is 1, the singlechip acquires a second temporary scrambling key from the scrambling key storage area to generate the scrambling key;
the single chip microcomputer performs memory write scrambling processing according to the first scrambling factor, the second scrambling factor and the third scrambling factor to generate a write data scrambling, and the method specifically comprises the following steps:
the single chip microcomputer generates first temporary data according to the result of the XOR between the first scrambling factor and the second scrambling factor;
and the singlechip generates a write-in data scrambling code according to the XOR result of the first temporary data and the third scrambling code factor.
2. The method according to claim 1, wherein the generating a first scrambling factor by the single chip microcomputer performing pre-scrambling on the scrambling key comprises:
and the singlechip performs full-byte negation processing on the scrambling key to generate the first scrambling factor.
3. The method according to claim 1, wherein the generating a second scrambling factor by the single chip microcomputer by performing pre-scrambling processing on the write address specifically includes:
and the singlechip performs full-byte negation processing on the write-in address to generate the second scrambling factor.
4. The method according to claim 1, wherein the single chip performs pre-scrambling processing on the written text to generate a third scrambling factor, specifically comprising:
and the single chip microcomputer performs full-byte negation processing on the written original text to generate the third scrambling factor.
5. A method for descrambling a memory, the method comprising:
the single chip microcomputer obtains a scrambling key;
the single chip microcomputer obtains a read address;
the single chip microcomputer carries out pre-scrambling processing on the scrambling key to generate a fourth scrambling factor;
the single chip microcomputer carries out pre-scrambling processing on the read address to generate a fifth scrambling factor;
the single chip microcomputer acquires data bytes from the read address of the memory to generate read data;
the single chip microcomputer performs descrambling processing after memory reading according to the read data, the fourth scrambling factor and the fifth scrambling factor to generate temporary decoding data;
the singlechip performs pre-disturbance removing processing on the temporary decoding data to generate a read original text;
the scrambling key is specifically data stored in a storage area of the single chip microcomputer;
the single chip microcomputer performs descrambling processing after memory reading according to the read data, the fourth scrambling factor and the fifth scrambling factor to generate temporary decoding data, and the method specifically comprises the following steps:
the single chip microcomputer generates second temporary data according to the result of the coincidence of the read data and the fourth scrambling code factor;
and the singlechip generates the temporary decoding data according to the result of the coincidence of the second temporary data and the fifth scrambling factor.
6. The method according to claim 5, wherein the singlechip performs descrambling on the temporary decoded data to generate a read-out text, and specifically includes:
and the singlechip performs full-byte negation processing on the temporary decoding data to generate the read original text.
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