CN110299919B - low-power-consumption ultrahigh-speed high-precision analog-to-digital converter - Google Patents
low-power-consumption ultrahigh-speed high-precision analog-to-digital converter Download PDFInfo
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- CN110299919B CN110299919B CN201910787405.7A CN201910787405A CN110299919B CN 110299919 B CN110299919 B CN 110299919B CN 201910787405 A CN201910787405 A CN 201910787405A CN 110299919 B CN110299919 B CN 110299919B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
- H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
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Abstract
The invention discloses a low-power-consumption ultrahigh-speed high-precision analog-to-digital converter which comprises an input circuit, a low-speed ADC (analog-to-digital converter), a 1/16 frequency divider and an output circuit, wherein the input circuit is connected with the low-speed ADC, the low-speed ADC is connected with the output circuit, and the 1/16 frequency divider is respectively connected with the input circuit and the low-speed ADC; the input circuit samples an input signal by adopting the frequency of 1.6 GHz; the low-speed ADC acquires signals from the input circuit at the frequency of 100MHz, and is a low-power consumption ADC circuit architecture with the sampling frequency of 10-bit resolution gigahertz, which is built in an IC chip.
Description
Technical Field
The invention relates to the technical field of analog-to-digital conversion, in particular to a low-power-consumption ultrahigh-speed high-precision analog-to-digital converter.
Background
with the increasing bandwidth requirement of input analog signals and the increasing requirement of direct sampling of radio frequency signals, ultra-high speed analog-to-digital converter (ADC) chips have a huge market demand.
The existing ultra-high speed ADC architecture mainly comprises a Flash (Flash), a folding interpolation, a Pipeline (Pipeline), time interleaving and the like.
A Flash ADC (Flash ADC), also called a parallel ADC, is the simplest ADC architecture in the industry that can achieve the highest conversion rate, but as the resolution is increased, the number of required comparators increases exponentially, resulting in a significant increase in chip area and power consumption. In addition, mismatch between numerous comparators will severely limit the performance of the ADC.
Folded interpolation ADCs are an evolution of flash ADCs with the goal of reducing the number of comparators. In order to realize high-speed and high-precision performance, the folding factor of the framework is required to be high, so that the frequency of an output signal of the folder is high, high requirements on the precision and the speed of the comparator are provided, the design difficulty is high, and the power consumption is increased.
the pipeline ADC is used for cascading multi-stage high-speed low-precision sub-ADCs, and each stage of sub-ADC carries out quantitative conversion on a residual signal of a previous stage in sequence in a pipeline mode so as to realize high-speed high-precision performance. With the increase of the sampling frequency of the ADC, the setup time of the operational amplifier needs to be shortened accordingly, i.e. the bandwidth index is increased, so that the power consumption is increased. Especially for ADCs operating at gigahertz sampling rates, the operational amplifiers in the pipeline architecture will consume significant power.
The time-interleaved ADC is a popular architecture for realizing a super-high-speed ADC in recent years, and realizes high-speed quantization conversion of signals by utilizing time-sharing alternate sampling work of a plurality of low-speed ADCs. The low-speed ADC can be selected from various architectures, and different combinations can produce different effects. However, in any collocation, the time-interleaved ADC itself is sensitive to mismatch between the low-speed ADCs, which is embodied as sampling time mismatch, mismatch, gain mismatch, and the like between the low-speed ADCs. These mismatches severely limit the performance of the time-interleaved ADC.
In summary, for the demands of low-power consumption, ultra-high speed and high precision ADCs in the market, no standard architecture design exists at present, and the ADC architectures need to be designed in a targeted manner according to different index demands.
Disclosure of Invention
the invention aims to provide a low-power-consumption ultrahigh-speed high-precision analog-to-digital converter, which is a low-power-consumption ADC circuit architecture with a 10-bit resolution gigahertz sampling frequency and built in an IC chip.
The invention is realized by the following technical scheme: a low-power-consumption ultra-high-speed high-precision analog-to-digital converter comprises an input circuit, a low-speed ADC, a 1/16 frequency divider and an output circuit, wherein the input circuit is connected with the low-speed ADC, the low-speed ADC is connected with the output circuit, and the 1/16 frequency divider is respectively connected with the input circuit and the low-speed ADC; the input circuit samples an input signal at a frequency of 1.6 GHz; the low-speed ADC obtains signals from an input circuit at the frequency of 100 MHz.
In order to further realize the invention, the following arrangement mode is adopted: the low-speed ADC comprises 16 SAR _ ADCs which are subjected to time-sharing alternate sampling work, the SAR _ ADCs are connected with the input circuit in parallel, the 1/16 frequency divider is connected with the SAR _ ADC in a control mode, and the SAR _ ADC is connected with the output circuit.
In order to further realize the invention, the following arrangement mode is adopted: a local capacitor is arranged at the reference voltage access point of any SAR _ ADC.
In order to further realize the invention, the following arrangement mode is adopted: the same reference voltage is used for 16 SAR _ ADCs.
In order to further realize the invention, the following arrangement mode is adopted: the input circuit comprises a terminal resistor and an input signal processing circuit which are connected with each other, and the input signal processing circuit is connected with the low-speed ADC.
In order to further realize the invention, the following arrangement mode is adopted: the terminal resistor is two resistors which are connected in series and have the same resistance value and are connected to the input end of the input signal processing circuit.
in order to further realize the invention, the following arrangement mode is adopted: the output circuit comprises a digital circuit and a low-voltage differential signal output circuit which are connected with each other, and the output end of the low-speed ADC is connected with the digital circuit.
in order to further realize the invention, the following arrangement mode is adopted: the digital circuit outputs a signal at a frequency of 1.6GHz into a low voltage differential signal output circuit.
in order to further realize the invention, the following arrangement mode is adopted: the output circuit differentially outputs 10-bit quantized digital codes in a parallel mode.
compared with the prior art, the invention has the following advantages and beneficial effects:
(1) The invention relates to a low-power consumption ADC circuit architecture with 10-bit resolution gigahertz sampling frequency, which is constructed in an IC chip.
(2) the invention mainly aims at the ADC framework with 10-bit resolution and 1.6GHz sampling frequency to design, and realizes the low-power consumption ultrahigh-speed high-precision ADC.
(3) The invention can realize that the ADC with 10-bit resolution works under the sampling frequency of 1.6 gigahertz, and when the frequency of an input signal is 373 megahertz, the effective bit (ENOB) of the ADC reaches 8.6 bits.
(4) The invention adopts the technical means of analog circuit design to reduce the mismatch influence among the low-speed ADCs in the time-interleaved ADC so as to improve the performance and simultaneously avoid the complex background digital correction algorithm and the extra power consumption.
(5) the invention is used for improving the technical means of designing the analog circuit of the ultra-high-speed high-precision ADC, eliminating the influence of background digital correction on signal quantization conversion and shortening the output time of the signal quantization conversion.
Drawings
Fig. 1 is a schematic diagram of the present invention.
FIG. 2 is a schematic diagram of a portion of the low speed ADC of the present invention.
Detailed Description
the present invention will be described in further detail with reference to examples, but the embodiments of the present invention are not limited thereto.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings of the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the equipment or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
It is worth noting that: in the present application, when it is necessary to apply the known technology or the conventional technology in the field, the applicant may have the case that the known technology or/and the conventional technology is not specifically described in the text, but the technical means is not specifically disclosed in the text, and the present application is considered to be not in compliance with the twenty-sixth clause of the patent law.
The noun explains:
ADC, acronym for Analog-to-Digital Converter, refers to an Analog-to-Digital Converter or Analog-to-Digital Converter.
SAR _ ADC, successive approximation analog-to-digital converter.
LVDS, an abbreviation of Low-Voltage Differential Signaling, refers to Low-Voltage Differential signals (Low-Voltage Differential signals).
Example 1:
The invention designs a low-power consumption ultra-high speed high precision analog-to-digital converter, which is a low-power consumption ADC circuit framework with 10-bit resolution gigahertz sampling frequency built in an IC chip, as shown in figures 1 and 2, and particularly adopts the following arrangement structure: the input circuit is connected with the low-speed ADC, the low-speed ADC is connected with the output circuit, and the 1/16 frequency divider is respectively connected with the input circuit and the low-speed ADC; the input circuit samples an input signal at a frequency of 1.6 GHz; the low-speed ADC obtains signals from an input circuit at the frequency of 100 MHz.
As a preferred arrangement scheme, the low-power-consumption ultra-high-speed high-precision analog-to-digital converter mainly comprises an input circuit, a low-speed ADC, a 1/16 frequency divider and an output circuit, wherein the input circuit samples an input signal at the frequency of 1.6GHz after introducing and buffering the signal under the condition of reducing signal reflection and ensuring the signal transmission efficiency, and simultaneously isolates the influence on a signal input end caused by the working of the low-speed ADC; the low-speed ADC receives the same reference voltage, sequentially acquires signals from the input circuit at the frequency of 100MHz, and performs quantization conversion on the acquired signals according to the reference voltage to form a 10-bit digital code and outputs the digital code to the output circuit; the output circuit receives the quantized output digital codes of the low-speed ADC, and outputs 10-bit quantized code words to the low-power-consumption ultrahigh-speed high-precision analog-to-digital converter in a differential mode in a parallel mode after the assumed digital codes are sorted and sequenced for use by the digital signal processing circuit; and the 1/16 frequency divider receives a clock with the frequency of 1.6GHz, divides the clock into 100MHz sub-clocks with 16 phases and transmits the sub-clocks to the low-speed ADC, so that the low-speed ADC realizes time-sharing alternate sampling work.
Example 2:
The present embodiment is further optimized based on the above embodiment, and the same parts as those in the technical solutions of the foregoing embodiments will not be described herein again, as shown in fig. 1 and fig. 2, in order to further better implement the present invention, the following setting modes are particularly adopted: the low-speed ADC comprises 16 SAR _ ADCs which are subjected to time-sharing alternate sampling work, the SAR _ ADCs are connected with the input circuit in parallel, the 1/16 frequency divider is connected with the SAR _ ADC in a control mode, and the SAR _ ADC is connected with the output circuit.
As a preferred arrangement scheme, the low-speed ADC mainly comprises 16 SAR _ ADCs which are alternately sampled and operated at different time intervals, the 16 SAR _ ADCs which are alternately sampled and operated at different time intervals are arranged in a parallel architecture mode, the output sides of the input circuits are connected with the 16 SAR _ ADCs which are alternately sampled and operated at different time intervals, the 1/16 frequency divider is used for controlling and connecting the 16 SAR _ ADCs which are alternately sampled and operated at different time intervals, and the 16 SAR _ ADCs which are alternately sampled and operated at different time intervals are connected with the output circuits; the input circuit receives a 1.6GHz sampling clock to sample an input signal and buffer and output the sampled input signal to 16 low-speed SAR _ ADC signal receiving ends working in time-sharing alternative sampling; after the 16 low-speed SAR _ ADCs working in time-sharing alternative sampling receive the 100MHz sampling clock frequency-divided by the 1/16 frequency divider, the received input signals are subjected to alternative time-sharing sampling and quantized conversion output.
Example 3:
The present embodiment is further optimized based on any of the above embodiments, and the same parts as those in the technical solutions of the foregoing embodiments will not be described herein again, as shown in fig. 1 and fig. 2, in order to further better implement the present invention, the following setting modes are particularly adopted: local capacitors are arranged at reference voltage access points of any SAR _ ADC, and as an optimal arrangement scheme, the local capacitors (C _ DEC) are introduced into the reference voltage access points of each SAR _ ADC to reduce dynamic mismatch among reference voltages, so that gain mismatch among the SAR _ ADCs is greatly reduced, and the performance of the ultra-high-speed high-precision analog-to-digital converter is improved.
Example 4:
the present embodiment is further optimized based on any of the above embodiments, and the same parts as those in the technical solutions of the foregoing embodiments will not be described herein again, as shown in fig. 1 and fig. 2, in order to further better implement the present invention, the following setting modes are particularly adopted: the same reference voltage is adopted by the 16 SAR _ ADCs, and as a preferred arrangement scheme, a uniform reference voltage (VREF _ L16 (preferably 0.4V)) is provided for the 16 SAR _ ADCs which are operated by time-sharing alternate sampling so as to eliminate static voltage mismatch.
Example 5:
The present embodiment is further optimized based on any of the above embodiments, and the same parts as those in the technical solutions of the foregoing embodiments will not be described herein again, as shown in fig. 1 and fig. 2, in order to further better implement the present invention, the following setting modes are particularly adopted: the input circuit comprises a terminal resistor and an input signal processing circuit which are connected with each other, and the input signal processing circuit is connected with the low-speed ADC.
as a preferred arrangement scheme, the input circuit is formed by a terminal resistor and an input signal processing circuit which are connected with each other, wherein the terminal resistor is hung at two input ends of the input signal processing circuit and used as a terminal of a high-speed signal transmission link for matching, so that reflection is reduced, and the signal transmission efficiency is ensured; the input signal processing circuit is used for sampling and buffering an input signal, receiving an analog input signal to be quantized and converted, buffering the input signal, sampling the input signal at the frequency of 1.6GHz, outputting the input signal to the low-speed ADC which alternately works in the later stage, and simultaneously isolating the influence of the low-speed ADC on a signal input end when the low-speed ADC works.
Example 6:
The present embodiment is further optimized based on any of the above embodiments, and the same parts as those in the technical solutions of the foregoing embodiments will not be described herein again, as shown in fig. 1 and fig. 2, in order to further better implement the present invention, the following setting modes are particularly adopted: the terminal resistor is two resistors which are connected in series and have the same resistance value and are connected to the input end of the input signal processing circuit.
Preferably, the terminating resistor is formed by connecting two resistors (R1, R2) of the same resistance in series, preferably a 50 Ω resistor.
Example 7:
The present embodiment is further optimized based on any of the above embodiments, and the same parts as those in the technical solutions of the foregoing embodiments will not be described herein again, as shown in fig. 1 and fig. 2, in order to further better implement the present invention, the following setting modes are particularly adopted: the output circuit comprises a digital circuit and a low-voltage differential signal output circuit which are connected with each other, and the output end of the low-speed ADC is connected with the digital circuit.
As a preferable arrangement scheme, the output circuit is formed by a digital circuit and a Low Voltage Differential Signaling (LVDS) output circuit which are connected with each other, 16 SAR _ ADCs which perform time-sharing alternate sampling work receive the same reference voltage (VREF _ L16), sequentially acquire signals from an input signal processing (buffering/sampling) circuit at the frequency of 100MHz, perform quantization conversion on the acquired signals according to the reference voltage, and output 10-bit digital codes to the digital circuit; the digital circuit receives 16 quantized output digital codes of SAR _ ADC which are subjected to time-sharing alternate sampling work, and the digital codes are output to a low-voltage differential signal (LVDS) output circuit at the frequency of 1.6GHz after being sorted and sequenced; a Low Voltage Differential Signaling (LVDS) output circuit receives a digital code transmitted at a frequency of 1.6GHz, and differentially outputs 10-bit quantized code words to a chip (the low-power consumption ultrahigh-speed high-precision analog-to-digital converter) in a parallel mode for being used by a digital signal processing circuit; the 1/16 frequency divider receives a clock with the frequency of 1.6GHz, divides the clock into 100MHz sub-clocks with 16 phases and transmits the sub-clocks to the 16 SAR _ ADCs, so that the SAR _ ADCs realize time-sharing alternate sampling operation.
example 8:
The present embodiment is further optimized based on any of the above embodiments, and the same parts as those in the technical solutions of the foregoing embodiments will not be described herein again, as shown in fig. 1 and fig. 2, in order to further better implement the present invention, the following setting modes are particularly adopted: the digital circuit outputs a signal at a frequency of 1.6GHz into a low voltage differential signal output circuit.
Example 9:
The present embodiment is further optimized based on any of the above embodiments, and the same parts as those in the technical solutions of the foregoing embodiments will not be described herein again, as shown in fig. 1 and fig. 2, in order to further better implement the present invention, the following setting modes are particularly adopted: the output circuit differentially outputs 10-bit quantized digital codes in a parallel mode.
Example 10:
The present embodiment is further optimized based on any of the above embodiments, and the same parts as those in the technical solutions of the foregoing embodiments will not be described herein again, as shown in fig. 1 and fig. 2, in order to further better implement the present invention, the following setting modes are particularly adopted:
a low-power-consumption ultra-high-speed high-precision analog-to-digital converter is composed of a terminal resistor (two 50-ohm resistors are connected in series), an input signal buffering/sampling circuit (an input signal processing circuit), 16 low-speed successive approximation type ADCs (SAR _ ADCs) with time-sharing alternative sampling work, a digital circuit, a low-voltage differential signal (LVDS) output circuit and a 1/16 frequency divider.
The terminal resistor is hung at the two ends of the signal input of the input signal buffering/sampling circuit; the input signal buffering/sampling circuit receives a 1.6GHz sampling clock to sample an input signal and buffer and output the sampled input signal to 16 low-speed SAR _ ADC signal receiving ends which perform time-sharing alternate sampling work; after the 16 low-speed SAR _ ADCs working in time-sharing alternative sampling receive 100MHz sampling clocks divided by the 1/16 frequency divider, the received input signals are subjected to alternative time-sharing sampling and quantized conversion output; the digital circuit receives 16 time-sharing alternative sampling working 100 MSPS digital signals subjected to low-speed SAR _ ADC quantization conversion, and outputs the digital signals to a low-voltage differential signal (LVDS) output circuit at a frequency of 1.6GHz after sequencing and sorting; the final 10-bit quantized digital code of the ultra-high-speed high-precision analog-to-digital converter (ADC) is differentially output to the outside of the chip by a low-voltage differential signal (LVDS) output circuit in a parallel mode for being used by a digital signal processing circuit.
when in use:
1. according to the using environment, a user installs the ultra ~ high ~ speed high ~ precision analog ~ to ~ digital converter (hereinafter, directly referred to as ADC) of the invention, and hooks a matching resistor at each pair of differential output ends (D0P/D0N ~ D9P/D9N) of a low ~ voltage differential signal (LVDS) output circuit for signal transmission matching;
2. After step 1 is finished, the ADC of the invention is connected to a power supply;
3. After step 2, the differential analog signal to be quantized and converted is connected to the input end (VINP/VINN) of the ADC;
4. after the step 3 is completed, the ADC of the invention automatically completes the conversion from the input analog signal to the digital signal, and outputs the digital signal at the output end (D0P/D0N ~ D9P/D9N) of the Low Voltage Differential Signaling (LVDS) output circuit, and a user only needs to obtain 10 ~ bit ADC quantization conversion output digital code at the output end (D0P/D0N ~ D9P/D9N) of the Low Voltage Differential Signaling (LVDS) output circuit, and then carries out digital processing at the handover end.
5. the ADC self-quantization process of the invention comprises the following steps:
a) The differentially input analog signals are dissipated on the terminal resistor, so that the signals are ensured to enter the input signal buffer/sampling circuit in a low-reflection and high-efficiency mode;
b) After an input signal processing (buffering/sampling) circuit receives a differential analog signal, the signal is buffered and sampled and is transmitted to 16 low-speed SAR _ ADC common input ends which perform time-sharing alternate sampling work;
c) The 16 low-speed SAR _ ADCs working in time-sharing alternative sampling sequentially perform sampling quantization conversion on signals on a common input end of the SAR _ ADC, and 16 groups of digital code conversion results of 10 bits are formed respectively and are sent to a digital circuit for processing;
d) The digital circuit receives 16 groups of 10-bit analog signal digital codes for sorting and sequencing to form 1 group of 10-bit high-speed digital codes and outputs the 1 group of 10-bit high-speed digital codes to a low-voltage differential signal (LVDS) output circuit;
e) the Low Voltage Differential Signaling (LVDS) output circuit outputs the 10-bit high-speed digital code transmitted by the digital circuit to the outside of the ADC chip for subsequent processing by the circuit.
in actual use, the specific embodiments are as follows:
(1) boot process
the method comprises the steps that a user installs the ADC according to a use environment, 100 omega matching resistors are connected to each pair of differential output ends (D0P/D0N ~ D9P/D9N) of a low ~ voltage differential signaling (LVDS) output circuit in a hanging mode to carry out signal transmission matching, after the matching resistors are connected in a hanging mode, the ADC is connected to a 1.9V power supply, and after the ADC power supply is connected in, differential analog signals to be subjected to quantitative conversion are connected to an ADC input end (VINP/VINN) of the ADC;
(2) signal quantization conversion process
After the start-up of the ADC is completed, a differential analog signal with the maximum swing of 0.4V is input to an ADC input end (VINP/VINN). The input end of the ADC is connected with a terminal resistor formed by connecting two 50 omega series resistors in a hanging mode to match with the impedance of a signal source, reflection is reduced, and signal transmission efficiency is improved.
after the input signal to be quantized and converted is efficiently transmitted to the input signal processing (buffering/sampling) circuit, the input signal buffering/sampling circuit buffers the input signal with a gain of 0dB and samples the buffered signal with an operating clock of 1.6 GHz. The sampled signals are discretized to form a step shape for the subsequent 16 low-speed SAR _ ADCs working in time-sharing alternative sampling. The sampling method eliminates the mismatch of sampling time among the low-speed ADCs in the time-interleaved ADC, and can effectively improve the performance of the ADC. The bandwidth of the input signal processing (buffering/sampling) circuit is designed to be 4 GHz, and when the frequency of an input signal is 373 MHz, a sampled step signal has high linearity.
the step signals sampled by an input signal processing (buffering/sampling) circuit are transmitted to 16 low ~ speed SAR _ ADC common input ends working in time ~ sharing and alternate sampling, the 16 low ~ speed SAR _ ADCs sequentially adopt the steps at different times on the common input ends into the common input ends according to respective received sampling clocks (CLK _ L00 ~ CLK _ L15), and carry out quantitative conversion on the steps according to reference voltages received by the low ~ speed SAR _ ADCs to form 10 ~ bit digital codes and transmit the 10 ~ bit digital codes to a digital circuit at the frequency of 100 MHz.
In order to solve the offset mismatch between the low-speed ADCs in the time-interleaved ADC, the offset correction of the SAR _ ADC is added in the SAR _ ADC which works by time-sharing alternate sampling, and the offset reduction of the SAR _ ADC is realized by utilizing a charge storage technology, so that the aim of reducing the offset mismatch is fulfilled. In the invention, 1ns is needed for completing self-maladjustment correction when the SAR _ ADC starts each quantization conversion, and the working frequency of the SAR _ ADC is set to be 100MHz under the condition of ensuring that the SAR _ ADC has enough time to complete the 10-bit digital code quantization conversion for acquiring a step signal. Accordingly, 16 such SAR _ ADCs are required to perform time division alternate sampling operation to form a super high speed ADC having a sampling frequency of 1.6 GHz.
When the SAR _ ADC performs quantization conversion on the sampled signal, a reference voltage is needed. The DC value of the voltage is consistent with the maximum swing amplitude of the differential input signal, and is 0.4V in the invention. However, in the quantization conversion process of the SAR _ ADC, the reference voltage may fluctuate under the influence of the circuit, and the same design may have a deviation after the manufacturing is completed, so that there is a mismatch between the reference voltages independently provided to each SAR _ ADC in the time-division alternative sampling operation in the actual circuit, that is, a gain mismatch, resulting in a degradation of the performance of the time-interleaved ADC. In the invention, uniform reference voltage is provided for 16 SAR _ ADCs which are subjected to time-sharing alternate sampling work so as to eliminate static voltage mismatch, and a local capacitor (C _ DEC) is introduced into a reference voltage access point of each SAR _ ADC so as to reduce dynamic mismatch among the reference voltages, thereby greatly reducing gain mismatch among the low-speed SAR _ ADCs and improving the performance of the ultra-high-speed high-precision ADC.
16 low-speed SAR _ ADCs with time-sharing alternate sampling work respectively quantize and sequentially acquire respective internal step signals to form 16 groups of 10-bit digital code conversion results transmitted in parallel, and the conversion results are sent to a digital circuit for processing at an updating frequency of 100 MHz. After the digital circuit receives the 16 groups of 10-bit digital codes transmitted in parallel, the digital codes are sorted and sequenced, and the sorted digital codes are transmitted to a low-voltage differential signaling (LVDS) output circuit at the updating frequency of 1.6 GHz. In the invention, the digital circuit only carries out data sorting and sequencing in the ultra-high-speed high-precision ADC, and the mismatch influence among the low-speed SAR _ ADC is solved by an analog circuit design technical means. Compared with a super-high-speed high-precision ADC (analog to digital converter) framework adopting a background digital correction algorithm, the digital circuit is easy to realize, small in scale and low in power consumption, extra time is not needed for correcting digital codes transmitted by a low-speed ADC, and the time for signal quantization conversion output is short.
The Low Voltage Differential Signaling (LVDS) output circuit processes 10-bit 1.6 GSPS digital codes transmitted by the digital circuit, converts the digital codes into current signals and outputs the current signals to the outside of an ADC chip for processing by users.
(3) quantized transform result receiving process
the quantization conversion digital code of the input signal sampled at the current moment is subjected to time delay required by ADC quantization conversion and then appears at the output port (D0P/D0N ~ D9P/D9N) of a low ~ voltage differential signaling (LVDS) output circuit of the ADC, and the user only needs to obtain differential voltages at two ends of a 100 ~ ohm matching resistor hung at the output port (D0P/D0N ~ D9P/D9N) of the low ~ voltage differential signaling (LVDS) output circuit together and then carries out digital processing at the handover rear end.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and all simple modifications and equivalent variations of the above embodiments according to the technical spirit of the present invention are included in the scope of the present invention.
Claims (6)
1. A low-power consumption superhigh speed high accuracy analog-to-digital converter which characterized in that: the ADC circuit comprises an input circuit, a low-speed ADC, a 1/16 frequency divider and an output circuit, wherein the input circuit is connected with the low-speed ADC, the low-speed ADC is connected with the output circuit, and the 1/16 frequency divider is respectively connected with the input circuit and the low-speed ADC; the input circuit samples an input signal at a frequency of 1.6 GHz; the low-speed ADC acquires signals from the input circuit at the frequency of 100 MHz; the input circuit is used for introducing and buffering signals under the conditions of reducing signal reflection and ensuring signal transmission efficiency, sampling the input signals at the frequency of 1.6GHz to form step-shaped signals, inputting the step-shaped signals to the low-speed ADC, and isolating the influence on a signal input end when the low-speed ADC works;
The low-speed ADC comprises 16 SAR _ ADCs which work in time-sharing alternate sampling, the SAR _ ADCs are connected with the input circuit in parallel, the 1/16 frequency divider is connected with the SAR _ ADC in a control mode, the SAR _ ADC is connected with the output circuit, self offset correction is added into the SAR _ ADC which works in time-sharing alternate sampling, and the SAR _ ADC offset is reduced by utilizing a charge storage technology;
A local capacitor is arranged at a reference voltage access point of any one SAR _ ADC;
and 16 SAR _ ADCs adopt the same reference voltage.
2. A low power consumption ultra high speed high accuracy analog to digital converter according to claim 1, characterized in that: the input circuit comprises a terminal resistor and an input signal processing circuit which are connected with each other, and the input signal processing circuit is connected with the low-speed ADC.
3. A low power consumption ultra high speed high accuracy analog to digital converter according to claim 2, characterized in that: the terminal resistor is two resistors which are connected in series and have the same resistance value and are connected to the input end of the input signal processing circuit.
4. A low power consumption ultra high speed high accuracy analog to digital converter according to claim 1 or 3, characterized in that: the output circuit comprises a digital circuit and a low-voltage differential signal output circuit which are connected with each other, and the output end of the low-speed ADC is connected with the digital circuit.
5. A low power consumption ultra high speed high accuracy analog to digital converter according to claim 4, characterized in that: the digital circuit outputs a signal into the low-voltage differential signal output circuit at a frequency of 1.6 GHz.
6. A low power consumption ultra high speed high accuracy analog to digital converter according to claim 1 or 3 or 5, characterized in that: the output circuit differentially outputs 10-bit quantized digital codes in a parallel mode.
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| CN116633331B (en) * | 2023-07-21 | 2023-10-20 | 成都铭科思微电子技术有限责任公司 | Switching circuit capable of switching positive and negative voltage complementary output |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6177893B1 (en) * | 1998-09-15 | 2001-01-23 | Scott R. Velazquez | Parallel processing analog and digital converter |
| CN1684370A (en) * | 2004-04-16 | 2005-10-19 | 中国科学院半导体研究所 | Single electronic analogue digital signal converter |
| CN101388669A (en) * | 2007-09-13 | 2009-03-18 | 索尼株式会社 | Parallel type analog-to-digital conversion circuit, sampling circuit and comparison amplification circuit |
| CN102342027A (en) * | 2009-03-03 | 2012-02-01 | 交互数字专利控股公司 | Method for a radio frequency (RF) sampling apparatus with arrays of time interleaved samplers and scenario based dynamic resource allocation |
| CN105406867A (en) * | 2015-12-17 | 2016-03-16 | 成都博思微科技有限公司 | Time-interleaved assembly line ADC system and sequential operation method thereof |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2623668B1 (en) * | 1987-11-20 | 1990-03-09 | Thomson Composants Militaires | FAST ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL STRUCTURE |
| CN1055811C (en) * | 1996-04-26 | 2000-08-23 | 财团法人工业技术研究院 | Quasi-tandem A-D converter |
| US7541950B2 (en) * | 2006-07-20 | 2009-06-02 | Samplify Systems, Inc. | Enhanced time-interleaved A/D conversion using compression |
| CN102136841B (en) * | 2010-11-30 | 2013-10-09 | 浙江大学 | High-speed high-accuracy recorder and sampling data automatic-correction and high-order matching method thereof |
| CN104901695B (en) * | 2015-06-29 | 2017-09-29 | 合肥工业大学 | A kind of calibration module and its calibration method for TIADC sampling time errors |
-
2019
- 2019-08-26 CN CN201910787405.7A patent/CN110299919B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6177893B1 (en) * | 1998-09-15 | 2001-01-23 | Scott R. Velazquez | Parallel processing analog and digital converter |
| CN1684370A (en) * | 2004-04-16 | 2005-10-19 | 中国科学院半导体研究所 | Single electronic analogue digital signal converter |
| CN101388669A (en) * | 2007-09-13 | 2009-03-18 | 索尼株式会社 | Parallel type analog-to-digital conversion circuit, sampling circuit and comparison amplification circuit |
| CN102342027A (en) * | 2009-03-03 | 2012-02-01 | 交互数字专利控股公司 | Method for a radio frequency (RF) sampling apparatus with arrays of time interleaved samplers and scenario based dynamic resource allocation |
| CN105406867A (en) * | 2015-12-17 | 2016-03-16 | 成都博思微科技有限公司 | Time-interleaved assembly line ADC system and sequential operation method thereof |
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