CN110299386B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN110299386B CN110299386B CN201910538515.XA CN201910538515A CN110299386B CN 110299386 B CN110299386 B CN 110299386B CN 201910538515 A CN201910538515 A CN 201910538515A CN 110299386 B CN110299386 B CN 110299386B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K50/00—Organic light-emitting devices
- H10K50/80—Constructional details
- H10K50/86—Arrangements for improving contrast, e.g. preventing reflection of ambient light
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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Abstract
The invention relates to the technical field of display panels, and discloses a display panel and a display device. The display panel comprises a lower lining layer, a first metal wire, a second metal wire and a third metal wire. The first metal routing is located on the lower lining layer. The second metal routing is located on the lower lining layer. The third metal wire is positioned above the first metal wire and the second metal wire, the third metal wire is not contacted with the first metal wire and the second metal wire, and the third metal wire is connected to the fixed potential. The orthographic projections of the first metal wire and the second metal wire on the lower lining layer are at least partially overlapped with the orthographic projection of the third metal wire on the lower lining layer, so that the first metal wire and the second metal wire form coupling capacitance with the third metal wire respectively. Through the mode, the influence of crosstalk caused by parasitic capacitance between the first metal wire and the second metal wire can be reduced.
Description
Technical Field
The present invention relates to the field of display panel technologies, and in particular, to a display panel and a display device.
Background
Currently, Active Matrix Organic Light Emitting Diode (AMOLED) displays have a wide market application. Pixels in the OLED panel are driven to emit light by a current generated by a Driving Thin Film Transistor (DTFT) in a saturated state. Because parasitic capacitance exists between the signal line and the grid electrode of the driving TFT in the OLED panel, the voltage change on the signal line can affect the potential of the grid electrode of the driving TFT, and the problem of crosstalk is caused.
Disclosure of Invention
In view of the above, the present invention provides a display panel and a display device, which can reduce the influence of crosstalk caused by parasitic capacitance between a first metal trace and a second metal trace.
In order to solve the technical problems, the invention adopts a technical scheme that: a display panel is provided, which includes a lower liner layer, a first metal trace, a second metal trace and a third metal trace. The first metal routing is located on the lower lining layer. The second metal routing is located on the lower lining layer. The third metal wire is positioned above the first metal wire and the second metal wire, the third metal wire is not contacted with the first metal wire and the second metal wire, and the third metal wire is connected to the fixed potential. The orthographic projections of the first metal wire and the second metal wire on the lower lining layer are at least partially overlapped with the orthographic projection of the third metal wire on the lower lining layer, so that the first metal wire and the second metal wire form coupling capacitance with the third metal wire respectively.
In an embodiment of the invention, orthographic projections of the first metal trace and the second metal trace on the underlying layer are located in an area defined by an orthographic projection of the third metal trace on the underlying layer.
In an embodiment of the invention, the display panel further includes a plurality of pixels arranged in an array, the plurality of pixels include a first pixel and a second pixel which are adjacent to each other, and orthographic projections of a first metal trace corresponding to the first pixel and a second metal trace corresponding to the second pixel on the underlying layer are respectively at least partially overlapped with orthographic projections of a same third metal trace on the underlying layer.
In an embodiment of the invention, the first metal trace is a gate of the driving transistor.
In an embodiment of the invention, the first metal trace and the second metal trace are disposed on the same layer, and the first metal trace is connected to the gate of the driving transistor, and an orthographic projection of a portion of the first metal trace and a portion of the second metal trace disposed on the same layer on the underlying layer are at least partially overlapped with an orthographic projection of the third metal trace on the underlying layer.
In an embodiment of the invention, the second metal trace is a data signal line.
In an embodiment of the invention, the third metal trace is connected to the power signal line or the reference voltage signal line.
In an embodiment of the invention, the display panel further includes a planarization layer, and the planarization layer contacts and covers the third metal trace.
In an embodiment of the invention, the display panel further includes a first metal plate and a second metal plate located above the first metal plate, and a first storage capacitor is formed between the first metal plate and the second metal plate; the display panel also comprises a third metal polar plate which is arranged on the same layer as the third metal routing wire, the third metal polar plate is positioned above the second metal polar plate, the third metal polar plate and the second metal polar plate are not contacted with each other, and the orthographic projections of the third metal polar plate and the second metal polar plate on the lower lining layer are at least partially overlapped, so that a second storage capacitor is formed between the third metal polar plate and the second metal polar plate; the second storage capacitor is connected with the first storage capacitor in parallel.
In order to solve the technical problem, the invention adopts another technical scheme that: there is provided a display device, which includes a driving circuit and a display panel as set forth in the above embodiments, wherein the driving circuit is coupled to the display panel for driving the display panel to realize the display function thereof.
The invention has the beneficial effects that: different from the prior art, the invention provides a display panel. The first metal wire and the second metal wire of the display panel form coupling capacitance with the third metal wire respectively. The third metal wire is connected to a fixed potential, that is, the potential of the third metal wire is fixed. Due to the existence of the coupling capacitor, the third metal wire with fixed potential can stabilize the potential of the first metal wire, so that the influence degree of the potential of the first metal wire by the parasitic capacitor (the parasitic capacitor exists between the first metal wire and the second metal wire) is reduced. And the third metal is walked and can also be stabilized the electric potential of second metal and walk the line, can reduce the change of second metal when the electric potential of second metal is walked the line electric potential to reduce the electric potential change of second metal and walked the influence of line electric potential to first metal, further reduced the electric potential of first metal and walked the degree that the electric potential of line is influenced by parasitic capacitance, just also reduced the influence that parasitic capacitance between first metal is walked and the second metal and is aroused the crosstalk, and then improved display panel's display effect.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. Moreover, the drawings and the description are not intended to limit the scope of the inventive concept in any way, but rather to illustrate it by those skilled in the art with reference to specific embodiments.
FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view along A-A of the display panel shown in FIG. 1;
FIG. 3 is a schematic structural diagram of another embodiment of a display panel according to the present invention;
FIG. 4 is a schematic cross-sectional view along the direction B-B of the display panel shown in FIG. 3;
FIG. 5 is a schematic structural diagram of a display panel according to yet another embodiment of the present invention;
FIG. 6 is a schematic structural diagram of a display device according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
In order to solve the technical problem in the prior art that crosstalk is seriously affected due to parasitic capacitance between a first metal wire and a second metal wire, an embodiment of the present invention provides a display panel. The display panel comprises a lower lining layer, a first metal wire, a second metal wire and a third metal wire. The first metal routing is located on the lower lining layer. The second metal routing is located on the lower lining layer. The third metal wire is positioned above the first metal wire and the second metal wire, the third metal wire is not contacted with the first metal wire and the second metal wire, and the third metal wire is connected to the fixed potential. The orthographic projections of the first metal wire and the second metal wire on the lower lining layer are at least partially overlapped with the orthographic projection of the third metal wire on the lower lining layer, so that the first metal wire and the second metal wire form coupling capacitance with the third metal wire respectively. As described in detail below.
In the current OLED panel, a parasitic capacitance is generated between the Data line and the gate of the driving TFT. The potential on the Data line varies. Due to the existence of parasitic capacitance, the potential change of the Data line can cause the corresponding change of the potential of the grid electrode of the driving TFT, and the writing of a power supply signal on a power supply signal line (Vdd) into the light-emitting device can be influenced, and the normal light-emitting display of the light-emitting device can be influenced.
For example, the driving TFT is usually a PMOS transistor (P-type metal-oxide-semiconductor field effect transistor), and a parasitic capacitance exists between the Data line and the gate of the driving TFT. If the potential on the Data line is in a high potential state for a long time, the gate potential is higher after the gate of the driving TFT is coupled through the parasitic capacitance, so that the conduction degree of the driving TFT is lower, and further, the writing of a power signal on a power signal wire is insufficient, the display of a light-emitting device is dark, and the display problem of uneven display is caused.
In view of the above, an embodiment of the present invention provides a display panel to solve the above technical problems in the prior art. The following is a detailed description:
referring to fig. 1-2, fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the invention, and fig. 2 is a schematic cross-sectional structural diagram of the display panel shown in fig. 1 along a direction a-a. It is understood that other functional film layers of the display panel 1, such as a planarization layer, a pixel definition layer, a light emitting layer, an encapsulation layer, etc., are also formed on the third metal traces 14, which are not shown in fig. 1 and 2.
In an embodiment, the display panel 1 includes an underlayer 11, a first metal trace 12, a second metal trace 13, and a third metal trace 14. The lower liner layer 11 is a general term for the functional film layer under the first metal trace 12 and the second metal trace 13, and the lower liner layer 11 includes a substrate (e.g., a flexible substrate or a glass substrate), a buffer layer, and the like. The first metal trace 12, the second metal trace 13 and the third metal trace 14 are formed on the underlayer 11 based on the underlayer 11.
The first metal trace 12 and the second metal trace 13 are located on the underlayer 11. The first metal trace 12 and the second metal trace 13 may be in the same layer structure; or the second metal trace 13 is located above the first metal trace 12, and the two are different layer structures, which will be described in detail below.
The third metal trace 14 is located above the first metal trace 12 and the second metal trace 13, the third metal trace 14 is not in contact with the first metal trace 12 and the second metal trace 13, and an inorganic layer such as an interlayer dielectric layer (ILD) is formed between the third metal trace 14 and the first metal trace 12 and the second metal trace 13 to form insulation. In addition, orthographic projections of the first metal wire 12 and the second metal wire 13 on the lower liner 11 are at least partially overlapped with orthographic projections of the third metal wire 14 on the lower liner 11, so that the first metal wire 12 and the second metal wire 13 form coupling capacitance with the third metal wire 14 respectively. It is understood that there may be no other metal trace between the first metal trace 12 and the third metal trace 14, and between the second metal trace 13 and the third metal trace 14, so as to avoid affecting the coupling capacitance formed by the first metal trace 12 and the second metal trace 13 and the third metal trace 14, respectively.
The third metal trace 14 is connected to a fixed potential, which is fixed. Due to the existence of the coupling capacitance, the third metal trace 14 can stabilize the potential of the first metal trace 12, so as to reduce the influence degree of the potential of the first metal trace 12 by the parasitic capacitance (the parasitic capacitance exists between the first metal trace 12 and the second metal trace 13). In addition, the third metal trace 14 can also stabilize the potential of the second metal trace 13, and the variation of the potential of the second metal trace 13 can be reduced when the potential of the second metal trace 13 changes, so as to reduce the influence of the potential change of the second metal trace 13 on the potential of the first metal trace 12, further reduce the influence of the potential of the first metal trace 12 on the parasitic capacitance, and also reduce the influence of crosstalk caused by the parasitic capacitance between the first metal trace 12 and the second metal trace 13, thereby improving the display effect of the display panel 1.
In the present embodiment, there is no overlap in the orthographic projections of the first metal trace 12 and the second metal trace 13 on the underlayer 11, so as to reduce the parasitic capacitance between the first metal trace 12 and the second metal trace 13. Certainly, in other embodiments of the present invention, orthographic projections of the first metal trace 12 and the second metal trace 13 on the underlayer 11 may also overlap, and by the way in this embodiment that the first metal trace 12 and the second metal trace 13 respectively form a coupling capacitance with the third metal trace 14 and the third metal trace 14 is connected to a fixed potential, the potentials of the first metal trace 12 and the second metal trace 13 can be stabilized as well, so as to reduce the influence of crosstalk caused by a parasitic capacitance between the first metal trace 12 and the second metal trace 13, and further improve the display effect of the display panel 1.
Please continue to refer to fig. 1-2. The first metal trace 12 may be a gate of the driving transistor, the second metal trace 13 may be a Data signal line (Data), and the first metal trace 12 and the second metal trace 13 at this time are different layer structures. The third metal wiring 14 is used for stabilizing the electric potentials of the grid electrode of the driving transistor and the data signal line, reducing the influence of the electric potential change of the data signal line on the electric potential of the grid electrode of the driving transistor, ensuring that the driving transistor has enough conduction degree, enabling a power supply signal written into the light-emitting device on a power supply signal line (Vdd) to meet the requirement, enabling the light-emitting device to normally emit light for display, and further solving the problem of uneven display in the prior art.
Referring to fig. 3-4, fig. 3 is a schematic structural diagram of another embodiment of a display panel of the invention, and fig. 4 is a schematic cross-sectional structural diagram of the display panel shown in fig. 3 in the direction B-B. It is understood that other functional film layers of the display panel 1, such as a planarization layer, a pixel definition layer, a light emitting layer, an encapsulation layer, etc., are also formed on the third metal traces 14, which are not shown in fig. 3 and 4.
In an alternative embodiment, the first metal trace 12 is a jumper structure connected to the gate 21 of the driving transistor, the first metal trace 12 and the second metal trace 13 are disposed on the same layer at this time, and the first metal trace 12 and the gate 21 of the driving transistor are different layer structures, and the first metal trace 12 and the gate 21 of the driving transistor are electrically connected through the wire changing hole 22, so as to reduce the overlapping area between the gate 21 of the driving transistor and other signal lines in the display panel 1, thereby reducing the parasitic capacitance of the gate 21 of the driving transistor, and facilitating to improve the display effect of the display panel 1. And the orthographic projections of the parts of the first metal wire 12 and the second metal wire 13 which are arranged in the same layer on the underlayer 11 at least partially overlap with the orthographic projections of the third metal wire 14 on the underlayer 11.
Specifically, the gate 21 of the driving transistor needs to be connected to the target circuit structure 24, wherein the target circuit structure 24 is a conventional circuit portion of a conventional display panel, and is understood by those skilled in the art and will not be described herein again. Since the coverage area of the gate electrode 21 of the driving transistor is large, if a jumper structure is not adopted, the gate electrode 21 of the driving transistor needs to be directly connected with the target circuit structure 24 through the scanning signal line 23, which may cause overlap between the gate electrode 21 of the driving transistor and the scanning signal line 23, and the overlap area between the gate electrode 21 of the driving transistor and the scanning signal line 23 is large, resulting in large parasitic capacitance. By adopting the jumper structure, that is, the first metal trace 12 is connected to the gate 21 of the driving transistor, and the first metal trace 12 is connected to the target circuit structure 24, so that the gate 21 of the driving transistor is connected to the target circuit structure 24, which means that no overlap is formed between the gate 21 of the driving transistor and the scanning signal line 23, instead, the first metal trace 12 with a smaller line width is overlapped with the scanning signal line 23, and the overlapping area between the first metal trace 12 and the scanning signal line 23 is much smaller than the overlapping area between the gate 21 of the driving transistor and the scanning signal line 23, so that the parasitic capacitance between the first metal trace 12 and the scanning signal line 23 is much smaller than the parasitic capacitance between the gate 21 of the driving transistor and the scanning signal line 23 when the jumper structure is not adopted, and therefore the parasitic capacitance of the gate 21 of the driving transistor can be reduced, so as to improve the display effect of the display panel 1.
The potential of the first metal trace 12 is the same as the potential of the gate 21 of the driving transistor, which stabilizes the potential of the first metal trace 12, i.e., stabilizes the potential of the gate 21 of the driving transistor, so that the third metal trace 14 and the first metal trace 12 form a coupling capacitor, and further stabilizes the potential of the first metal trace 12.
Please continue to refer to fig. 1-2. In the present embodiment, orthographic projections of the first metal trace 12 and the second metal trace 13 on the underlying layer 11 respectively at least partially overlap with orthographic projections of the third metal trace 14 on the underlying layer 11 to form a coupling capacitor. In order to increase the coupling capacitance and improve the ability of the third metal trace 14 to stabilize the potentials of the first metal trace 12 and the second metal trace 13, the orthographic projections of the first metal trace 12 and the second metal trace 13 on the underlayer 11 are located in the area defined by the orthographic projection of the third metal trace 14 on the underlayer 11, that is, the third metal trace 14 completely covers the first metal trace 12 and the second metal trace 13, so that the overlapping area of the third metal trace 14, the first metal trace 12 and the second metal trace 13 is maximized.
Please continue to refer to fig. 1-2. In this embodiment, the display panel 1 further includes a plurality of pixels arranged in an array, and each pixel may be a sub-pixel corresponding to a different luminescent color (e.g., R, G, B, etc.), or each pixel may be a complete pixel unit capable of outputting complete color system light, which is not limited herein. Including adjacent first and second pixels 31 and 32. Orthographic projections of the first metal wire 12 corresponding to the first pixel 31 and the second metal wire 13 corresponding to the second pixel 32 on the lower layer 11 respectively at least partially overlap with orthographic projections of the same third metal wire 14 on the lower layer 11. And the pixels of the entire display panel 1 are composed of several of the above-mentioned adjacent first pixels 31 and second pixels 32. Preferably, the first metal wire 12 corresponding to the first pixel 31 and the second metal wire 13 corresponding to the second pixel 32 are completely covered by the same third metal wire 14.
That is to say, for a certain pixel, the electric potential of the gate of the driving transistor in the corresponding pixel circuit is mainly subjected to the electric potential crosstalk of the data signal line of the adjacent pixel, so the electric potential of the gate of the driving transistor of the pixel and the electric potential of the data signal line of the adjacent pixel are stabilized by the third metal routing 14, that is, the influence of the crosstalk caused by the parasitic capacitance on the electric potential of the gate of the driving transistor of the pixel can be greatly reduced, which is beneficial to the normal light emitting display of the pixel.
Please continue to refer to fig. 1-2. In the present embodiment, the third metal trace 14 is connected to the power signal line (Vdd) or the reference voltage signal line (Vref). Fig. 1-2 illustrate a case where the third metal trace 14 is connected to the reference voltage signal line 15, and the electrical connection between the third metal trace 14 and the reference voltage signal line 15 can be achieved through the wire replacement hole 151, which is merely an example and is not a limitation on the form of connecting the third metal trace 14 to the fixed potential. Since the potentials of the power signal line and the reference voltage signal line are constant, the third metal wire 14 is connected to the power signal line or the reference voltage signal line, so that the potential of the third metal wire 14 can be fixed, and the potential of the first metal wire 12 and the potential of the second metal wire 13 can be stabilized by using the third metal wire 14 with the fixed potential.
Please refer to fig. 5. In the present embodiment, the display panel 1 further includes a planarization layer 16. The planarization layer 16 contacts and covers the third metal trace 14 to form functional film layers such as an anode, a light emitting layer, a cathode, and an encapsulation layer on the planarization layer 16.
Please continue to refer to fig. 5. In an embodiment, the display panel 1 further includes a first metal plate 17 and a second metal plate 18 located above the first metal plate 17. A capacitor insulating layer (CI) is formed between the first metal plate 17 and the second metal plate 18 to make the first metal plate 17 and the second metal plate 18 not contact with each other and be insulated, so that a first storage capacitor is formed between the first metal plate 17 and the second metal plate 18. The first storage capacitor participates in a storage capacitor (Cst) forming the pixel circuit, and two poles of the storage capacitor are respectively connected with the gate and the source of the driving transistor, so that the storage capacitor also has the capability of stabilizing the gate potential of the driving transistor, and the storage capacitor of the pixel circuit is increased, so that the capability of stabilizing the gate potential of the driving transistor by the storage capacitor can be improved.
Specifically, the display panel 1 further includes a third metal plate 19 disposed on the same layer as the third metal trace 14, that is, the third metal trace 14 and the third metal plate 19 belong to the same layer of metal structure, and the planarization layer 16 of the display panel 1 contacts and covers the third metal trace 14 and the third metal plate 19.
The third metal plate 19 is located above the second metal plate 18, and an inorganic layer such as an interlayer dielectric layer is formed between the third metal plate 19 and the second metal plate 18 so that they are not in contact with each other and are insulated. The orthographic projections of the third metal plate 19 and the second metal plate 18 on the underlayer 11 at least partially overlap, so that a second storage capacitor is formed between the third metal plate 19 and the second metal plate 18. Preferably, the third metal plate 19 completely covers the second metal plate 18 to maximize the second storage capacitance. The second storage capacitor is connected in parallel with the first storage capacitor, and the storage capacitor of the pixel circuit is the sum of the first storage capacitor and the second storage capacitor, so that the storage capacitor of the pixel circuit is increased on the basis of the first storage capacitor, the capability of the storage capacitor for stabilizing the gate potential of the driving transistor is improved, the degree of influence of the parasitic capacitance on the potential of the first metal wire 12 (namely, the potential of the gate of the driving transistor) is further reduced, and the display effect of the display panel 1 is improved.
It should be noted that, in the same layer arrangement and the same layer structure described in the embodiments of the present invention, for example, the first metal trace 12 and the second metal trace 13 are arranged in the same layer, which does not mean that the heights of the horizontal planes of the first metal trace 12 and the second metal trace 13 are the same, but the heights of the horizontal planes of the first metal trace 12 and the second metal trace 13 in the stacked structure of the display panel 1 are different.
In summary, in the display panel provided by the present invention, the first metal trace and the second metal trace respectively form a coupling capacitor with the third metal trace. The third metal wire is connected to a fixed potential, that is, the potential of the third metal wire is fixed. Due to the existence of the coupling capacitor, the third metal wire with fixed potential can stabilize the potential of the first metal wire, so that the influence degree of the potential of the first metal wire by the parasitic capacitor (the parasitic capacitor exists between the first metal wire and the second metal wire) is reduced. And the third metal is walked and can also be stabilized the electric potential of second metal and walk the line, can reduce the change of second metal when the electric potential of second metal is walked the line electric potential to reduce the electric potential change of second metal and walked the influence of line electric potential to first metal, further reduced the electric potential of first metal and walked the degree that the electric potential of line is influenced by parasitic capacitance, just also reduced the influence that parasitic capacitance between first metal is walked and the second metal and is aroused the crosstalk, and then improved display panel's display effect.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a display device according to an embodiment of the invention.
In an embodiment, the display device 4 includes a driving circuit 41 and a display panel 42, and the driving circuit 41 is coupled to the display panel 42 for driving the display panel 42 to implement its display function. The display panel 42 is the display panel described in the above embodiments, and will not be described herein again.
In addition, in the present invention, unless otherwise expressly specified or limited, the terms "connected," "stacked," and the like are to be construed broadly, e.g., as meaning permanently connected, detachably connected, or integrally formed; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (6)
1. A display panel, comprising:
an underlayer;
a first metal trace located on the underlying layer;
a second metal trace located on the lower liner layer;
a third metal trace, which is located above the first metal trace and the second metal trace, and which is not in contact with the first metal trace and the second metal trace, and which is connected to a fixed potential;
wherein orthographic projections of the first metal wire and the second metal wire on the lower lining layer are respectively at least partially overlapped with orthographic projections of the third metal wire on the lower lining layer, so that the first metal wire and the second metal wire respectively form coupling capacitance with the third metal wire;
the second metal wiring is a data signal line;
the third metal routing is connected to a power signal line;
the first metal routing and the second metal routing are arranged on the same layer, the first metal routing is connected to a grid electrode of a driving transistor and is connected with a target circuit structure through the first metal routing, no overlapping is formed between the grid electrode of the driving transistor and a scanning signal line, overlapping is formed between the first metal routing and the scanning signal line, the line width of the first metal routing is smaller than that of the grid electrode of the driving transistor, and orthographic projections of the parts, arranged on the same layer, of the first metal routing and the second metal routing on the lower lining layer are at least partially overlapped with orthographic projections of the third metal routing on the lower lining layer.
2. The display panel of claim 1, wherein an orthographic projection of the first metal trace and the second metal trace on the underlying layer is within an orthographic projection of the third metal trace on the underlying layer.
3. The display panel according to claim 1, wherein the display panel further comprises a plurality of pixels arranged in an array, the plurality of pixels include adjacent first pixels and second pixels, and orthographic projections of the first metal traces corresponding to the first pixels and the second metal traces corresponding to the second pixels on the lower liner at least partially overlap with orthographic projections of the same third metal traces on the lower liner.
4. The display panel according to any one of claims 1 to 3, wherein the display panel further comprises a planarization layer, and the planarization layer contacts and covers the third metal trace.
5. The display panel according to claim 1, wherein the display panel further comprises a first metal plate and a second metal plate located above the first metal plate, and a first storage capacitor is formed between the first metal plate and the second metal plate;
the display panel further comprises a third metal polar plate arranged on the same layer as the third metal routing, the third metal polar plate is positioned above the second metal polar plate and is not in contact with the second metal polar plate, and orthographic projections of the third metal polar plate and the second metal polar plate on the lower lining layer are at least partially overlapped, so that a second storage capacitor is formed between the third metal polar plate and the second metal polar plate;
wherein the second storage capacitor is connected in parallel with the first storage capacitor.
6. A display device, comprising a driving circuit and the display panel of any one of claims 1 to 5, wherein the driving circuit is coupled to the display panel for driving the display panel to realize its display function.
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| CN111081141B (en) * | 2020-01-08 | 2022-04-26 | 昆山国显光电有限公司 | Array substrate, display panel and display device |
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| CN104701328A (en) * | 2015-03-25 | 2015-06-10 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof and display device |
| CN109389907A (en) * | 2018-12-11 | 2019-02-26 | 厦门天马微电子有限公司 | Display panel and display device |
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