CN110264948A - Shift register cell, driving method, gate driving circuit and display device - Google Patents
Shift register cell, driving method, gate driving circuit and display device Download PDFInfo
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- CN110264948A CN110264948A CN201910554453.1A CN201910554453A CN110264948A CN 110264948 A CN110264948 A CN 110264948A CN 201910554453 A CN201910554453 A CN 201910554453A CN 110264948 A CN110264948 A CN 110264948A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/3433—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices
- G09G3/344—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices based on particles moving in a fluid or in a gas, e.g. electrophoretic devices
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
Abstract
The invention discloses a kind of shift register cell, driving method, gate driving circuit and display devices, belong to field of display technology.It include: input module, output module, pull-down control module and pull-down module；Input module is used under the control of the first clock signal from the first clock signal terminal, provides the input signal from input signal end to the first pull-up node；Output module is used under the control of the first pull-up node, provides the second clock signal from second clock signal end to output end；Pull-down control module is used under the control of the first clock signal, provides the first power supply signal from the first power end to the first pull-down node, and, the current potential of the first pull-down node is controlled based on third clock signal；Pull-down module is used under the control of the first pull-down node, provides the first power supply signal to output end and the first pull-up node.The present invention can guarantee pull-down module to the noise reduction effect of output end.
Description
Technical field
The present invention relates to field of display technology, in particular to a kind of shift register cell, driving method, gate driving electricity
Road and display device.
Background technique
When displaying an image, it is right using gate driving circuit (Gate Driver on Array, GOA) to need for display device
Pixel unit is scanned, and gate driving circuit (also referred to as shift register) includes multiple cascade shift register cells, often
A shift register cell corresponds to one-row pixels unit, is realized by multiple shift register cells to multirow pixel in display device
The progressive scan of unit drives, to show image.Wherein, after completing the driving to certain row pixel unit, certain is needed through this
The corresponding shift register cell of row pixel unit carries out noise reduction to the output end of the shift register cell, to guarantee that this is defeated
The stability of outlet output signal.
In the related technology, shift register cell includes: pull-down module, by providing to the pull-down module in effectively electricity
It is in running order to can control the pull-down module for the signal of position (such as high level), so that by the pull-down module to the shifting
The output end of bit register unit carries out noise reduction.
But in the course of work of shift register cell, pull-down module is usually in the drive of effective current potential for a long time
Under dynamic, it be easy to cause the electrology characteristic of the pull-down module to be affected, influences pull-down module to the noise reduction effect of output end, cause
It is abnormal that display occurs in display device.
Summary of the invention
The present invention provides a kind of shift register cell, driving method, gate driving circuit and display devices, can solve
Certainly element included by each shift register cell is more in the related technology, leads to gate driving circuit institute in a display device
The larger problem of the chip area of occupancy.The technical solution is as follows:
In a first aspect, providing a kind of shift register cell, comprising: input module, output module, pull-down control module
And pull-down module；
The input module is connect with input signal end, the first clock signal terminal and the first pull-up node respectively, described defeated
Enter module under the control of the first clock signal from first clock signal terminal, the first pull-up node of Xiang Suoshu to be mentioned
For the input signal from the input signal end；
The output module is connect with second clock signal end, first pull-up node and output end respectively, described defeated
Module is used under the control of first pull-up node out, and Xiang Suoshu output end is provided from the second clock signal end
Second clock signal；
The pull-down control module respectively with first clock signal terminal, third clock signal terminal, the first power end and
The connection of first pull-down node, the pull-down control module is used under the control of first clock signal, under Xiang Suoshu first
Node is drawn to provide the first power supply signal from first power end, and, based on from the third clock signal terminal
Third clock signal controls the current potential of first pull-down node；
The pull-down module respectively with first power end, first pull-down node, first pull-up node and
Output end connection, the pull-down module are used under the control of first pull-down node, Xiang Suoshu output end and described
First pull-up node provides first power supply signal.
Optionally, the pull-down module includes: the first transistor and second transistor；
The grid of the first transistor is connect with first pull-down node, the first of the first transistor extremely with
The first power end connection, the second pole of the first transistor is connect with first pull-up node；
The grid of the second transistor is connect with first pull-down node, the first pole of the second transistor and institute
The connection of the first power end is stated, the second pole of the second transistor is connect with the output end.
Optionally, the pull-down control module is also connect with the second clock signal end, and the pull-down control module is also
For under the control of the second clock signal, the first pull-down node of Xiang Suoshu to provide the third clock signal.
Optionally, the pull-down control module includes: the 14th transistor, third transistor, the 4th transistor, the 5th crystalline substance
Body pipe and first capacitor device；
The grid of 14th transistor and first is extremely connect with the second clock signal end, and the described 14th is brilliant
Second pole of body pipe is connect with the second pull-down node；
The grid of the third transistor is connect with second pull-down node, the first pole of the third transistor and institute
The connection of third clock signal terminal is stated, the second pole of the third transistor is connect with first pull-down node；
The grid of 4th transistor is connect with first clock signal terminal, the first pole of the 4th transistor with
The first power end connection, the second pole of the 4th transistor is connect with first pull-down node.
The grid of 5th transistor is connect with first clock signal terminal, the first pole of the 5th transistor with
The first power end connection, the second pole of the 5th transistor is connect with second pull-down node；
One end of the first capacitor device is connect with second pull-down node, the other end of the first capacitor device and institute
State the connection of the first pull-down node.
Optionally, the shift register cell further include: be connected on the input module and first pull-up node
Between feedback module, and the feedback module is connect by the second pull-up node with the input module；
The feedback module also connects with first pull-up node, first clock signal terminal and second source end respectively
It connects, the feedback module is used under the control of first pull-up node, and the second pull-up node of Xiang Suoshu is provided from described
The second source signal at second source end, and, the input module is used under the control of first clock signal, is passed through
The feedback module provides the input signal to first pull-up node.
Optionally, the feedback module includes: the 6th transistor and the 7th transistor；
The grid of 6th transistor is connect with first clock signal terminal, the first pole of the 6th transistor with
The second pull-up node connection, the second pole of the 6th transistor is connect with first pull-up node；
The grid of 7th transistor is connect with first pull-up node, the first pole of the 7th transistor and institute
The connection of second source end is stated, the second pole of the 7th transistor is connect with second pull-up node.
Second aspect provides a kind of driving method of shift register cell, and the method is for driving shift LD
Device unit, the shift register cell include: input module, output module, pull-down control module and pull-down module, the side
Method includes: charging stage, output stage and the first noise reduction stage；
In the charging stage, the current potential of the first clock signal of the first clock signal terminal output is effective current potential, input
Signal end output input signal current potential be effective current potential, the input module under the control of first clock signal,
The input signal for being in effective current potential is provided to the first pull-up node；
In the output stage, the current potential of the second clock signal of second clock signal end output is effective current potential, described
The current potential of first pull-up node remains effective current potential, and the output module is under the control of first pull-up node, to defeated
Outlet provides the second clock signal for being in effective current potential；
In the first noise reduction stage, the current potential of the third clock signal of third clock signal terminal output is effective current potential,
The current potential of the power supply signal of first power end output is invalid current potential, and the pull-down control module is at the first pull-down node offer
In the third clock signal of effective current potential, the pull-down module is under the control of first pull-down node, Xiang Suoshu output end
The first power supply signal for being in invalid current potential is provided with first pull-up node.
Optionally, the shift register cell further include: be connected on the input module and first pull-up node
Between feedback module, and the feedback module is connect by the second pull-up node with the input module, and the method is also wrapped
It includes:
In the output stage, the current potential of first pull-up node remains effective current potential, the output of second source end
The current potential of second source signal is effective current potential, and the current potential of first clock signal is effective current potential, and the feedback module exists
Under the control of first pull-up node, the second pull-up node of Xiang Suoshu provides the second source signal for being in effective current potential.
The third aspect, provides a kind of gate driving circuit, and the gate driving circuit includes: multiple cascade first party
Any shift register cell in face.
Fourth aspect, provides a kind of display device, and the display device includes the electricity of gate driving described in first aspect
Road.
5th aspect, provides a kind of storage medium, computer program, the computer is stored in the storage medium
The control method of shift register cell described in second aspect is realized when program is executed by processor.
Technical solution provided by the invention has the benefit that
Shift register cell, driving method, gate driving circuit and display device provided in an embodiment of the present invention, due to
The current potential of first pull-down node can occur according to the current potential of the first clock signal, the first power supply signal and third clock signal
Variation, and since the current potential of first clock signal He the third clock signal changes according to the fixed cycle, so that should
The current potential of first pull-down node without being in effective current potential for a long time, compared to the relevant technologies, can reduce because downward for a long time
Drawing-die block provides effective current potential to be influenced caused by the pull-down module electrology characteristic, ensure that pull-down module to the noise reduction of output end
Effect guarantees the display effect of display device.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is a kind of structural schematic diagram of shift register cell in the related technology provided in an embodiment of the present invention；
Fig. 2 is a kind of timing diagram of the driving process of shift register cell shown in FIG. 1 provided in an embodiment of the present invention；
Fig. 3 is a kind of structural schematic diagram of shift register cell provided in an embodiment of the present invention；
Fig. 4 is a kind of circuit diagram of shift register cell provided in an embodiment of the present invention；
Fig. 5 is the structural schematic diagram of another shift register cell provided in an embodiment of the present invention；
Fig. 6 is the circuit diagram of another shift register cell provided in an embodiment of the present invention；
Fig. 7 is a kind of flow chart of the driving method of shift register cell provided in an embodiment of the present invention；
Fig. 8 is a kind of timing diagram of the driving process of shift register cell provided in an embodiment of the present invention；
Fig. 9 is a kind of structural schematic diagram of gate driving circuit provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
The transistor used in all embodiments of the invention all can be thin film transistor (TFT) or field-effect tube or other characteristics
Identical device is mainly switching transistor according to transistor used by effect the embodiment of the present invention in circuit.By
It is symmetrical in the source electrode of the switching transistor used here, drain electrode, so its source electrode, drain electrode can be interchanged.In this hair
In bright embodiment, wherein it will be known as the first order by source electrode, drain electrode is known as the second level.The centre of transistor is provided by the form in attached drawing
End is grid, signal input part is source electrode, signal output end is drain electrode.In addition, switch crystal used by the embodiment of the present invention
Pipe may include p-type switching transistor and N-type switching transistor, wherein p-type switching transistor is led when grid is low level
It is logical, end when grid is high level, N-type switching transistor is connected when grid is high level, cuts when grid is low level
Only.In addition, multiple signals in each embodiment of the present invention are all corresponding with high level and low level, effective current potential of signal is to make
The current potential that switching transistor is opened, such as: for p-type switching transistor, low level is effective current potential, switchs crystal for N-type
Pipe, high level are effective current potential.
As known for inventor, shift register cell includes: pull-down module.For example, as shown in Figure 1, the pull-down module
It include: the pull-down transistor T3 that drain electrode is connect with output end OUT (N).Have by providing to be in the grid of the pull-down transistor
The signal for imitating current potential (such as high level) can control pull-down transistor conducting, to pass through the pull-down transistor to the displacement
The output end of register cell carries out noise reduction.Wherein, input transistors T1 is used under the control of clock signal terminal CLK1-1, is led to
It crosses the signal from input terminal OUT (N-1) (that is to say higher level's output end) and pulls up node Q charging.Output transistor T2 is used for
Under the control of pull-up node Q, the signal from clock signal terminal CLK1-2 is provided to output end OUT (N).Capacitor is for making
Pull-up node Q variation synchronous with the current potential of output end OUT (N).First drop-down control transistor T4 is used in junior output end OUT
(N+1) under control, the current potential pull-up of pull-down node QB is effectively electricity by the signal exported by junior output end OUT (N+1)
Position.Second drop-down control transistor T5 is used under the control of pull-up node Q, by the signal of power end VGL, by pull-down node
The current potential drop-down of QB is invalid current potential.
From the driver' s timing figure of the shift register cell shown in Fig. 2 it can be seen that shift register cell work
During work, loads and be only in invalid current potential in the period of driving pixel unit in the signal on the pull-down transistor grid
(such as low level).It is easy to cause the threshold voltage shift of the pull-down transistor in this way, causes pull-down transistor to output end
Noise reduction is not thorough, and then it is abnormal to cause display device display occur.For example, when effective current potential is high level, the lower crystal pulling
The pipe range time is under the driving of high level, and positive excursion occurs in the threshold voltage that will lead to the pull-down transistor, causes to pass through
The pull-down transistor is not thorough the noise reduction of output end, causes display device display occur abnormal.
Fig. 3 is a kind of structural schematic diagram of shift register cell provided in an embodiment of the present invention, with reference to Fig. 3, the displacement
Register cell may include: input module 10, output module 20, pull-down control module 30 and pull-down module 40.
Input module 10 is connect with input signal end IN, the first clock signal terminal CLK1 and the first pull-up node P1 respectively,
Input module 10 is used under the control of the first clock signal from the first clock signal terminal CLK1, to the first pull-up node P1
Input signal from input signal end IN is provided.
Output module 20 is connect with second clock signal end CLK2, the first pull-up node P1 and output end OUT respectively, output
Module 20 is used under the control of the first pull-up node P1, provides the from second clock signal end CLK2 to output end OUT
Two clock signals.
Pull-down control module 30 respectively with the first clock signal terminal CLK1, third clock signal terminal CLK3, the first power end
VGL and the first pull-down node N1 connection, pull-down control module 30 are used under the control of the first clock signal, to the first drop-down section
Point N1 provides the first power supply signal from the first power end VGL, and, the first pull-down node is controlled based on third clock signal
The current potential of N1.
Pull-down module 40 respectively with the first power end VGL, the first pull-down node N1, the first pull-up node P1 and output end
OUT connection, pull-down module 40 are used under the control of the first pull-down node N1, mention to output end OUT and the first pull-up node P1
For the first power supply signal.
In conclusion shift register cell provided in an embodiment of the present invention, since the current potential of the first pull-down node can be with
It is changed according to the current potential of the first clock signal, the first power supply signal and third clock signal, and due to first clock
Signal and the current potential of the third clock signal change according to the fixed cycle, so that the current potential of first pull-down node is not necessarily to
It is in effective current potential for a long time, compared to the relevant technologies, can reduce and provide effective current potential to this because pulling down module for a long time
It is influenced caused by pull-down module electrology characteristic, ensure that pull-down module to the noise reduction effect of output end, guarantees the aobvious of display device
Show effect.
Optionally, as shown in Figures 4 to 6, pull-down module 40 may include: the first transistor M1 and second transistor M2.
The grid of the first transistor M1 is connect with the first pull-down node N1, and the first of the first transistor M1 is extremely electric with first
Source VGL connection, the second pole of the first transistor M1 are connect with the first pull-up node P1.
The grid of second transistor M2 is connect with the first pull-down node N1, the first pole of second transistor M2 and the first power supply
VGL connection is held, the second pole of second transistor M2 is connect with output end OUT.
In a kind of achievable mode, please continue to refer to Fig. 4 and Fig. 6, pull-down control module 30 may include: third crystal
Pipe M3 and the 4th transistor M4.
The grid of third transistor M3 and first is extremely connect with third clock signal terminal CLK3, and the of third transistor M3
Two poles are connect with the first pull-down node N1.Alternatively, when the first pole third transistor M3 is connect with third clock signal terminal CLK3,
The grid of third transistor M3 can also be connect with other signal ends.
The grid of 4th transistor M4 is connect with the first clock signal terminal CLK1, the first pole and first of the 4th transistor M4
Power end VGL connection, the second pole of the 4th transistor M4 is connect with the first pull-down node N1.
Please continue to refer to Fig. 5 and Fig. 6, in the achievable mode of another kind, when pull-down control module 30 can also be with second
The CLK2 connection of clock signal end, pull-down control module 30 are also used under the control of second clock signal, to the first pull-down node N1
Third clock signal is provided.
At this point, as shown in figure 5, the pull-down control module 30 may include: the first control submodule 301 and the second control
Module 302.First control submodule 301 is respectively and under the first clock signal terminal CLK1, second clock signal end CLK2, second
Node N2 and the first power end VGL connection are drawn, which is used under the control of the first clock signal, to
The second pull-down node N2 provides the first power supply signal, and, under the control of second clock signal, to second pull-down node
N2 provides the second clock signal.Second control submodule 302 respectively with third clock signal terminal CLK3, the first pull-down node
N1, the second pull-down node N2, the first clock signal terminal CLK1 and the first power end VGL, second control submodule 302 are used for
Under the control of first clock signal, the first power supply signal is provided to the second pull-down node N2, and, in the second pull-down node N2
Control under, to the second pull-down node N2 provide third power supply signal.
At this point, referring to FIG. 6, first control submodule 301 includes: the 14th transistor M14 and the 5th transistor M5.
The grid of 14th transistor M14 and first is extremely connect with second clock signal end CLK2, the 14th transistor
The second pole of M14 is connect with the second pull-down node N2.
The grid of 5th transistor M5 is connect with the first clock signal terminal CLK1, the first pole and first of the 5th transistor M5
Power end VGL connection, the second pole of the 5th transistor M5 is connect with the second pull-down node N2.
Referring to FIG. 6, second control submodule 302 includes: third transistor M3, the 4th transistor M4 and first capacitor
Device C1.
The grid of third transistor M3 is connect with the second pull-down node N2, the first pole of third transistor M3 and third clock
Signal end CLK3 connection, the second pole of third transistor M3 are connect with the first pull-down node N1.
The grid of 4th transistor M4 is connect with the first clock signal terminal CLK1, the first pole and first of the 4th transistor M4
Power end VGL connection, the second pole of the 4th transistor M4 is connect with the first pull-down node N1.
One end of first capacitor device C1 is connect with the second pull-down node N2, and the other end of first capacitor device and the first drop-down save
Point N1 connection.
The current potential of the second pull-down node N2 is controlled by the first control submodule 301, then passes through second pull-down node N2
The on state of the second control submodule 302 is controlled, so that mentioning by the second control submodule 302 to the first pull-down node N1
Eminence can provide the letter for being in effective current potential to the first pull-down node N1 with losing without threshold value when the signal of effective current potential
Number, it can efficiently control the current potential of first pull-down node N1.
Please continue to refer to Fig. 4 and Fig. 6, output module 20 may include: the 8th transistor M8.
The grid of 8th transistor M8 is connect with the first pull-up node P1, the first pole of the 8th transistor M8 and second clock
Signal end CLK2 connection, the second pole of the 8th transistor M8 is connect with output end OUT.
Optionally, with continued reference to FIG. 5, output module 20 can also be connect with cascade signal end CR, the cascade signal end
CR with the input signal end IN of the cascade shift register cell of shift register cell for connecting, at this point, output module 20
It is also used under the control of the first pull-up node P1, provides second clock signal to cascade signal end CR.
Correspondingly, pull-down module 40 is also connect with cascade signal end CR, pull-down module 40 is also used in the first pull-down node
Under the control of N1, the first power supply signal is provided to cascade signal end CR.
With continued reference to FIG. 6, output module 20 can also include: the 9th transistor M9.
The grid of 9th transistor M9 is connect with the first pull-up node P1, the first pole of the 9th transistor M9 and second clock
Signal end CLK2 connection, the second pole of the 9th transistor M9 are connect with cascade signal end CR.
Optionally, with continued reference to FIG. 6, the output module 20 can also include: the second capacitor C2, second capacitor
One end of C2 is connect with the grid of the 9th transistor M9, the other end of second capacitor C2 and the second of the 9th transistor M9
Pole connection.
Correspondingly, with continued reference to FIG. 6, pull-down module 40 can also include: the tenth transistor M10.
The grid of tenth transistor M10 is connect with the first pull-down node N1, the first pole of the tenth transistor M10 and the first electricity
Source VGL connection, the second pole of the tenth transistor M10 are connect with cascade signal end CR.
In one implementation, with continued reference to FIG. 4, input module 10 may include: the 11st transistor M11.The
The grid of 11 transistor M11 is connect with the first clock signal terminal CLK1, the first pole of the 11st transistor M11 and input signal
IN connection is held, the second pole of the 11st transistor M11 is connect with the first pull-up node P1.
In another implementation, with continued reference to FIG. 6, input module 10 may include: the 11st transistor M11.
The grid of 11st transistor M11 is connect with the first clock signal terminal CLK1, and the first pole of the 11st transistor M11 and input are believed
Number end IN connection, the second pole of the 11st transistor M11 is connect with the second pull-up node P2.
With continued reference to FIG. 5, shift register cell can also include: reseting module 50.Reseting module 50 is respectively and multiple
Position signal end RST, the first power end VGL, the second pull-down node N2 and the first pull-up node P1 connection, reseting module 50 are used for
Under the control of reset signal from reset signal end RST, first is provided to the first pull-down node N1 and the first pull-up node P1
Power supply signal.
With continued reference to FIG. 6, reseting module 50 may include: the tenth two-transistor M12 and the 13rd transistor M13.
The grid of tenth two-transistor M12 is connect with reset signal end RST, the first pole of the tenth two-transistor M12 and the
One power end VGL connection, the second pole of the tenth two-transistor M12 is connect with the second pull-down node N2.
The grid of 13rd transistor M13 is connect with reset signal end RST, the first pole of the 13rd transistor M13 and the
One power end VGL connection, the second pole of the 13rd transistor M13 is connect with the first pull-up node P1.
Further, with continued reference to FIG. 5, shift register cell can also include: to be connected on input module 10 and
Feedback module 60 between one pull-up node P1, the feedback module 60 are connect by the second pull-up node P2 with input module 10.
Also, the feedback module 60 also connects with the first pull-up node P1, the first clock signal terminal CLK1 and second source end VGH respectively
It connects, feedback module 60 is used under the control of the first pull-up node P1, is provided to the second pull-up node P2 and is come from second source end
The second source signal of VGH.Correspondingly, input module 10 is used under the control of the first clock signal, pass through feedback module 60
The input signal from input signal end IN is provided to the first pull-up node P1.
Optionally, as shown in fig. 6, feedback module 60 may include: the 6th transistor M6 and the 7th transistor M7.
The grid of 6th transistor M6 is connect with the first clock signal terminal CLK1, the first pole and second of the 6th transistor M6
Pull-up node P2 connection, the second pole of the 6th transistor M6 is connect with the first pull-up node P1.
The grid of 7th transistor M7 is connect with the first pull-up node P1, the first pole of the 7th transistor M7 and second source
VGH connection is held, the second pole of the 7th transistor M7 is connect with the second pull-up node P2.
In the output stage of shift register cell, second is provided to the second pull-up node P2 by the feedback module 60
Power supply signal, so that the current potential of the current potential of the second pull-up node P2 and the first pull-up node P1 remain effective current potential, it can
Voltage instability caused by leaking electricity because of the first pull-up node P1 is prevented, and then guarantees output stability.
In conclusion shift register cell provided in an embodiment of the present invention, since the current potential of the first pull-down node can be with
It is changed according to the current potential of the first clock signal, the first power supply signal and third clock signal, and due to first clock
Signal and the current potential of the third clock signal change according to the fixed cycle, so that the current potential of first pull-down node is not necessarily to
It is in effective current potential for a long time, compared to the relevant technologies, can reduce and provide effective current potential to this because pulling down module for a long time
It is influenced caused by pull-down module electrology characteristic, ensure that pull-down module to the noise reduction effect of output end, guarantees the aobvious of display device
Show effect.
Fig. 7 is a kind of flow chart of the driving method of shift register cell provided in an embodiment of the present invention, and this method can
With for drive as Fig. 1 to Fig. 6 it is any shown in shift register cell, the shift register cell include: input module 10,
Output module 20, pull-down control module 30 and pull-down module 40, as shown in fig. 7, this method may include:
Step 701, in the charging stage, the first clock signal terminal output the first clock signal current potential be effective current potential,
The current potential of the input signal of input signal end output is effective current potential, and input module is under the control of the first clock signal, to the
One pull-up node provides the input signal for being in effective current potential.
In step 702, output stage, the current potential of the second clock signal of second clock signal end output is effective current potential,
The current potential of first pull-up node remains effective current potential, and output module provides under the control of the first pull-up node to output end
Second clock signal in effective current potential.
Step 703, in the first noise reduction stage, third clock signal terminal output third clock signal current potential be effectively electricity
Position, the current potential of the power supply signal of the first power end output are invalid current potential, and pull-down control module is at the first pull-down node offer
In the third clock signal of effective current potential, pull-down module is under the control of the first pull-down node, to output end and the first pull-up section
Point provides the first power supply signal for being in invalid current potential.
In conclusion the driving method of shift register cell provided in an embodiment of the present invention, due to the first drop-down section
The current potential of point can change according to the current potential of the first clock signal, the first power supply signal and third clock signal, and by
It changes according to the fixed cycle in the current potential of first clock signal He the third clock signal, so that the first drop-down section
The current potential of point without being in effective current potential for a long time, compared to the relevant technologies, can reduce and provide because pulling down module for a long time
Effective current potential is influenced caused by the pull-down module electrology characteristic, ensure that pull-down module to the noise reduction effect of output end, guarantees
The display effect of display device.
Optionally, shift register cell can also include: to be connected between input module 10 and the first pull-up node P1
Feedback module 60, and feedback module 60 is connect by the second pull-up node P2 with input module 10, at this point, this method is also wrapped
It includes:
In output stage, the current potential of the first pull-up node remains effective current potential, the second source of second source end output
The current potential of signal is effective current potential, and the current potential of the first clock signal is effective current potential, control of the feedback module in the first pull-up node
Under system, the second source signal for being in effective current potential is provided to the second pull-up node.
In second noise reduction stage, the first clock signal terminal output the first clock signal current potential be effective current potential, first
The current potential of first power supply signal of power end output is effective current potential, and pull-down module is under the control of the first signal, to the
One pull-down node and the second pull-down node provide the first power supply signal for being in invalid current potential.
Illustratively, Fig. 8 is a kind of timing diagram of the driving process of shift register cell provided in an embodiment of the present invention, with
Each transistor in shift register cell and shift register cell shown in fig. 6 is N-type transistor, effective current potential phase
For invalid current potential be high level for, the driving principle of shift register cell provided in an embodiment of the present invention is discussed in detail.
Referring to FIG. 8, the current potential of the reset signal of reset signal end RST output is height in the first noise reduction stage t1 of the overall situation
Level, the current potential of the signal of other signal ends output are low level, and the first power supply signal of the first power end VGL output is low
Level, the tenth two-transistor M12 and the 13rd transistor M13 are connected under the control of the reset signal, and the first power end VGL is logical
It crosses the tenth two-transistor M12 to provide to the second pull-down node N2 in low level first power supply signal, the first power end VGL is logical
It crosses the 13rd transistor M13 to provide to the first pull-up node P1 in low level first power supply signal, and in first capacitor device
Under the coupling of C1, the current potential of the first pull-down node N1 becomes low level with the current potential of the second pull-down node N2, thus to
One pull-down node N1, the second pull-down node N2 and the first pull-up node P1 are reset.
In charging stage t2, the current potential of the first clock signal of the first clock signal terminal CLK1 output is high level, other
The current potential of the clock signal of clock signal output is low level, and the current potential of the input signal of input signal end IN output is high electricity
Flat, the 11st transistor M11 and the 6th transistor M6 are connected under the control of the first clock signal, and input signal end IN is by being somebody's turn to do
11st transistor M11 provides the input signal for being in high level to the second pull-up node P2, so that second pull-up node P2
Current potential become high level, and the input signal for being in high level is provided to the first pull-up node P1 by the 6th transistor M6,
It charges for the first pull-up node P1, so that the current potential of first pull-up node P1 has a degree of rising.
Also, in charging stage t2, the current potential of the second source signal of second source end VGH output is high level,
And since the first pull-up node P1 is in high level, so that the 7th transistor M7 is led under the control of first pull-up node P1
Logical, which provides the second source for being in high level by the 7th transistor M7 to the second pull-up node P2
Signal, so that the current potential of second pull-up node P2 remains high level.
Meanwhile the 4th transistor M4 and the 5th transistor M5 be connected under the control of the first clock signal, the first power end
VGL provides the first power supply signal for being in invalid point, and the first electricity by the 4th transistor M4 to the first pull-down node N1
Source VGL provides the first power supply signal for being in invalid point by the 5th transistor M5 to the second pull-down node N2, so that
First pull-down node N1 and the second pull-down node N2 remain low level so that the first transistor M1, the tenth transistor M10 and
Second transistor M2 is turned off.
In output stage t3, second clock signal end CLK2 output second clock signal current potential be high level, first
The current potential of pull-up node P1 remains high level, the 8th transistor M8 and the 9th transistor M9 in the control of the first pull-up node P1
Lower conducting, second clock signal end CLK2 are provided to cascade signal end CR by the 8th transistor M8 and are in the second of high level
Clock signal, and, second clock signal end CLK2 is provided to output end OUT in high level by the 9th transistor M9
Second clock signal, to drive the pixel unit in display panel.
Also, in output stage t3, the current potential of the second source signal of second source end VGH output is high level,
7th transistor M7 is connected under the control of the first pull-up node P1, the second source end VGH by the 7th transistor M7 to
Second pull-up node P2 provides the second source signal for being in high level, so that the current potential of second pull-up node P2 remains height
Level.
Meanwhile the 4th transistor M4 be connected under the control of second clock signal, second clock signal end CLK2 by should
4th transistor M4 provides the second clock signal for high level to the second pull-down node N2, pre- to second pull-down node N2
Charging, so that the current potential of second pull-down node N2 has a degree of raising.At this point, due to the first pull-up node P1 and
Two pull-up node P2 are in high level, so that the pressure difference of the first pull-up node P1 and the second pull-up node P2 are smaller, it can
It prevents the first pull-up node P1 from leaking electricity by the 6th transistor M6, is able to maintain the voltage stability of the first pull-up node P1, into
And guarantee the output stability of output end OUT.
In first noise reduction stage t4, the current potential of the third clock signal of third clock signal terminal CLK3 output is high level,
The current potential of the power supply signal of first power end VGL output is low level, and the second pull-down node N2 remains high level, third crystal
Pipe M3 is connected under the control of second pull-down node N2, and third clock signal terminal CLK3 passes through third transistor M3 to first
Pull-down node N1 provides the third clock signal for being in high level, so that the current potential of first pull-down node N1 becomes high level.
Also, under the coupling of first capacitor device C1, the current potential of the second pull-down node N2 can be with the current potential of the first pull-down node N1
It further increases, so that third transistor M3 is fully opened, to guarantee that third clock signal terminal CLK3 loses ground without threshold value
The signal for being in high level is provided to the first pull-down node N1, can efficiently control the electricity of first pull-down node N1
Position.
Correspondingly, the control of the first transistor M1, second transistor M2 and the tenth transistor M10 in first pull-down node N1
The lower conducting of system, so that the first power end VGL is provided to the first pull-up node P1 in low level the by the first transistor M1
One power supply signal is provided to output end OUT by second transistor M2 and is in low level first power supply signal, and the tenth crystalline substance is passed through
Body pipe M10 is provided to cascade signal end CR and is in low level first power supply signal, to the first pull-up node P1, output end
OUT and cascade signal end CR noise reduction.
In second noise reduction stage t5, the current potential of the first clock signal of the first clock signal terminal CLK1 output is high level,
The current potential of first power supply signal of the first power end VGL output is high level, the 4th transistor M4 and the 5th transistor M5 the
It is connected under the control of one clock signal, the first power end VGL is by the 4th transistor M4 at the first pull-down node N1 offer
In the first power supply signal of invalid point, and the first power end VGL is mentioned by the 5th transistor M5 to the second pull-down node N2
For being in the first power supply signal of invalid point, noise reduction is carried out to the first pull-down node N1 and the second pull-down node N2, so that plus
The signal for being loaded in the first transistor M1, second transistor M2 and the tenth transistor M10 is in low level.
The current potential that can be seen that the first pull-down node N1 and the second pull-down node N2 from above-mentioned driving process can be with first
The current potential of clock signal, the first power supply signal and third clock signal changes, and makes the first pull-down node N1 and second
The current potential of pull-down node N2 can change according to height pulse generation, so that the first pull-down node N1 and the second pull-down node
The current potential of N2 without being in high level for a long time, and compared to the relevant technologies, can reduce leads to the because long-time provides high level
There is positive excursion in the threshold voltage of one transistor M1, second transistor M2 and the tenth transistor M10, can guarantee transistor
Electrology characteristic.
It should be noted that the specific potential value of each power end VGL and the signal of signal end output can be according to reality
Circuit needs in border are adjusted, for example, the current potential of the first power supply signal can be 8 volts (V), the current potential of second source signal can be with
For -8V, it is not limited in the embodiment of the present invention.
In conclusion the driving method of shift register cell provided in an embodiment of the present invention, due to the first drop-down section
The current potential of point can change according to the current potential of the first clock signal, the first power supply signal and third clock signal, and by
It changes according to the fixed cycle in the current potential of first clock signal He the third clock signal, so that the first drop-down section
The current potential of point without being in effective current potential for a long time, compared to the relevant technologies, can reduce and provide because pulling down module for a long time
Effective current potential is influenced caused by the pull-down module electrology characteristic, ensure that pull-down module to the noise reduction effect of output end, guarantees
The display effect of display device.
The embodiment of the invention provides a kind of gate driving circuit, which may include multiple cascade shiftings
Bit register unit, and each shift register cell is shift register cell shown in Fig. 1 to Fig. 6 is any.
In a kind of achievable mode, when the output module of shift register cell is connect with output end and cascade signal end
When, in multiple cascade shift register cell, each output end can be connect with one-row pixels unit, and j-th of displacement
The cascade signal end CR of register cell is connect with the input signal end IN of+1 shift register cell of jth, and j is positive integer.
Illustratively, Fig. 9 is a kind of partial structural diagram of gate driving circuit provided in an embodiment of the present invention, the Fig. 9
Shown in include three cascade shifting deposit units in structure, in three cascade shift register cells, each displacement
Register cell can for Fig. 1 to Fig. 6 it is any shown in shift register cell, as shown in figure 9, can be in gate driving circuit
It is provided with an enabling signal end, three clock signal terminals, a reset signal end TRST, effective potential power source signal end VG1
With invalid potential power source end VG2, the first power end VGL of each shift register cell with the invalid potential power source end VG2
Connection, and the second source end VGH of each shift register cell with effective potential power source signal end VG1.Enabling signal end
Enabling signal STV is exported, three clock signal terminals export clock signal CK1, CK2 and CK3 respectively, and CK1, CK2 and the CK3's accounts for
Sky is than identical, and CK1, CK2 and CK3 are sequentially output the clock signal in effective current potential, in three cascade shift LD lists
In member, the input signal of the input signal end IN input of first order shift register cell GOA1 is enabling signal STV, the first order
First clock signal of the first clock signal terminal CLK1 input of shift register cell GOA1 is clock signal CK1, the first order
The second clock signal of the second clock signal end CLK2 input of shift register cell GOA1 is clock signal CK2, this first
The waveform of the signal of the output end OUT output of grade shift register cell GOA1 please refers to the waveform of the OUT1 in Fig. 8；The second level
The grade that the input signal of the input signal end IN input of shift register cell GOA2 is first order shift register cell GOA1
Join the signal of signal end CR1 output, waveform please refers to the waveform of the OUT1 in Fig. 8, second level shift register cell GOA2
The first clock signal terminal CLK1 input the first clock signal be clock signal CK2, second level shift register cell GOA2
Second clock signal end CLK2 input second clock signal be clock signal CK3, the second level shift register cell
The waveform of the signal of the output end OUT output of GOA2 please refers to the waveform of the OUT2 in Fig. 8；Third level shift register cell
The cascade signal end CR2 that the input signal of the input signal end IN input of GOA3 is second level shift register cell GOA2 is exported
Signal, waveform please refers to the waveform of the OUT2 in Fig. 8, the first clock signal terminal of third level shift register cell GOA3
First clock signal of CLK1 input is clock signal CK3, the second clock signal end of third level shift register cell GOA3
The second clock signal of CLK2 input is clock signal CK1, and the output end OUT of third level shift register cell GOA3 is exported
The waveform of signal please refer to the waveform of the OUT3 in Fig. 8.Gate driving circuit provided in an embodiment of the present invention can be with three
Shift register cell is unit, repeats the above connection.
In the achievable mode of another kind, when the output module of shift register cell is only connect with output end, this is more
In a cascade shift register cell, the output end OUT and+1 shift register list of jth of j-th of shift register cell
The input signal end IN connection of member, j is positive integer.
In conclusion gate driving circuit provided in an embodiment of the present invention includes multiple cascade shift register cells,
It include input module, output module, pull-down control module and pull-down module, the shift register in each shift register cell
The circuit structure of unit is relatively simple, and the input module in the shift register cell can be according to the current potential pair of input signal
First pull-up node is charged and is resetted, it is not necessary that the circuit resetted to the first pull-up node is additionally arranged, compared to phase
Pass technology reduces parts number and signal wire the space occupied in shift register cell, and then effectively reduces grid drive
Dynamic circuit occupied chip area in a display device, is conducive to the realization of narrow frame.
The embodiment of the present invention provides a kind of display device, which may include grid provided in an embodiment of the present invention
Driving circuit.The display device can be with are as follows: liquid crystal display panel, Electronic Paper, Organic Light Emitting Diode (English: Organic Light-
Emitting Diode, referred to as: OLED) panel, mobile phone, tablet computer, television set, display, laptop, digital phase
Any products or components having a display function such as frame, navigator.
The embodiment of the invention also provides a kind of storage medium, computer program, computer are stored in the storage medium
The driving method of shift register cell provided in an embodiment of the present invention is realized when program is executed by processor.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of shift register cell characterized by comprising input module, output module, pull-down control module and drop-down
Module；
The input module is connect with input signal end, the first clock signal terminal and the first pull-up node respectively, the input mould
Block is used under the control of the first clock signal from first clock signal terminal, and the first pull-up node of Xiang Suoshu, which provides, to be come
Input signal from the input signal end；
The output module is connect with second clock signal end, first pull-up node and output end respectively, the output mould
Block is used under the control of first pull-up node, and Xiang Suoshu output end provides second from the second clock signal end
Clock signal；
The pull-down control module respectively with first clock signal terminal, third clock signal terminal, the first power end and first
Pull-down node connection, the pull-down control module are used under the control of first clock signal, the drop-down section of Xiang Suoshu first
Point provides the first power supply signal from first power end, and, based on the third from the third clock signal terminal
Clock signal controls the current potential of first pull-down node；
The pull-down module respectively with first power end, first pull-down node, first pull-up node and described
Output end connection, the pull-down module are used for the Xiang Suoshu output end and described first under the control of first pull-down node
Pull-up node provides first power supply signal.
2. shift register cell according to claim 1, which is characterized in that the pull-down module includes: first crystal
Pipe and second transistor；
The grid of the first transistor is connect with first pull-down node, the first of the first transistor extremely with it is described
The connection of first power end, the second pole of the first transistor is connect with first pull-up node；
The grid of the second transistor is connect with first pull-down node, the first pole of the second transistor and described the
The connection of one power end, the second pole of the second transistor is connect with the output end.
3. shift register cell according to claim 1 or 2, which is characterized in that the pull-down control module also with institute
The connection of second clock signal end is stated, the pull-down control module is also used under the control of the second clock signal, Xiang Suoshu
First pull-down node provides the third clock signal.
4. shift register cell according to claim 3, which is characterized in that the pull-down control module includes: the tenth
Four transistors, third transistor, the 4th transistor, the 5th transistor and first capacitor device；
The grid of 14th transistor and first is extremely connect with the second clock signal end, the 14th transistor
The second pole connect with the second pull-down node；
The grid of the third transistor is connect with second pull-down node, the first pole of the third transistor and described the
The connection of three clock signal terminals, the second pole of the third transistor is connect with first pull-down node；
The grid of 4th transistor is connect with first clock signal terminal, the first pole of the 4th transistor with it is described
The connection of first power end, the second pole of the 4th transistor is connect with first pull-down node.
The grid of 5th transistor is connect with first clock signal terminal, the first pole of the 5th transistor with it is described
The connection of first power end, the second pole of the 5th transistor is connect with second pull-down node；
One end of the first capacitor device is connect with second pull-down node, the other end of the first capacitor device and described the
The connection of one pull-down node.
5. shift register cell according to claim 1 or 2, which is characterized in that the shift register cell also wraps
It includes: the feedback module being connected between the input module and first pull-up node, and the feedback module passes through second
Pull-up node is connect with the input module；
The feedback module is also connect with first pull-up node, first clock signal terminal and second source end respectively,
The feedback module is used under the control of first pull-up node, and the second pull-up node of Xiang Suoshu, which provides, comes from described second
The second source signal of power end, and, the input module is used under the control of first clock signal, by described
Feedback module provides the input signal to first pull-up node.
6. shift register cell according to claim 5, which is characterized in that the feedback module includes: the 6th crystal
Pipe and the 7th transistor；
The grid of 6th transistor is connect with first clock signal terminal, the first pole of the 6th transistor with it is described
The connection of second pull-up node, the second pole of the 6th transistor is connect with first pull-up node；
The grid of 7th transistor is connect with first pull-up node, the first pole of the 7th transistor and described the
The connection of two power ends, the second pole of the 7th transistor is connect with second pull-up node.
7. a kind of driving method of shift register cell, which is characterized in that the method is used to drive shift register cell,
The shift register cell includes: input module, output module, pull-down control module and pull-down module, which comprises
Charging stage, output stage and the first noise reduction stage；
In the charging stage, the current potential of the first clock signal of the first clock signal terminal output is effective current potential, input signal
The current potential for holding the input signal of output is effective current potential, and the input module is under the control of first clock signal, to the
One pull-up node provides the input signal for being in effective current potential；
In the output stage, second clock signal end output second clock signal current potential be effective current potential, described first
The current potential of pull-up node remains effective current potential, and the output module is under the control of first pull-up node, to output end
The second clock signal for being in effective current potential is provided；
In the first noise reduction stage, third clock signal terminal output third clock signal current potential be effective current potential, first
The current potential of the power supply signal of power end output is invalid current potential, and the pull-down control module, which provides to be in the first pull-down node, to be had
The third clock signal of current potential is imitated, the pull-down module is under the control of first pull-down node, Xiang Suoshu output end and institute
It states the first pull-up node and the first power supply signal for being in invalid current potential is provided.
8. the method according to the description of claim 7 is characterized in that the shift register cell further include: be connected on described
Feedback module between input module and first pull-up node, and the feedback module by the second pull-up node with it is described
Input module connection, the method also includes:
In the output stage, the current potential of first pull-up node remains effective current potential, and the second of the output of second source end
The current potential of power supply signal is effective current potential, and the current potential of first clock signal is effective current potential, and the feedback module is described
Under the control of first pull-up node, the second pull-up node of Xiang Suoshu provides the second source signal for being in effective current potential.
9. a kind of gate driving circuit, which is characterized in that the gate driving circuit includes: multiple cascade claims 1 to 6
Any shift register cell.
10. a kind of display device, which is characterized in that the display device includes: gate driving circuit as claimed in claim 9.
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| CN111312322A (en) * | 2020-03-12 | 2020-06-19 | 深圳市华星光电半导体显示技术有限公司 | Shifting register unit, grid driving circuit and display panel |
| CN111445833A (en) * | 2020-05-09 | 2020-07-24 | 合肥京东方卓印科技有限公司 | Shift register unit, control method thereof and grid drive circuit |
| CN113257205A (en) * | 2021-05-18 | 2021-08-13 | 武汉华星光电技术有限公司 | Grid driving circuit and display panel |
| CN113643641A (en) * | 2021-08-03 | 2021-11-12 | 武汉华星光电技术有限公司 | Grid driving circuit and display panel |
| CN114120870A (en) * | 2020-09-01 | 2022-03-01 | 深圳市柔宇科技股份有限公司 | GOA circuit |
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