CN110261758B

CN110261758B - Device under test verification device and related product

Info

Publication number: CN110261758B
Application number: CN201910499933.2A
Authority: CN
Inventors: 不公告发明人
Original assignee: Cambricon Technologies Corp Ltd
Current assignee: Cambricon Technologies Corp Ltd
Priority date: 2019-06-10
Filing date: 2019-06-10
Publication date: 2021-09-21
Anticipated expiration: 2039-06-10
Also published as: CN110261758A

Abstract

The application provides a device to be tested verification device and a related product, the device to be tested verification device is used for verifying machine state, a probe instruction is added into an instruction sequence through an address dependency tree in the embodiment of the application, the instruction sequence is verified again according to an execution result of the probe instruction until an instruction causing errors is obtained, therefore, the instruction sequence can be verified accurately and quickly, the position where the instruction causing the errors is located is determined, and the verification speed of the device to be tested is improved.

Description

Device under test verification device and related product

Technical Field

The application relates to the technical field of chip verification, in particular to a device to be tested verification device and a related product.

Background

As silicon material semiconductor processes approach physical limits, it becomes increasingly difficult to integrate more transistors per unit area of silicon material chip. The integrated functions of integrated circuits in electronic devices are increasing, and the number of instructions to be executed by a processor is also increasing, which makes the verification of instruction sets in an actuator more and more complex, and provides a new challenge for verification technology, so that when the device to be tested is verified, how to accurately and efficiently verify the device to be tested becomes a problem to be considered.

Disclosure of Invention

The embodiment of the application provides a to-be-detected device verification device and a related product, which can quickly and accurately locate the position of an instruction causing error aiming at a to-be-detected device with a large number of integrated instructions, and improve the verification efficiency of the to-be-detected device.

In a first aspect, there is provided a device under test verification apparatus comprising an actuator and a controller, wherein,

the executor is used for running an instruction sequence;

the controller is used for adding a probe instruction behind at least one node instruction of the address dependency tree to obtain a new instruction sequence when determining that an instruction causing an error exists in the instruction sequence according to an execution result of the instruction sequence;

the executor is further used for verifying the new instruction sequence;

the controller is further configured to determine a target PC value according to an execution result of the probe instruction until the target PC value meets a preset condition, and use a node instruction corresponding to the target PC value meeting the preset condition as an instruction causing an error in the instruction sequence.

In a second aspect, an embodiment of the present application provides a device under test verification method, which is applied to a device under test verification apparatus, where the device under test verification apparatus includes an actuator and a controller, and the method includes:

the actuator runs a command sequence;

when the controller determines that an instruction causing an error exists in the instruction sequence according to an execution result of the instruction sequence, adding a probe instruction behind at least one node instruction of an address dependency tree to obtain a new instruction sequence;

the executor verifies the new instruction sequence;

and the controller determines a target PC value according to the execution result of the probe instruction until the target PC value meets a preset condition, and takes the node instruction corresponding to the target PC value meeting the preset condition as an instruction causing an error in the instruction sequence.

Optionally, adding a probe instruction after the instruction of at least one node of the address dependency tree to obtain a new instruction sequence includes:

and the controller adds a probe instruction behind the node instruction corresponding to each PC value of each node in the address dependency tree to obtain the new instruction sequence.

the controller acquires mark information of nodes in the address dependency tree, wherein the mark information is used for determining whether a node instruction corresponding to each PC value in the nodes needs to be inserted into a probe instruction;

and adding a probe instruction behind the node instruction corresponding to each PC value of the node marked as the node needing to be added with the probe instruction according to the marking information of the node in the address dependency tree to obtain the new instruction sequence.

Optionally, the obtaining the tag information of the node in the address dependency tree includes:

if the execution result of the probe instruction behind the node instruction corresponding to at least one PC value in the currently accessed node is wrong, the controller marks the child node of the currently accessed node as the probe instruction needing to be added;

if the execution results of the probe instruction behind the node instruction corresponding to at least one PC value in the currently accessed node are correct, the controller marks the child node of the currently accessed node as a probe instruction which is not required to be added, and obtains the marking information of the node in the address dependency tree.

and if the currently accessed node is the root node, the controller marks the root node as a probe instruction needing to be added.

Optionally, the method further comprises:

and after the actuator completes the verification of the probe instruction behind the node instruction corresponding to at least one PC value in the currently accessed node, the controller eliminates the probe instruction in the currently accessed node.

Optionally, the determining a target PC value according to an execution result of the probe instruction until the target PC value meets a preset condition, and taking a node instruction corresponding to the target PC value meeting the preset condition as an instruction causing an error in the instruction sequence includes:

if the execution result of the probe instruction is wrong and the PC value corresponding to the node instruction before the probe instruction is smaller than the target PC value, updating the target PC value to the PC value corresponding to the node instruction before the probe instruction until the target PC value meets a preset condition; when the target PC value meets a preset condition, taking a node instruction corresponding to the target PC value as the instruction causing the error;

and when the target PC value is the minimum PC value in the PC values of the node instructions in front of the probe instruction with the wrong execution result, the controller determines that the target PC value meets a preset condition.

Optionally, the verifying the new instruction sequence includes:

the executor adds a synchronization instruction between the currently verified probe instruction and a node instruction corresponding to the currently verified probe instruction;

determining a target synchronization instruction which is closest to a node instruction corresponding to the currently verified probe instruction in the new instruction sequence, wherein the target synchronization instruction is positioned before the node instruction corresponding to the currently verified probe instruction;

executing the new instruction sequence from the target synchronization instruction to the currently validated probe instruction.

Optionally, the apparatus further comprises a storage unit, the storage unit comprising a RAM and a register, the method further comprising:

after the executor runs the instruction sequence and when the execution result of the instruction sequence is wrong, the controller constructs an address dependency tree according to the execution result of the instruction sequence; wherein, the root node of the address dependency tree comprises a RAM address area or a register number where an output result of an instruction outputting an error result in the initial instruction sequence is located; and the next-layer node of the address dependency tree comprises a RAM address interval or a register number where an operand of a node instruction corresponding to at least one PC value accessed by the previous-layer node is located.

In a third aspect, the present application provides a computer-readable storage medium storing a computer program for electronic data exchange, wherein the computer program causes a computer to execute the method steps according to the second aspect.

In a fourth aspect, embodiments of the present application provide a computer program product comprising a non-transitory computer readable storage medium storing a computer program operable to cause a computer to perform the method steps of the second aspect.

In a fifth aspect, an embodiment of the present application provides a chip, where the chip includes the device under test verification apparatus according to the first aspect.

In a sixth aspect, an embodiment of the present application provides a chip packaging structure, where the chip packaging structure includes the chip described in the fifth aspect.

It can be seen that, in the verification apparatus for a device under test according to the embodiment of the present application, the executor runs the instruction sequence, when the controller determines that there is an instruction causing an error in the instruction sequence according to an execution result of the instruction sequence, the probe instruction is added behind at least one node instruction of the address dependency tree to obtain a new instruction sequence, the executor verifies the new instruction sequence, the controller determines the target PC value according to the execution result of the probe instruction until the target PC value meets a preset condition, and the node instruction corresponding to the target PC value meeting the preset condition is used as the instruction causing the error in the instruction sequence. According to the embodiment of the application, the probe instruction is added into the instruction sequence through the address dependency tree, and the instruction sequence is verified again according to the execution result of the probe instruction until the instruction causing the error is obtained, so that the instruction sequence can be accurately and quickly verified, the position where the instruction causing the error is located is determined, and the verification speed of the device to be tested is improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a device under test verification apparatus according to an embodiment of the present disclosure;

fig. 2A is a schematic flowchart of a verification method for a device under test according to an embodiment of the present disclosure;

FIG. 2B is a schematic diagram illustrating a sequence of instructions provided by an embodiment of the present application;

FIG. 2C is a schematic diagram illustrating an address dependency tree according to an embodiment of the present disclosure;

fig. 3 is a structural diagram of a group board card provided in an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first," "second," "third," and "fourth," etc. in the description and claims of this application and in the accompanying drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

At present, in order to deal with a relatively complex verification scene of a Device Under Test (DUT) with a complex integrated function and a large number of instruction sets, the applicant focuses on improving observability and controllability of the device under test.

The observability of the device to be tested refers to the observation capability of a verifier on the interior of the device to be tested. The verifier can observe the machine state of the device to be tested in the simulation process through the simulation waveform and the environment printing. For the RAM with larger storage space, the form of file saving is easier to analyze. The controllability of the device to be tested refers to the control capability of a verification person on the machine state of the device to be tested. For example, the verifier may perform a forced assignment operation on a signal in the device under test using a force statement in systemveilog, or change an operating state of the device under test by changing an interface signal of the device under test, or assign a value to a memory inside the device under test by a back-gate access method, or the like. For a complex heterogeneous multi-core system, the observability and the controllability of a device to be tested are improved, and the problem analysis by verification personnel is facilitated.

However, in the verification process, the output of each stimulus may not be compared due to the design of the device under test and the environment building method. For example, the results of some instructions may be out of order when written to RAM, making it difficult for a verifier to determine to which instruction the output belongs when grabbing the output signal. As another example, different kinds of instructions may share the same functional unit, and it is difficult to determine to which instruction its output belongs due to complex timing relationships among functional units. As another example, comparing the output of each instruction may result in a verification environment that is too complex to maintain. These reasons may lead to incomplete alignment during verification, that is, when a segment of input excitation is input into the device under test and the output result thereof is not consistent with the reference model, it is likely not caused by the excitation input last in the excitation sequence, but may be caused by the excitation in the middle of the excitation sequence. Locating the stimulus that causes the device under test to operate incorrectly in the middle of the stimulus sequence is likely to be a very time consuming process. For example, data competition occurs between two input/output IO instructions in a lengthy instruction sequence, which results in inconsistent comparison results between simulation results of the device under test and the reference model. Since the locations where data contention occurs may be repeatedly read and written, so that the last location where error occurs may be far from the location where data contention occurs, finding the cause of error is a very time consuming matter.

In order to solve the above problem, the instructions in the instruction set of the device under test can be divided into two types: the instructions of the results can be detected in real time and the instructions of the results cannot be detected in real time. The instruction capable of detecting the result in real time refers to an instruction that the verification environment can capture certain signals from the device to be tested to obtain an operation result and compare the operation result after the instruction is executed in the simulation process of the device to be tested, that is, the environment can know the error of instruction execution in real time. The instruction which cannot detect the result in real time is an instruction which cannot capture signals in the simulation process of the device to be detected by the environment so as to compare the result. For instructions that cannot compare results in real time, if an error occurs in their execution during the simulation, the detection of the error by the environment may be delayed, as found by comparing data persisted in RAM after the instruction has been executed. Therefore, for a mixed sequence of instructions capable of detecting results in real time and instructions incapable of detecting results in real time, if the final machine state such as data reserved in a RAM or a register is found to be incorrect after the instruction sequence is executed, and no error is found in the instruction sequence execution process, it is necessary to trace back which instruction in the instruction sequence causes an execution error. Even if an instruction which can detect the result in real time is found to be in error in operation, the error may be caused by an instruction which cannot detect the result in real time and is in error in operation because there is a link (such as data correlation, etc.) between the instruction which can detect the result in real time and the instruction which cannot detect the result in real time. Therefore, in order to quickly locate the instruction causing the simulation result error of the device to be tested, the scheme for verifying the device to be tested by adding the probe instruction to the instruction set with complex integrated functions and large number is provided.

The device under test verification apparatus used in the present application is described below. Referring to fig. 1, a device under test verification apparatus is provided, which includes a processor 101 and a memory unit 102, wherein the processor 101 includes an executor 10 and a controller 11, and the memory unit 102 includes a register 21 and a random access memory RAM 22. Wherein the content of the first and second substances,

the actuator 10 is used for operating a command sequence;

the controller 11 is configured to add a probe instruction after at least one node instruction of the address dependency tree to obtain a new instruction sequence when it is determined that an instruction causing an error exists in the instruction sequence according to an execution result of the instruction sequence;

the executor 10 is further configured to verify the new instruction sequence;

the controller 11 is further configured to determine a target PC value according to an execution result of the probe instruction until the target PC value meets a preset condition, and use a node instruction corresponding to the target PC value meeting the preset condition as an instruction causing an error in the instruction sequence.

Alternatively, when the target PC value is a minimum PC value among PC values of node instructions preceding the probe instruction whose execution result is erroneous among the added probe instructions, the controller may consider that the target PC value satisfies a preset condition. At this time, the node instruction corresponding to the minimum PC value is an instruction causing an error in the instruction sequence.

The register and the RAM are used for storing an instruction sequence to be verified, the instruction sequence comprises n instructions, and n is an integer greater than 1.

In a possible embodiment, in terms of adding a probe instruction after the at least one node instruction of the address dependency tree to obtain a new instruction sequence, the controller is specifically configured to:

and adding a probe instruction behind the node instruction corresponding to each PC value of each node in the address dependency tree to obtain the new instruction sequence.

acquiring marking information of nodes in the address dependency tree, wherein the marking information is used for determining whether a node instruction corresponding to each PC value in the nodes needs to be inserted into a probe instruction;

In one possible embodiment, in the aspect of obtaining the tag information of the node in the address dependency tree, the controller is specifically configured to:

if the execution result of the probe instruction behind the node instruction corresponding to at least one PC value in the currently accessed node is wrong, marking the child node of the currently accessed node as the probe instruction needing to be added;

if the execution results of the probe instruction behind the node instruction corresponding to at least one PC value in the currently accessed node are all correct, marking the child nodes of the currently accessed node as the probe instruction which is not required to be added, and obtaining the marking information of the nodes in the address dependency tree.

Specifically, if the execution result of the probe instruction behind the node instruction corresponding to at least one PC value in the currently accessed node is wrong, the child node of the currently accessed node is marked as the probe instruction that needs to be added. If the execution results of the probe instructions behind the node instructions corresponding to all the PC values in the currently accessed node are correct, marking the child nodes of the currently accessed node as the probe instructions which are not required to be added, and obtaining the marking information of the nodes in the address dependency tree.

and if the currently accessed node is the root node, marking the root node as a probe instruction needing to be added.

In a possible embodiment, the controller is further configured to eliminate the probe instruction in the currently visited node after the executor completes verification of the probe instruction subsequent to the node instruction corresponding to the at least one PC value in the currently visited node.

In a possible embodiment, in the aspect that the target PC value is determined according to the execution result of the probe instruction until the target PC value meets a preset condition, and a node instruction corresponding to the target PC value meeting the preset condition is used as an instruction causing an error in the instruction sequence, the controller is specifically configured to:

In a possible embodiment, in said verifying the new command sequence, the executor is specifically configured to:

adding a synchronization instruction between the currently verified probe instruction and the node instruction corresponding to the currently verified probe instruction;

In one possible embodiment, the controller is further configured to:

after the executor runs the instruction sequence and when the execution result of the instruction sequence is wrong, constructing an address dependency tree according to the execution result of the instruction sequence; wherein, the root node of the address dependency tree comprises a RAM address area or a register number where an output result of an instruction outputting an error result in the initial instruction sequence is located; and the next-layer node of the address dependency tree comprises a RAM address interval or a register number where an operand of a node instruction corresponding to at least one PC value accessed by the previous-layer node is located.

As shown in fig. 2A, fig. 2A is a schematic flowchart of a method for verifying a device under test provided in an embodiment of the present application, and is applied to a device under test verification apparatus, where the device under test verification apparatus includes an actuator and a controller. The method comprises the following steps:

201. the actuator runs the sequence of instructions.

In the embodiment of the application, the executor may run the instruction sequence to obtain an execution result of the instruction sequence.

202. And when the controller determines that an instruction causing an error exists in the instruction sequence according to the execution result of the instruction sequence, adding a probe instruction behind at least one node instruction of the address dependence tree to obtain a new instruction sequence.

In the embodiment of the application, the controller may determine that there is an instruction causing an error in the instruction sequence when the execution result of the instruction sequence is incorrect. Referring to fig. 2B, fig. 2B is a schematic diagram illustrating an instruction sequence according to an embodiment of the present disclosure, as shown in fig. 2B, the instruction sequence includes an instruction capable of comparing results in real time and an instruction incapable of comparing results in real time, where the instruction capable of comparing results in real time can know whether an execution result of the instruction is correct in real time during an execution process of the instruction sequence. The instructions of the results cannot be compared in real time, and errors cannot be reported even if errors occur in the execution process of the instruction sequence. Therefore, if the instruction outputting the wrong result in the instruction sequence is an instruction that cannot compare the results in real time, the position of the instruction causing the error in the execution process of the instruction sequence needs to be found. In the embodiment of the application, a probe instruction can be added behind at least one node instruction of the address dependency tree to obtain a new instruction sequence after the probe instruction is added, and further, an instruction causing an error can be relocated according to an execution result of the new instruction sequence.

Optionally, after the executor runs the instruction sequence and when the execution result of the instruction sequence is incorrect, the controller may construct an address dependency tree according to the execution result of the instruction sequence; wherein, the root node of the address dependency tree comprises a RAM address area or a register number where an output result of an instruction outputting an error result in the initial instruction sequence is located; and the next-layer node of the address dependency tree comprises a RAM address interval or a register number where an operand of a node instruction corresponding to at least one PC value accessed by the previous-layer node is located.

The controller can construct an address dependency tree according to the instruction which outputs the error result in the instruction sequence, and the node instruction corresponding to each PC value in the address dependency tree can be an instruction which cannot compare the result in real time. Specifically, a root node in the address dependency tree includes a RAM address interval or a register number where an output result of an instruction outputting an erroneous result in the instruction sequence is located, and a child node in the address dependency tree includes a RAM address interval or a register number where an operand corresponding to the output result of the root node is located. That is, according to the relationship from top to bottom of the address dependency tree, the next level node of the address dependency tree is the RAM address interval or register number where the operand of the instruction accessing the address information of the previous level node is located.

The address dependency tree includes a plurality of nodes, each node further includes a PC value of a node instruction accessing a corresponding address interval, and the PC value is a flag amount of any instruction that can uniquely mark any core, indicating which instruction the currently executed instruction is. The node instruction corresponding to each PC value in each node in the address dependency tree is an instruction which can not compare results in real time.

The probe instruction is a simple instruction capable of comparing results in real time, and an operand of the probe instruction is from an instruction incapable of comparing results in real time (in the embodiment of the present application, the operand of the probe instruction is from a previous node instruction), so that if the instruction incapable of comparing results in real time is in error, the probe instruction is also in error. In the embodiment of the application, at least one node instruction corresponding to each PC value in the address dependency tree is an instruction that cannot compare results in real time, so that the probe instruction is added behind the node instruction that cannot compare results in real time, and whether the execution result of the node instruction before the probe instruction is correct can be determined according to the execution result of the probe instruction, and thus which node instruction causes an execution result error of an instruction sequence can be found relatively quickly.

Referring to fig. 2C, fig. 2C is a schematic diagram illustrating an address dependency tree according to the present application, where the address dependency tree includes 6 nodes, an address interval of each node stores at least one PC value, and each PC value corresponds to a node instruction. The 1 st node, i.e. the root node, contains the PC value a and the PC value b, and the PC values a and b in the 1 st node may be PC values corresponding to the instructions in the instruction sequence that output erroneous results. The 2 nd node and the 3 rd node are child nodes of the 1 st node, the 2 nd node contains a PC value c, and the execution result of the node instruction pointed by the PC value c can be the operand of the node instruction corresponding to the PC value a and/or b in the 1 st node. The 3 rd node contains a PC value d and a PC value e, and similarly, the execution result of the node instruction pointed to by the PC values d and e may be the operand of the node instruction corresponding to the PC values a and/or b in the 1 st node. The 4 th node and the 5 th node are child nodes of the 2 nd node, the 4 th node contains a PC value f and a PC value g, and the execution results of the node instructions pointed by the PC values f and g can be operands of the instructions corresponding to the PC value c in the 2 nd node. The 5 th node contains a PC value h, which points to the result of the execution of the node instruction that may be the operand of the node instruction corresponding to the PC value c in the 2 nd node. The 6 th node is a child node of the 3 rd node, and the 6 th node contains a PC value i, and the execution result of the node instruction pointed by the PC value i can be the operand of the node instruction corresponding to the PC value d and/or e in the 3 rd node.

Optionally, in step 202, adding a probe instruction after at least one node instruction of the address dependency tree to obtain a new instruction sequence, may include the following steps:

21. and the controller adds a probe instruction behind the node instruction corresponding to each PC value of each node in the address dependency tree to obtain the new instruction sequence.

In the embodiment of the application, the controller may add a probe instruction after a node instruction corresponding to each PC value of each node in the address dependency tree to obtain a new instruction sequence, and thus, the executor may verify whether the node instruction corresponding to each PC value of each node in the address dependency tree is an instruction causing an error in the instruction sequence by executing the new instruction sequence. For example, the address dependency tree shown in fig. 2C includes 6 nodes, where 9 PC values from PC value a to PC value i correspond to 9 node instructions, and a probe instruction may be added after each node instruction in the 9 node instructions to obtain a new instruction sequence. Therefore, the probe instruction is an instruction capable of comparing results in real time, so that each node instruction which cannot compare results in real time in the address dependency tree can be converted into an instruction capable of comparing results in real time by adding the probe instruction behind the node instruction corresponding to each PC value in the address dependency tree, and therefore wrong instructions in an instruction sequence can be found quickly.

22. the controller acquires mark information of nodes in the address dependency tree, wherein the mark information is used for determining whether a node instruction corresponding to each PC value in the nodes needs to be inserted into a probe instruction;

23. and the controller adds the probe instruction after the node instruction corresponding to each PC value of the node marked as the node needing to be added with the probe instruction according to the marking information of the node in the address dependency tree to obtain the new instruction sequence.

In the embodiment of the application, the controller can obtain the marking information of the nodes in the address dependency tree, wherein the marking information of some nodes is 'probe instruction needing to be added', and the marking information of some nodes is 'probe instruction not needing to be added', so that the probe instruction can be added behind the node instruction corresponding to each PC value of the node marked as the node needing to be added, and a new instruction sequence is obtained. Therefore, after the executor executes the node instruction, the probe instruction behind the executor can be executed immediately, and whether the previous node instruction is an error instruction can be determined according to the execution result of the probe instruction as the probe instruction is an instruction capable of comparing results in real time.

Optionally, if the tag information of each node in the address dependency tree is "probe instruction to be added", the tag information of each node may be obtained, and a probe instruction is added after an instruction corresponding to each PC value of all nodes tagged as the node to be added with the probe instruction, that is, a probe instruction is added after a node instruction corresponding to each PC value of each node in all nodes, so as to obtain a new instruction sequence.

Optionally, if the tag information of only a part of nodes in the address dependency tree is "probe instruction needs to be added", the tag information of each node may be obtained, and a probe instruction is added after a node instruction corresponding to each PC value of all nodes tagged as the nodes that need to be added with the probe instruction. The node marked with the information "needing to add the probe instruction" may be all nodes in a certain layer of the address dependency tree, or the node marked with the information "needing to add the probe instruction" may also be all nodes in a certain layer of the address dependency tree. For example, if the tag information of the root node of the first layer in the address dependency tree is "probe instruction needs to be added", a probe instruction may be added after the instruction corresponding to each PC value of the root node. The address dependency tree shown in fig. 2C is followed by probe instructions for both node instruction a for PC value a and node instruction B for PC value B. For another example, if each node at level 2 in the address dependency tree is marked as "probe instruction insertion required," a probe instruction may be added after the node instruction corresponding to each PC value at each node at level 2. That is, the probe command is added after the node commands C, D and E corresponding to the PC values c, d and E, to obtain a new command sequence.

Specifically, if the number of node instructions corresponding to the PC values of all nodes in the address dependency tree is large, probe instructions can be added for multiple times, and each time, a probe instruction is added behind a node instruction corresponding to a PC value of a node at a certain level in the address dependency tree. For example, if the label information of the root node in the first layer in the address dependency tree is "probe instruction needs to be added", a probe instruction may be added after an instruction corresponding to each PC value of the root node, as shown in fig. 2C, that is, a probe instruction is added after both a node instruction a corresponding to the PC value a and a node instruction B corresponding to the PC value B, so as to obtain and run a new instruction sequence. And then, according to the operation result of the new instruction sequence, determining whether a probe instruction needs to be inserted into a child node (a second layer node) of the first layer node. Thus, the determination is made layer by layer.

In the embodiment of the application, the node instructions corresponding to the layer-by-layer nodes in the address dependency tree are sequentially added into the nodes of the probe instruction to insert the probe instruction, and compared with a scheme that the probe instruction is inserted once aiming at the node instructions corresponding to all the nodes in the address dependency tree, the method is favorable for restoring the operation process of the initial instruction sequence, thereby reproducing errors, simplifying the verification process and improving the verification efficiency.

Optionally, in the step 22, obtaining the label information of the node in the address dependency tree may include the following steps:

a1, if the execution result of the probe instruction behind the node instruction corresponding to at least one PC value in the currently accessed node is wrong, the controller marks the child node of the currently accessed node as the probe instruction needing to be added;

a2, if the execution result of the probe instruction behind the node instruction corresponding to at least one PC value in the currently accessed node is correct, the controller marks the child node of the currently accessed node as a probe instruction which does not need to be added, and obtains the marking information of the node in the address dependency tree.

Specifically, if the execution results of the probe instructions subsequent to the node instructions corresponding to all the PC values in the currently accessed node are correct, the controller marks the child nodes of the currently accessed node as not needing to add the probe instructions.

The node currently accessed may be any node in the address dependency tree.

If the address space of the currently accessed node includes one PC value, the controller may mark a child node of the currently accessed node as "needing to add a probe instruction" if the execution result of the probe instruction corresponding to the node instruction of the one PC value is wrong. If the address space of the currently accessed node includes a plurality of PC values, the controller may mark a child node of the current node as "needing to add a probe instruction" if an execution result of the probe instruction corresponding to the node instruction having at least one PC value among the plurality of PC values is incorrect. Specifically, if the execution results of all probe instructions corresponding to all node instructions of all PC values in the currently accessed node are correct, the controller may mark the child node of the current node as "no probe instruction needs to be added". Therefore, each node of each layer in the address dependency tree can be marked to obtain the marking information of each node. In the embodiment of the application, when the execution results of all probe instructions corresponding to all node instructions of all PC values in the currently accessed node are correct, the child nodes of the current node are marked as 'no probe instruction adding required', and then the probe instructions can not be added to the node instructions corresponding to the child nodes of the current node in the execution process, so that unnecessary probe instruction adding operation in an instruction sequence can be reduced, unnecessary probe instructions in a new instruction sequence are reduced, the execution rate of the probe instructions is improved, and the verification efficiency of a device to be verified is improved.

a3, if the node accessed at present is the root node, the controller marks the root node as needing to add the probe instruction.

In a specific implementation, the root node may be a node that needs to join a probe instruction by default. The node where the instruction outputting the incorrect result in the root node instruction sequence is located may be the first node in the address dependency tree. Further, all children of the root node may be marked as "joining probe instructions needed". Each node of the second layer in the address dependency tree can be marked as 'needing to add a probe instruction', and a probe instruction is added behind each node instruction corresponding to the PC value of the node needing to add the probe instruction, so that a new instruction sequence is obtained. If the execution result of the probe instruction of at least one node instruction with a PC value in the currently accessed node in the second layer is wrong, the controller marks the child node of the currently accessed node as a probe instruction needing to be added, namely marks the node in the third layer as a probe instruction needing to be added. If the execution results of all probe instructions corresponding to all node instructions of all PC values in the currently accessed node in the second layer are correct, the controller marks the child node of the currently accessed node in the second layer as "no probe instruction needs to be added", that is, marks the node in the third layer as "no probe instruction needs to be added". Therefore, each node of the third layer can be further marked to obtain the marking information. In this way, for each node of each layer in the address dependency tree, whether the marking information of the child node of the next layer is "probe instruction needs to be added" or "probe instruction does not need to be added" can be determined according to at least one execution result of at least one probe instruction corresponding to at least one node instruction of each node.

For example, as shown in FIG. 2C, the first level includes a root node, i.e., node 1. The second tier includes 2 nodes: node 2 and node 3. If the probe instruction execution result behind the node instruction corresponding to the PC value c in the 2 nd node is wrong, the controller marks the child nodes of the 2 nd node as the probe instruction needing to be added, namely marks the 4 th node and the 5 th node as the probe instruction needing to be added. Further, the controller may add probe commands after the node commands to which the PC values f, g, and h of the 4 th node and the 5 th node point, respectively. If the execution result of the probe instruction behind the node instruction corresponding to the PC value c is correct, the controller marks the child node of the 2 nd node as the probe instruction which is not required to be added, namely marks the 4 th node and the 5 th node as the probe instruction which is not required to be added, and at the moment, the probe instruction does not need to be added behind the node instructions pointed by the PC values f, g and h of the 4 th node and the 5 th node respectively. If the probe instruction execution result after the node instruction corresponding to the PC value d in the 3 rd node is wrong and/or the probe instruction execution result after the node instruction corresponding to the PC value e is wrong, the controller marks the child node of the 3 rd node as the probe instruction which needs to be added, namely marks the 6 th node as the probe instruction which needs to be added. Further, the controller may insert a probe command behind the PC value i point to the ground node command. If the probe instruction execution result after the node instruction corresponding to the PC value d and the probe instruction execution result after the node instruction corresponding to the PC value e are both correct, the controller marks the child node of the 3 rd node as a probe instruction that does not need to be added, that is, marks the 6 th node as a probe instruction that does not need to be added, and at this time, it is not necessary to insert a probe instruction after the node instruction pointed to by the PC value i.

203. The executor verifies the new instruction sequence.

In the embodiment of the present application, the executor may verify the new instruction sequence, and specifically, the executor may execute the new instruction sequence, so that a position of an instruction causing an error may be located according to an execution result of executing the new instruction sequence.

The executor can verify the new instruction sequence added with at least one probe instruction to obtain the execution result of each probe instruction in at least one probe instruction in the new instruction sequence, and locate the instruction causing the error according to the execution result of the probe instruction and the address dependency tree. Specifically, if the execution result of at least one probe instruction corresponding to the node instruction corresponding to at least one PC value in the currently accessed node is wrong, the controller marks the child node of the currently accessed node as a probe instruction that needs to be added, and then, the probe instruction can be inserted into the instruction sequence again according to the marking information of the child node of the currently accessed node, so as to obtain a new instruction sequence again, and the executor is repeatedly called to verify the new instruction sequence.

The executor determines whether the probe instruction is executed wrongly, can obtain the operation result of the probe instruction, compares the operation result of the probe instruction with a preset correct operation result, determines that the probe instruction is executed correctly if the operation result is consistent with the correct operation result, and determines that the probe instruction is executed wrongly if the operation result is inconsistent with the correct operation result. Alternatively, the correct result may be a result obtained by a simulator (reference model) executing the new instruction sequence, and the result obtained by the simulator is the correct result by default in the embodiment of the present application.

For example, the controller may mark the root node of the address dependency tree and each node of the second layer (i.e., all child nodes of the root node) as nodes that need to be added with the probe instruction, so that the controller may obtain mark information of the nodes in the address dependency tree, and add the probe instruction after the node instruction corresponding to each PC value in the root node and each node of the second layer (i.e., all child nodes of the root node) according to the mark information, to obtain a new instruction sequence. And then the executor executes a new instruction sequence, and if the execution result of at least one probe instruction in at least one node instruction corresponding to at least one PC value in one node in the nodes of the second layer is wrong, the controller marks the child node of the node as 'needing to add the probe instruction'. If the execution results of all probe instructions corresponding to all node instructions of all PC values in another node in the nodes of the second layer are correct, the controller marks the child nodes of the node as 'no probe instruction adding required'. Therefore, the controller can determine the marking information corresponding to the node of the third layer according to the execution result of the probe instruction in the node of the second layer, namely which nodes in the third layer are marked as needing to be added with the probe instruction, and which nodes do not need to be added with the probe instruction. And then, the controller can acquire the marking information of the nodes in the address dependency tree again, add the probe instruction behind the node instruction corresponding to each PC value in the nodes marked as the nodes needing to be added with the probe instruction in the nodes on the third layer according to the marking information to obtain a new instruction sequence, and call the actuator to re-verify the new instruction sequence.

For example, as shown in the address dependency tree in fig. 2C, the controller may mark the root node of the address dependency tree and each node of the second layer as the probe instruction that needs to be added, so that the controller may obtain the mark information of each node in the address dependency tree, and add the probe instruction after the node instruction corresponding to each PC value in the root node and each node 2 and 3 of the second layer according to the mark information, that is, insert the probe instruction after the node instruction corresponding to each of the PC value C, the PC value d, and the PC value e, to obtain a new instruction sequence. And then, calling an actuator to execute a new instruction sequence to obtain a first execution result of the probe instruction corresponding to the node instruction C with the PC value C, a second execution result of the probe instruction corresponding to the node instruction D with the PC value D, and a third execution result of the probe instruction corresponding to the node instruction E with the PC value E. If the first execution result is wrong, it may be determined that the execution result of the at least one probe instruction corresponding to the at least one node instruction of the at least one PC value in the 2 nd node is wrong, the child nodes of the 2 nd node may be marked as probe instructions that need to be added, that is, the 4 th node and the 5 th node are marked as "probe instructions that need to be added", and the probe instructions are added after the instructions corresponding to each PC value in the 4 th node and the 5 th node. If the second execution result and the third execution result are both correct, it can be determined that the execution results of all probe instructions corresponding to all node instructions of all PC values in the 3 rd node are correct, and therefore, the child node of the 3 rd node is marked as not needing to add a probe instruction. Therefore, the marking information can be obtained again, the probe instruction is added behind the instruction corresponding to each PC value of the 4 th node and the 5 th node in the nodes of the third layer according to the marking information to obtain a new instruction sequence, and the executor is called to verify the new instruction sequence.

Therefore, when the execution results of all probe instructions corresponding to all node instructions of all PC values in the currently accessed node are correct, the child node of the current node is marked as 'no probe instruction adding required', and the effect of adding no probe instruction to the node instruction corresponding to the child node of the current node is further realized, so that unnecessary probe instruction adding operation in an instruction sequence can be reduced, unnecessary probe instructions in a new instruction sequence are reduced, the execution rate of the probe instruction is improved, and the verification efficiency of a device to be verified is improved.

Optionally, in step 203, the verifying the new command sequence by the executor may include:

the executor executes from a first instruction of the new instruction sequence to a termination instruction of the new instruction sequence.

In this embodiment, each time the new instruction sequence is executed, the execution from the first instruction of the new instruction sequence to the termination instruction of the new instruction sequence may be performed, specifically, the execution from the first instruction of the new instruction sequence to the termination instruction of the new instruction sequence may be performed according to the initial state before the execution of the initial instruction sequence until the execution of the termination instruction of the new instruction sequence.

31. the executor adds a synchronization instruction between the currently verified probe instruction and a node instruction corresponding to the currently verified probe instruction;

optionally, the currently validated probe instructions may be one or more of the added probe instructions. Further, the currently verified probe command may be all probe commands, and the executor may add a synchronization command between each probe command and the node command corresponding to the probe command.

32. Determining a target synchronization instruction which is closest to a node instruction corresponding to the currently verified probe instruction in the new instruction sequence, wherein the target synchronization instruction is positioned before the node instruction corresponding to the currently verified probe instruction;

33. executing the new instruction sequence from the target synchronization instruction to the currently validated probe instruction.

In the embodiment of the application, if a new instruction sequence is obtained each time, and the new instruction sequence is executed from the first instruction of the instruction sequence, there may be a case where many instructions in the instruction sequence are repeatedly executed for many times, so that a synchronization instruction may be added between a currently verified probe instruction and a node instruction corresponding to the currently verified probe instruction, and the synchronization instruction may ensure that all previous instructions have been completely executed, so that, when the new instruction sequence is executed, a target synchronization instruction closest to the node instruction corresponding to the currently verified probe instruction in the new instruction sequence may be determined, the target synchronization instruction is placed before the node instruction corresponding to the currently verified probe instruction, and then the new instruction sequence is executed from the target synchronization instruction to the termination instruction of the new instruction sequence, therefore, the instruction from the first instruction to the target synchronization point does not need to be repeatedly executed, and the instruction sequence to the node instruction is directly executed from the target synchronization point, so that the execution rate of the instruction sequence can be increased, and the verification rate can be improved.

The executor executes the new instruction sequence to the termination instruction of the new instruction sequence from the target synchronization instruction, and specifically, the executor may take a machine state snapshot corresponding to the target synchronization instruction as an initial state and execute the new instruction sequence to the termination instruction of the new instruction sequence according to the initial state. The termination instruction in the new instruction sequence may be an inserted probe instruction.

Optionally, in this embodiment of the present application, the method may further include the following steps:

In the embodiment of the application, the probe instruction in the current node can be eliminated through the verification of the probe instruction behind the node instruction corresponding to at least one PC value in the currently accessed node. In specific implementation, if the current node includes a root node, at least one probe instruction is added according to the marking information of the root node to obtain a new instruction sequence, and after the new instruction sequence is executed, probe instructions added behind the node instruction corresponding to each PC value of the root node can be eliminated. And adding a probe instruction behind the instruction corresponding to each PC value of all the nodes of the second layer according to the marking information of the child nodes of the root node, namely the child nodes of the second layer, so as to obtain a new instruction sequence.

Further, the actuator executes the new instruction sequence to obtain an execution result of at least one probe instruction in the new instruction sequence, determines the marking information of each node of the third layer according to the execution result, and eliminates probe instructions added behind the node instructions corresponding to each PC value of all nodes of the second layer, thereby adding the probe instructions according to the marking information of each node of the third layer. By analogy, for all nodes of each layer in the address dependency tree, after the node instruction corresponding to each PC value in each node of each layer is verified, the probe instruction added behind the node instruction can be used, so that when the node instruction corresponding to each PC value in each node of the next layer is verified, the new instruction sequence only contains the probe instruction corresponding to the node instruction corresponding to each PC value in each node of the next layer, and thus, the executed probe instruction does not exist in the new instruction sequence rerun every time, and further, unnecessary probe instructions in the new instruction sequence can be reduced, the number of probe instructions in the new instruction sequence is reduced, the execution rate of the probe instruction is increased, and the verification efficiency of the device to be verified is improved.

204. And the controller determines a target PC value according to the execution result of the probe instruction until the target PC value meets a preset condition, and takes the node instruction corresponding to the target PC value meeting the preset condition as an instruction causing an error in the instruction sequence.

In this embodiment, the controller determines the target PC value according to the execution result of the probe instruction, and after the new instruction sequence is executed, the execution result of each probe instruction in at least one probe instruction in the new instruction sequence can be obtained. If the execution result of the probe instruction is wrong, taking the PC value of the node instruction before the probe instruction with the wrong execution result as a target PC value, and determining the target PC value again every time the probe instruction with the wrong execution result is obtained.

Optionally, in step 204, determining a target PC value according to the execution result of the probe instruction until the instruction causing the error is obtained may include the following steps:

and if the execution result of the probe instruction is wrong and the PC value corresponding to the node instruction before the probe instruction is smaller than the target PC value, updating the target PC value to the PC value corresponding to the node instruction before the probe instruction until the target PC value meets a preset condition. And when the target PC value meets a preset condition, taking the node instruction corresponding to the target PC value as the instruction causing the error. And when the target PC value is the minimum PC value in the PC values of the node instructions in front of the probe instruction with the wrong execution result, the controller determines that the target PC value meets a preset condition.

In this embodiment, after the actuator executes a new instruction sequence, a first probe instruction with an incorrect execution result is obtained, a first PC value of a node instruction before the first probe instruction may be used as a target PC value, and after the new instruction sequence is executed, a second probe instruction with an incorrect execution result is obtained.

For example, as shown in fig. 2C, first, the controller may mark the root node of the address dependency tree as a probe instruction that needs to be added, and according to the mark information, add a probe instruction after a node instruction corresponding to each PC value of the root node to obtain a new instruction sequence. And the executor executes the new instruction sequence to obtain the error execution result of the probe instruction behind the node instruction A corresponding to the PC value a. At this time, the controller may mark child nodes of the root node, that is, the 2 nd node and the 3 rd node of the second layer, as probe instructions that need to be added, and use the PC value a of the node instruction before the probe instruction with the wrong execution result as the target PC value, that is, update the target PC value to a. And then, after the execution of the new instruction sequence is finished, adding a probe instruction after a node instruction corresponding to each PC value of the root node is eliminated. Then, the controller may add a probe instruction to the node instruction corresponding to each PC value of the 2 nd node and the 3 rd node according to the label information of the second layer to obtain a new instruction sequence. The executor executes a new instruction sequence, and if the probe instruction execution result behind the node instruction corresponding to the PC value c is wrong, the controller marks the child node of the 2 nd node as a probe instruction needing to be added, namely marks the 4 th node and the 5 th node as probe instructions needing to be added; and if the PC value c is smaller than the currently determined target PC value a, taking the PC value c as a new target PC value. If the probe instruction execution result after the node instruction corresponding to the PC value d and the probe instruction execution result after the node instruction corresponding to the PC value e are both correct, the controller marks the child node of the 3 rd node as a probe instruction that does not need to be added, i.e., marks the 6 th node as a probe instruction that does not need to be added, and does not update the target PC value at this time, i.e., the target PC value is still the PC value c. And in the same way, traversing the whole address dependency tree until the target PC value is the minimum PC value in the PC values of the node instructions before the probe instruction with the wrong execution result, so that the node instruction corresponding to the target PC value can be determined as the instruction causing the error.

According to the technical scheme provided by the application, the actuator runs the instruction sequence, the controller adds the probe instruction behind at least one node instruction of the address dependency tree when determining that the instruction sequence has the instruction causing the error according to the execution result of the instruction sequence to obtain a new instruction sequence, the actuator re-verifies the new instruction sequence, and the controller determines the target PC value according to the execution result of the probe instruction until the instruction causing the error is obtained.

The present application also discloses a computer-readable storage medium storing a computer program for electronic data exchange, wherein the computer program causes a computer to perform the steps of the device under test verification method as shown in fig. 2A.

The present application also discloses a computer program product comprising a non-transitory computer readable storage medium storing a computer program operable to cause a computer to perform the steps of the device under test verification method as shown in fig. 2A.

In some embodiments, a chip is also disclosed, which includes the device under test verification apparatus.

In some embodiments, a chip packaging structure is disclosed, which includes the above chip.

In some embodiments, a board card is disclosed, which includes the above chip package structure. Referring to fig. 3, fig. 3 provides a board card, which may include other kit components besides the chip 389, where the kit components include, but are not limited to: memory device 390, interface device 391 and control device 392;

the memory device 390 is connected to the chip in the chip package structure through a bus for storing data. The memory device may include a plurality of groups of memory cells 393. Each group of the storage units is connected with the chip through a bus. It is understood that each group of the memory cells may be a DDR SDRAM (Double Data Rate SDRAM).

DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read out on the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM. In one embodiment, the storage device may include 4 sets of the storage unit. Each group of the memory cells may include a plurality of DDR4 particles (chips). In one embodiment, the chip may internally include 4 72-bit DDR4 controllers, and 64 bits of the 72-bit DDR4 controller are used for data transmission, and 8 bits are used for ECC check. It can be understood that when DDR4-3200 particles are adopted in each group of memory cells, the theoretical bandwidth of data transmission can reach 25600 MB/s.

In one embodiment, each group of the memory cells includes a plurality of double rate synchronous dynamic random access memories arranged in parallel. DDR can transfer data twice in one clock cycle. And a controller for controlling DDR is arranged in the chip and is used for controlling data transmission and data storage of each memory unit.

The interface device is electrically connected with a chip in the chip packaging structure. The interface device is used for realizing data transmission between the chip and an external device (such as a server or a computer). For example, in one embodiment, the interface device may be a standard PCIE interface. For example, the data to be processed is transmitted to the chip by the server through the standard PCIE interface, so as to implement data transfer. Preferably, when PCIE 3.0X 16 interface transmission is adopted, the theoretical bandwidth can reach 16000 MB/s. In another embodiment, the interface device may also be another interface, and the present application does not limit the concrete expression of the other interface, and the interface unit may implement the switching function. In addition, the calculation result of the chip is still transmitted back to an external device (e.g., a server) by the interface device.

The control device is electrically connected with the chip. The control device is used for monitoring the state of the chip. Specifically, the chip and the control device may be electrically connected through an SPI interface. The control device may include a single chip Microcomputer (MCU). The chip may include a plurality of processing chips, a plurality of processing cores, or a plurality of processing circuits, and may carry a plurality of loads. Therefore, the chip can be in different working states such as multi-load and light load. The control device can realize the regulation and control of the working states of a plurality of processing chips, a plurality of processing andor a plurality of processing circuits in the chip.

In some embodiments, an electronic device is provided, which includes the chip or the board.

The electronic device comprises a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, an intelligent terminal, a mobile phone, a vehicle data recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, an earphone, a mobile storage, a wearable device, a vehicle, a household appliance, and/or a medical device.

The vehicle comprises an airplane, a ship and/or a vehicle; the household appliances comprise a television, an air conditioner, a microwave oven, a refrigerator, an electric cooker, a humidifier, a washing machine, an electric lamp, a gas stove and a range hood; the medical equipment comprises a nuclear magnetic resonance apparatus, a B-ultrasonic apparatus and/or an electrocardiograph.

It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are exemplary embodiments and that the acts and modules referred to are not necessarily required in this application.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one type of division of logical functions, and there may be other divisions when actually implementing, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices or units, and may be an electric or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or may be implemented in the form of a software program module.

The integrated units, if implemented in the form of software program modules and sold or used as stand-alone products, may be stored in a computer readable memory. Based on such understanding, the technical solution of the present application may be substantially implemented or a part of or all or part of the technical solution contributing to the prior art may be embodied in the form of a software product stored in a memory, and including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method described in the embodiments of the present application. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable memory, which may include: flash Memory disks, Read-Only memories (ROMs), Random Access Memories (RAMs), magnetic or optical disks, and the like.

The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the above description of the embodiments is only provided to help understand the method and the core concept of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. A device under test verification apparatus, comprising an actuator and a controller, wherein,

the executor is used for running an instruction sequence;

the executor is further used for verifying the new instruction sequence;

2. The apparatus of claim 1, wherein in adding a probe instruction after the at least one node instruction of the address dependency tree to obtain a new instruction sequence, the controller is specifically configured to:

3. The apparatus of claim 1, wherein in adding a probe instruction after the at least one node instruction of the address dependency tree to obtain a new instruction sequence, the controller is specifically configured to:

4. The apparatus according to claim 3, wherein in said obtaining tag information for nodes in the address dependency tree, the controller is specifically configured to:

5. The apparatus according to claim 3, wherein in said obtaining tag information for nodes in the address dependency tree, the controller is specifically configured to:

6. The apparatus of claim 4 or 5, wherein the controller is further configured to eliminate the probe command in the currently accessed node after the actuator completes verification of the probe command following the node command corresponding to the at least one PC value in the currently accessed node.

7. The apparatus according to any one of claims 1 to 5, wherein in the aspect that the target PC value is determined according to the execution result of the probe instruction until the target PC value meets a preset condition, and a node instruction corresponding to the target PC value meeting the preset condition is used as an instruction causing an error in the instruction sequence, the controller is specifically configured to:

8. The apparatus according to any of claims 1-5, wherein in said validating the new command sequence, the executor is specifically configured to:

9. The apparatus of claim 8, further comprising a storage unit comprising a RAM and a register, the controller further to:

after the executor runs the instruction sequence and when the execution result of the instruction sequence is wrong, constructing an address dependency tree according to the execution result of the instruction sequence; wherein, the root node of the address dependency tree comprises an RAM address area or a register number where an output result of an instruction outputting an error result in the initial instruction sequence is located; and the next level node of the address dependency tree comprises a RAM address interval or a register number where an operand of a node instruction corresponding to at least one PC value accessed by the previous level node is located.

10. A device under test verification method is applied to a device under test verification device, the device under test verification device comprises an actuator and a controller, and the method comprises the following steps:

the actuator runs a command sequence;

the executor verifies the new instruction sequence;

11. The method of claim 10, wherein adding a probe instruction after at least one node instruction of the address dependency tree to obtain a new instruction sequence comprises:

12. The method of claim 10, wherein adding a probe instruction after at least one node instruction of the address dependency tree to obtain a new instruction sequence comprises:

13. The method of claim 12, wherein obtaining the label information of the node in the address dependency tree comprises:

14. The method of claim 12, wherein obtaining the label information of the node in the address dependency tree comprises:

15. The method according to claim 13 or 14, characterized in that the method further comprises:

16. The method according to any one of claims 10 to 14, wherein the determining a target PC value according to the execution result of the probe instruction until the target PC value meets a preset condition, and taking a node instruction corresponding to the target PC value meeting the preset condition as an instruction causing an error in the instruction sequence comprises:

17. The method of any of claims 10-14, wherein the validating the new sequence of instructions comprises:

18. The method of claim 17, wherein the apparatus further comprises a storage unit comprising a RAM and a register, the method further comprising:

after the executor runs the instruction sequence and when the execution result of the instruction sequence is wrong, the controller constructs an address dependency tree according to the execution result of the instruction sequence; wherein, the root node of the address dependency tree comprises an RAM address area or a register number where an output result of an instruction outputting an error result in the initial instruction sequence is located; and the next level node of the address dependency tree comprises a RAM address interval or a register number where an operand of a node instruction corresponding to at least one PC value accessed by the previous level node is located.

19. A computer-readable storage medium, characterized in that it stores a computer program for electronic data exchange, wherein the computer program causes a computer to perform the method according to any one of claims 10-18.