CN110246459B

CN110246459B - Pixel circuit, driving method thereof, display panel and display device

Info

Publication number: CN110246459B
Application number: CN201910535904.7A
Authority: CN
Inventors: 王峥
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Display Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Display Technology Co Ltd
Priority date: 2019-06-20
Filing date: 2019-06-20
Publication date: 2021-01-22
Anticipated expiration: 2039-06-20
Also published as: CN110246459A; WO2020253398A1

Abstract

A pixel circuit, a driving method thereof, a display panel and a display device are provided. The pixel circuit includes a first drive circuit and a second drive circuit. The first driving circuit is configured to generate a first driving current for driving the first light emitting element to emit light according to the data signal, and the second driving circuit is configured to generate a second driving current for driving the second light emitting element to emit light according to the control signal. The control signal is derived from and is different from the data signal. The pixel circuit can selectively enable the second light-emitting element to emit light or not to emit light according to different data signals, so that the second light-emitting element is matched with the first light-emitting element to jointly display the gray scale corresponding to the data signals, and therefore, when a display panel and a display device comprising the pixel circuit are used for low gray scale display, the influence of electrical noise on a display picture can be reduced, and the display effect is improved.

Description

Pixel circuit, driving method thereof, display panel and display device

Technical Field

The embodiment of the disclosure relates to a pixel circuit, a driving method thereof, a display panel and a display device.

Background

The Organic Light-Emitting Diode (OLED) display panel has the advantages of thin thickness, Light weight, wide viewing angle, active Light emission, continuously adjustable Light emission color, low cost, fast response speed, low energy consumption, low driving voltage, wide working temperature range, simple production process, high Light-Emitting efficiency, flexible display and the like, and is more and more widely applied to the display fields of mobile phones, tablet computers, digital cameras and the like.

Disclosure of Invention

At least one embodiment of the present disclosure provides a pixel circuit including a first driving circuit configured to generate a first driving current for driving a first light emitting element to emit light according to a data signal and a second driving circuit configured to generate a second driving current for driving a second light emitting element to emit light according to a control signal, the control signal being derived from the data signal and different from the data signal.

For example, some embodiments of the present disclosure provide pixel circuits further comprising a voltage regulation circuit, wherein the voltage regulation circuit is configured to generate the control signal according to the data signal.

For example, in some embodiments of the present disclosure, the voltage regulating circuit includes a first switching transistor, a gate and a first pole of the first switching transistor are both connected to the control terminal of the first driving circuit, and a second pole of the first switching transistor is connected to the control terminal of the second driving circuit to form a diode structure.

For example, some embodiments of the present disclosure provide pixel circuits in which the voltage regulating circuit includes a diode, a first pole of the diode is connected to the control terminal of the first driving circuit, and a second pole of the diode is connected to the control terminal of the second driving circuit.

For example, some embodiments of the present disclosure provide pixel circuits, further including the first light emitting element, wherein a first pole of the first light emitting element is connected to a first power supply terminal to receive a first power supply voltage, the first driving circuit includes a first driving transistor, a gate of the first driving transistor is used as a control terminal of the first driving circuit, the first pole of the first driving transistor is connected to a second pole of the first light emitting element, and the second pole of the first driving transistor is connected to the second power supply terminal to receive a second power supply voltage.

For example, some embodiments of the present disclosure provide pixel circuits, further including the second light emitting element, wherein a first pole of the second light emitting element is connected to the first power supply terminal to receive the first power supply voltage, the second driving circuit includes a second driving transistor, a gate of the second driving transistor is used as a control terminal of the second driving circuit, a first pole of the second driving transistor is connected to a second pole of the second light emitting element, and a second pole of the second driving transistor is connected to the second power supply terminal to receive the second power supply voltage.

For example, some embodiments of the present disclosure provide pixel circuits further comprising an input circuit, wherein the input circuit is configured to apply the data signal to a control terminal of the first driving circuit in response to a first scan signal.

For example, in some embodiments of the present disclosure, the input circuit includes a second switching transistor, a gate of the second switching transistor is connected to the first scan signal terminal to receive the first scan signal, a first pole of the second switching transistor is connected to the data signal terminal to receive the data signal, and a second pole of the first switching transistor is connected to the control terminal of the first driving circuit.

For example, some embodiments of the present disclosure provide pixel circuits further including a first storage circuit configured to store the data signal and a first reset circuit configured to reset a control terminal of the first driving circuit in response to a second scan signal.

For example, in the pixel circuit provided in some embodiments of the present disclosure, the first storage circuit includes a first storage capacitor, the first reset circuit includes a third switching transistor, a first terminal of the first storage capacitor is coupled to the control terminal of the first driving circuit, a second terminal of the first storage capacitor is coupled to the control terminal of the second driving circuit, a gate of the third switching transistor is connected to the second scan signal terminal to receive the second scan signal, a first pole of the third switching transistor is connected to the control terminal of the first driving circuit, and a second pole of the third switching transistor is connected to the control terminal of the second driving circuit; or, a first terminal of the first storage capacitor is coupled to the control terminal of the first driving circuit, a second terminal of the first storage capacitor is connected to the second power terminal, a gate of the third switching transistor is connected to the second scan signal terminal to receive the second scan signal, a first terminal of the third switching transistor is connected to the control terminal of the first driving circuit, and a second terminal of the third switching transistor is connected to the second power terminal.

For example, some embodiments of the present disclosure provide pixel circuits further including a second storage circuit configured to store the control signal and a second reset circuit configured to reset a control terminal of the second driving circuit in response to a second scan signal.

For example, in some embodiments of the present disclosure, the second storage circuit includes a second storage capacitor, the second reset circuit includes a fourth switching transistor, a first terminal of the second storage capacitor is coupled to the control terminal of the second driving circuit, a second terminal of the second storage capacitor is connected to the second power supply terminal, a gate of the fourth switching transistor is connected to the second scan signal terminal to receive the second scan signal, a first electrode of the fourth switching transistor is connected to the control terminal of the second driving circuit, and a second electrode of the fourth switching transistor is connected to the second power supply terminal.

For example, some embodiments of the present disclosure provide pixel circuits in which the level range of the data signal includes a first range and a second range, the first driving current is greater than zero and the second driving current is equal to zero when the level of the data signal is in the first range, and both the first driving current and the second driving current are greater than zero when the level of the data signal is in the second range.

For example, in the pixel circuit provided in some embodiments of the present disclosure, the light emitting colors of the first light emitting element and the second light emitting element are the same, and the area of the light emitting region of the first light emitting element is smaller than the area of the light emitting region of the second light emitting element.

At least one embodiment of the present disclosure further provides a display panel, which includes a plurality of sub-pixels arranged in an array, wherein each of the sub-pixels includes the pixel circuit provided in any one of the embodiments of the present disclosure.

At least one embodiment of the present disclosure further provides a display device including the display panel provided in any one of the embodiments of the present disclosure.

At least one embodiment of the present disclosure further provides a driving method of a pixel circuit provided in accordance with any one of the embodiments of the present disclosure, including: and providing the data signal for the pixel circuit, so that the first light-emitting element and the second light-emitting element jointly display the gray scale to be displayed corresponding to the data signal.

For example, in some embodiments of the present disclosure, the gray scale range of the gray scale to be displayed includes a first gray scale range and a second gray scale range, and the level range of the data signal includes a first range and a second range; when the gray scale to be displayed is in the first gray scale range, providing the data signal in the first range for the pixel circuit, so that the first light-emitting element emits light and the second light-emitting element does not emit light; and when the gray scale to be displayed is in the second gray scale range, providing the data signal in the second range for the pixel circuit, so that the first light-emitting element and the second light-emitting element emit light.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

FIG. 1A is a schematic diagram of a 2T1C pixel circuit;

FIG. 1B is a schematic diagram of another 2T1C pixel circuit;

fig. 2 is a schematic block diagram of a pixel circuit according to at least one embodiment of the present disclosure;

fig. 3 is a schematic block diagram of another pixel circuit provided in at least one embodiment of the present disclosure;

fig. 4 is a circuit structure diagram of a specific implementation example of the pixel circuit shown in fig. 2;

FIG. 5 is a circuit diagram of an exemplary implementation of the pixel circuit shown in FIG. 3;

fig. 6 is a circuit configuration diagram of another specific implementation example of the pixel circuit shown in fig. 2;

FIG. 7 is a circuit diagram illustrating another exemplary implementation of the pixel circuit shown in FIG. 3;

fig. 8 is a signal timing diagram of a driving method of a pixel circuit according to at least one embodiment of the present disclosure;

fig. 9 is a schematic view of a display panel according to at least one embodiment of the present disclosure; and

fig. 10 is a schematic view of a display device according to at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

The present disclosure is illustrated by the following specific examples. A detailed description of known functions and known parts (elements) may be omitted in order to keep the following description of the embodiments of the present disclosure clear and concise. When any element of an embodiment of the present disclosure appears in more than one drawing, that element is identified in each drawing by the same or similar reference numeral.

The pixel circuits in the OLED display panel generally adopt a Matrix driving method, and are classified into Active Matrix (AM) driving and Passive Matrix (PM) driving according to whether a switching device is introduced into each sub-pixel. For example, the AMOLED integrates a group of thin film transistors and storage capacitors in the pixel circuit of each sub-pixel, and the current flowing through the OLED is controlled by driving and controlling the thin film transistors and the storage capacitors, so that the OLED emits light according to a gray scale to be displayed. Therefore, the AMOLED needs small driving current, low power consumption and longer service life, and can meet the large-size display requirements of high resolution and multi-gray scale. Meanwhile, the AMOLED has obvious advantages in the aspects of visual angle, color reduction, power consumption, response time and the like, and is suitable for display devices with high information content and high resolution.

The basic pixel circuit used in the AMOLED display panel is generally a 2T1C pixel circuit, i.e., two Thin-Film transistors (TFTs) and a storage capacitor Cs are used to implement the basic function of driving the OLED to emit light. Fig. 1A and 1B respectively show schematic diagrams of two kinds of 2T1C pixel circuits.

As shown in fig. 1A, a 2T1C pixel circuit includes a switching transistor T0, a driving transistor N0, and a storage capacitor Cs. For example, the gate of the switching transistor T0 is connected to the Scan line for receiving the Scan signal Scan1, for example, the source is connected to the data signal line for receiving the data signal Vdata, and the drain is connected to the gate of the driving transistor N0; the source of the driving transistor N0 is connected to a first voltage terminal to receive a first voltage Vdd (high voltage), and the drain is connected to the positive terminal of the OLED; one end of the storage capacitor Cs is connected to the drain of the switching transistor T0 and the gate of the driving transistor N0, and the other end is connected to the source of the driving transistor N0 and a first voltage terminal; the cathode terminal of the OLED is connected to the second voltage terminal to receive a second voltage Vss (low voltage, e.g., ground voltage).

The 2T1C pixel circuit is driven by controlling the brightness (gray scale) of the sub-pixels via two TFTs and a storage capacitor Cs. When the Scan signal Scan1 is applied through the Scan line to turn on the switch transistor T0, the data signal Vdata inputted from the data signal line by the data driving circuit will charge the storage capacitor Cs through the switch transistor T0, so that the data signal Vdata is stored in the storage capacitor Cs, and the stored data signal Vdata controls the conduction degree of the driving transistor N0, so as to control the magnitude of the current flowing through the driving transistor N0 to drive the OLED to emit light, i.e. the current determines the gray scale of the sub-pixel to emit light. In the 2T1C pixel circuit shown in fig. 1A, the switching transistor T0 is an N-type transistor and the driving transistor N0 is a P-type transistor.

As shown in fig. 1B, another 2T1C pixel circuit also includes a switch transistor T0, a driving transistor N0 and a storage capacitor Cs, but the connection is slightly changed, and the driving transistor N0 is an N-type transistor. The variations of the pixel circuit of FIG. 1B relative to FIG. 1A include: the positive terminal of the OLED is connected to the first voltage terminal to receive the first voltage Vdd (high voltage), while the negative terminal is connected to the drain of the driving transistor N0, and the source of the driving transistor N0 is connected to the second voltage terminal to receive the second voltage Vss (low voltage, e.g., ground voltage). One end of the storage capacitor Cs is connected to the drain of the switching transistor T0 and the gate of the driving transistor N0, and the other end is connected to the source of the driving transistor N0 and a second voltage terminal. The 2T1C pixel circuit operates in substantially the same manner as the pixel circuit shown in fig. 1A, and is not described here again.

In the pixel circuit shown in fig. 1A and 1B, the switching transistor T0 is not limited to an N-type transistor, but may be a P-type transistor, and the polarity of the Scan signal Scan1 for controlling on/off of the switching transistor may be changed accordingly.

In practical applications, on the basis of the 2T1C pixel circuit described above, the pixel circuit may further include a compensation transistor, a reset transistor, a sensing transistor, and the like to have a compensation function, a reset function, a sensing function, and the like, accordingly.

The AMOLED display panel generally includes a plurality of sub-pixels arranged in an array, and each sub-pixel may include, for example, the pixel circuit and the OLED described above. The pixel circuit is used for generating and controlling the driving current flowing through the OLED to drive the OLED to emit light, so that the AMOLED display panel displays. For example, each sub-pixel typically includes only 1 OLED, and accordingly, the pixel circuit typically includes only 1 driving transistor (shown with reference to fig. 1A and 1B). When the AMOLED display panel displaysThe gray level displayed by each sub-pixel is determined by the intensity of the driving current I (i.e. the current flowing through the driving transistor to drive the OLED to emit light). The driving currents I and (Vgs-Vth) generated by the pixel circuits in the sub-pixels²Proportional ratio, where Vgs is the voltage difference between the gate and source of the driving transistor and Vth is the threshold voltage of the driving transistor.

In the study, the inventors of the present application noted that: when electrical noise (e.g., fluctuation of the data signal Vdata, etc.) exists in the pixel circuit to cause a voltage difference actually loaded between the gate and the source of the driving transistor to deviate from an intended Vgs, assuming that the deviation (i.e., fluctuation of Vgs) is d (Vgs), accordingly, an actually generated driving current will deviate from an intended driving current I, assuming that the deviation (i.e., fluctuation of the driving current I) is dI, the following formula (1) can be derived by simple mathematical derivation:

this formula (1) shows that, in the case where the fluctuation of Vgs (i.e., d (Vgs)) caused by electrical noise is constant, at the time of high gray scale display, the driving current I is large, i.e., | Vgs-Vth | is large, and thus | dI/I | is small, i.e., the driving current is less affected; in contrast, in the low gray scale display, the driving current I is small, i.e., | Vgs-Vth | is small, and thus | dI/I | is large, i.e., the driving current is greatly influenced. Therefore, in the low gray scale display, the fluctuation of Vgs caused by the electrical noise may cause the gray scale of the actual display to deviate from the gray scale of the intended display, i.e., display inaccuracy, thereby affecting the display effect.

At least one embodiment of the present disclosure provides a pixel circuit. The pixel circuit includes a first drive circuit and a second drive circuit. The first driving circuit is configured to generate a first driving current for driving the first light emitting element to emit light according to the data signal, and the second driving circuit is configured to generate a second driving current for driving the second light emitting element to emit light according to the control signal. The control signal is derived from and is different from the data signal.

Some embodiments of the disclosure also provide a driving method, a display panel and a display device corresponding to the pixel circuit.

The pixel circuit provided by the embodiment of the disclosure can selectively enable the second light emitting element to emit light or not to emit light according to different data signals, so that the second light emitting element is matched with the first light emitting element to jointly display the gray scale corresponding to the data signals, and therefore, when a display panel and a display device comprising the pixel circuit are used for low gray scale display, the influence of electrical noise on a display picture can be reduced, and the display effect is improved.

Some embodiments of the present disclosure and examples thereof are described in detail below with reference to the accompanying drawings.

Fig. 2 is a schematic block diagram of a pixel circuit according to at least one embodiment of the present disclosure. For example, the pixel circuit 100 may be used in a sub-pixel of an AMOLED display panel, an inorganic Light Emitting Diode display panel, or a Quantum Dot Light Emitting Diode (QLED) display panel. For example, as shown in fig. 2, the pixel circuit 100 includes a first driving circuit 110, a second driving circuit 120, a first light emitting element 210, and a second light emitting element 220. That is, the first driving circuit 110, the second driving circuit 120, the first light emitting element 210, and the second light emitting element 220 are located in the same sub-pixel.

For example, as shown in fig. 2, the first driving circuit 110 includes a control terminal 111, a first terminal 112 and a second terminal 113, and is configured to generate a first driving current for driving the first light emitting element 210 to emit light according to a data signal. For example, in some examples, during the light emitting phase, the first driving circuit 110 may provide a first driving current to the first light emitting element 210 to drive the first light emitting element 210 to emit light according to a gray scale to be displayed by a sub-pixel including the pixel circuit 100 (different gray scales correspond to different data signals).

For example, the gray scale range of the gray scale to be displayed includes a first gray scale range and a second gray scale range. For example, in some examples, when the gray scale to be displayed is within the first gray scale range, the first light emitting element displays the gray scale to be displayed, that is, the light emitting brightness of the first light emitting element 210 meets the requirement of the gray scale to be displayed; when the gray scale to be displayed is within the second gray scale range, the luminance of the first light emitting element 210 is lower than the requirement of the gray scale to be displayed, and the second light emitting element 220 is made to emit light, so that the first light emitting element 210 and the second light emitting element 220 jointly display the gray scale to be displayed, that is, the superposition of the luminance of the first light emitting element 210 and the luminance of the second light emitting element 220 meets the requirement of the gray scale to be displayed.

For example, as shown in fig. 2, the second driving circuit 120 includes a control terminal 121, a first terminal 122 and a second terminal 123, and is configured to generate a second driving current for driving the second light emitting element 220 to emit light according to the control signal. For example, the control signal may be derived from and different from the data signal. For example, in some examples, in the light emitting phase, when the gray scale to be displayed is in the first gray scale range, the control signal obtained according to the data signal is insufficient to enable the second driving circuit 120 to provide the second driving current to the second light emitting element 220 (i.e. the generated second driving current is zero), so that the second light emitting element 220 does not emit light; when the gray scale to be displayed is within the second gray scale range, the control signal obtained according to the data signal can enable the second driving circuit 120 to provide the second driving current to the second light emitting element 220 to drive the second light emitting element 220 to emit light, and at this time, the superposition of the light emitting brightness of the second light emitting element 220 and the light emitting brightness of the first light emitting element 210 (i.e. the sum of the light emitting brightness of the two) meets the requirement of the gray scale to be displayed.

The gray scale range depends on the gray scale signal, and thus, the gray scale range may have various forms. For example, the gray scale signal can be 8 bits, and the corresponding gray scale range is [0,255 ]; alternatively, the gray scale signal may be 12 bits, and the corresponding gray scale range is [0,4095], etc. In the following, the division of the gray scale range is exemplified by the gray scale range of [0,255], but should not be construed as limiting the present disclosure. For example, in some examples, the first gray scale range is [0, n ], the second gray scale range is (n,255], where 0< n <255 and n is an integer, so that the first gray scale range can be defined as a low gray scale range and the second gray scale range can be defined as a high gray scale range.

For example, the first and second light emitting elements 210 and 220 may employ the same kind of light emitting diode, for example, an Organic Light Emitting Diode (OLED), a quantum dot light emitting diode (QLED), an inorganic light emitting diode, and the like, and the embodiments of the present disclosure include, but are not limited thereto. For example, the first light emitting element 210 and the second light emitting element 220 may be composed of the same or different materials, and may also be simultaneously formed on the array substrate of the display panel through the same semiconductor process step, and embodiments of the present disclosure include, but are not limited thereto. For example, the area of the light emitting region of the first light emitting element 210 is smaller than the area of the light emitting region of the second light emitting element 220.

For example, in the embodiment of the present disclosure, when a low gray scale is displayed, only the first light emitting element 210 is made to emit light, and the second light emitting element 220 is made not to emit light. Since the area of the light emitting region of the first light emitting element 210 is smaller, compared with a common pixel circuit including only one light emitting element, in order to achieve a required gray scale, the voltage value of the data signal supplied to the first light emitting element 210 (in the case where the first driving circuit 110 is implemented as an N-type transistor) is larger, so that the difference between the voltage of the data signal at this time and the voltage of the data signal corresponding to a zero gray scale is larger, and thus the pixel circuit 100 has stronger control power on the driving current, stronger interference resistance, and more accurate gray scale display. In the case where the first driving circuit 110 is implemented as a P-type transistor, when displaying a low gray scale, the difference between the voltage of the data signal provided to the first light emitting element 210 and the voltage of the data signal corresponding to the zero gray scale is also larger, so that the pixel circuit 100 can have stronger control over the driving current, stronger interference resistance, and more accurate gray scale display.

For example, as shown in fig. 2, the pixel circuit 100 may further include a voltage regulating circuit 130. The voltage regulating circuit 130 is configured to generate a control signal according to a data signal. For example, in some examples, as shown in fig. 2, the voltage regulating circuit 130 is connected to the control terminal 111 of the first driving circuit 110 and the control terminal 121 of the second driving circuit 120, respectively. For example, in some examples, in the data writing phase, the voltage regulating circuit 130 may generate a control signal according to the data signal received by the control terminal 111 of the first driving circuit 110, and apply the generated control signal to the control terminal 121 of the second driving circuit 120, so as to enable the second driving circuit 120 to generate a second driving current for driving the second light emitting element 220 to emit light according to the control signal in the subsequent light emitting phase. For example, in some examples, the voltage adjustment circuit 130 generates a control signal having a voltage value that is less than the absolute value of the voltage value of the data signal, e.g., the voltage value of the control signal and the voltage value of the data signal are both positive and the voltage value of the control signal is less than the voltage value of the data signal.

For example, as shown in fig. 2, the pixel circuit 100 may further include an input circuit 140. The input circuit 140 is configured to apply a data signal to the control terminal 111 of the first driving circuit 110 in response to the first scan signal SN 1. For example, in some examples, in the DATA writing phase, the input circuit 140 is turned on in response to the first scan signal SN1, so as to apply the DATA signal provided by the DATA signal terminal DATA to the control terminal 111 of the first driving circuit 110, so as to enable the first driving circuit 110 to generate the first driving current for driving the first light emitting element 210 to emit light according to the DATA signal in the subsequent light emitting phase.

For example, as shown in fig. 2, the pixel circuit 100 may further include a first storage circuit 150 and a first reset circuit 160. The first storage circuit 150 is configured to store a data signal, and the first reset circuit 160 is configured to reset the control terminal 111 of the first driving circuit 110 in response to the second scan signal SN 2. For example, in some examples, as shown in fig. 2, the first storage circuit 150 is connected to the control terminal 111 of the first driving circuit 110, so that the data signal received by the control terminal 111 of the first driving circuit 110 can be stored in the data writing phase. For example, in some examples, as shown in fig. 2, the first reset circuit 160 is connected to the control terminal 111 of the first driving circuit 110, so that the control terminal 111 of the first driving circuit 110 and the first storage circuit 150 may be reset in response to the second scan signal SN2 in a reset phase.

For example, as shown in fig. 2, the pixel circuit 100 may further include a second storage circuit 170 and a second reset circuit 180. The second storage circuit 170 is configured to store the control signal, and the second reset circuit 180 is configured to reset the control terminal 121 of the second driving circuit 120 in response to the second scan signal SN 2. For example, in some examples, as shown in fig. 2, the second storage circuit 170 is connected to the control terminal 121 of the second driving circuit 120, so that the control signal received by the control terminal 121 of the second driving circuit 120 can be stored in the data writing phase. For example, in some examples, as shown in fig. 2, the second reset circuit 180 is connected to the control terminal 121 of the second driving circuit 120, so that the control terminal 121 of the second driving circuit 120 and the second storage circuit 170 may be reset in response to the second scan signal SN2 in the reset phase.

It should be noted that the first scan signal SN1 and the second scan signal SN2 are described in the embodiments of the present disclosure to distinguish two scan control signals with different timings. For example, as described below, in an exemplary display device, when the pixel circuits 100 are arranged in an array, the first scan signal SN1 may be a scan control signal that controls the input circuits 140 in the pixel circuits 100 of the present row; the second scan signal SN2 may be a scan control signal that controls the input circuit 140 in the pixel circuit 100 of the previous row, and at the same time, the second scan signal SN2 also controls the first reset circuit 160 and the second reset circuit 180 in the pixel circuit 100 of the present row.

Fig. 3 is a schematic block diagram of another pixel circuit provided in at least one embodiment of the present disclosure. The pixel circuit shown in fig. 3 is different from the pixel circuit shown in fig. 2 in that: the first storage circuit 150 and the first reset circuit 160 are connected in different ways. It should be noted that other circuit structures of the pixel circuit shown in fig. 3 are substantially the same as those of the pixel circuit shown in fig. 2, and repeated parts are not repeated herein. Hereinafter, only differences between the pixel circuit shown in fig. 3 and the pixel circuit shown in fig. 2 will be described in comparison.

For example, in the pixel circuit 100 shown in fig. 2, one end of the first memory circuit 150 is connected to the control terminal 111 of the first driving circuit 110, and the other end of the first memory circuit 150 is connected to the second power source terminal ELVSS (for supplying the second power source voltage VSS), so that the voltage of the other end of the first memory circuit 150 is maintained at the second power source voltage VSS. For example, in the pixel circuit 100 shown in fig. 3, one end of the first storage circuit 150 is connected to the control terminal 111 of the first drive circuit 110, and the other end of the first storage circuit 150 is connected to the control terminal 121 of the second drive circuit 120, so that the voltage of the other end of the first storage circuit 150 is kept the same as the voltage of the control terminal 121 of the second drive circuit 120. It should be noted that although the first storage circuit 150 is connected in a different manner in the pixel circuit 100 shown in fig. 2 and 3, the first storage circuit 150 is not affected to realize the function of storing the data signal, and thus the normal operation of the pixel circuit 100 is not affected.

For example, in the pixel circuit 100 shown in fig. 2, the first reset circuit 160 is respectively connected to the second scan signal terminal (for providing the second scan signal SN2), the control terminal 111 of the first driving circuit 110, and the second power supply terminal ELVSS (the second power supply voltage VSS may be used for resetting the control terminal 111 of the first driving circuit 110), so that the control terminal 111 of the first driving circuit 110 and the first storage circuit 150 may be directly reset in response to the second scan signal SN2 in the reset phase. For example, in the pixel circuit 100 shown in fig. 3, the first reset circuit 160 is connected to the second scan signal terminal, the control terminal 111 of the first drive circuit 110, and the control terminal 121 of the second drive circuit 120, respectively, and since the second reset circuit 180 is turned on in the reset phase (the second reset circuit 180 resets the control terminal 121 of the second drive circuit 120 and the second storage circuit 170), the first reset circuit 160 can indirectly reset the control terminal 111 of the first drive circuit 110 and the first storage circuit 150 in response to the second scan signal SN2 in the reset phase, that is, the reset operation of the first reset circuit 160 needs to be performed when the second reset circuit 180 is turned on. It should be noted that although the first reset circuit 160 is connected in a different manner in the pixel circuit 100 shown in fig. 2 and 3, the first reset circuit 160 does not affect the function of performing the reset operation on the first driving circuit 110 and the first storage circuit 150, and thus the normal operation of the pixel circuit 100 is not affected.

It should be understood that the connection manner of the first storage circuit 150 and the first reset circuit 160 may also take other forms, for example, in the pixel circuit provided in some embodiments of the present disclosure, the first storage circuit 150 may adopt the connection manner shown in fig. 2, and the first reset circuit 160 may adopt the connection manner shown in fig. 3; alternatively, the first memory circuit 150 may employ the connection scheme shown in fig. 3, and the first reset circuit 160 may employ the connection scheme shown in fig. 2, or the like. It should also be understood that the second storage circuit 170 and the second reset circuit 180 may have other connection modes as long as they can perform their own necessary functions without affecting the normal operation of the pixel circuit 100.

It should be noted that, in practical applications, on the basis of the pixel circuit 100, the pixel circuit provided in the embodiment of the present disclosure may further include a compensation circuit, a sensing circuit, and the like to have a compensation function, a sensing function, and the like accordingly, and the embodiment of the present disclosure is not limited thereto.

Fig. 4 is a circuit configuration diagram of a specific implementation example of the pixel circuit shown in fig. 2. As shown in fig. 4, the pixel circuit 200 includes: a first driving transistor M1, a second driving transistor M2, first to fourth switching transistors T1, T2, T3, T4, a first storage capacitor Cs1, a second storage capacitor Cs2, and a first light emitting element L1 and a second light emitting element L2. For example, the first light emitting element L1 is the first light emitting element 210, and the second light emitting element L2 is the second light emitting element 220.

For example, the first light emitting element 210 and the second light emitting element 220 may be located in the same sub-pixel. For example, the first and second light emitting elements 210 and 220 may employ the same kind of light emitting diode, for example, an Organic Light Emitting Diode (OLED), a quantum dot light emitting diode (QLED), an inorganic light emitting diode, and the like, and the embodiments of the present disclosure include, but are not limited thereto. For example, the first light emitting element 210 and the second light emitting element 220 may be composed of the same material, and may also be simultaneously formed on the array substrate of the display panel through the same semiconductor process step, and embodiments of the present disclosure include, but are not limited thereto. For example, the first and second light emitting elements 210 and 220 emit light of the same color. For example, the area of the light emitting region of the first light emitting element 210 is smaller than the area of the light emitting region of the second light emitting element 220.

In the following embodiments, the first light emitting element 210 and the second light emitting element 220 are illustrated by using OLEDs, and are not described again. For example, the OLED may be of various types, such as top emission, bottom emission, and the like, and may emit red light, green light, blue light, or white light, and the like, which is not limited by the embodiments of the present disclosure. In addition, the following embodiments also describe the case where each transistor is an N-type transistor, but this does not limit the embodiments of the present disclosure.

For example, as shown in fig. 4, the first driving circuit 110 may be implemented as a first driving transistor M1. For example, as shown in fig. 4, a first pole (e.g., an anode) of the first light emitting element L1 (i.e., the first light emitting element 210) is connected to the first power source terminal ELVDD to receive the first power source voltage VDD; the gate of the first driving transistor M1 is connected as the control terminal 111 of the first driving circuit 110 and the first node P1, the first pole of the first driving transistor M1 is connected as the first terminal 112 of the first driving circuit 110 and the second pole (e.g., cathode) of the first light emitting element L1, and the second pole of the first driving transistor M1 is connected as the second terminal 113 of the first driving circuit 110 and the second power source terminal ELVSS to receive the second power source voltage VSS. For example, the first power supply voltage VDD may be a driving voltage, such as a high voltage. For example, the second power supply voltage VSS may be a low voltage, for example, the second power source terminal ELVSS may be grounded (e.g., to a common ground), so that the second power supply voltage VSS may be a zero voltage.

For example, as shown in fig. 4, the second driving circuit 120 may be implemented as a second driving transistor M2. For example, as shown in fig. 4, a first pole (e.g., an anode) of the second light emitting element L2 (i.e., the second light emitting element 220) is connected to the first power source terminal ELVDD to receive the first power source voltage VDD; the gate electrode of the second driving transistor M2 is connected as the control terminal 121 of the second driving circuit 120 and the second node P2, the first electrode of the second driving transistor M2 is connected as the first terminal 122 of the second driving circuit 120 and the second pole (e.g., cathode) of the second light emitting element L2, and the second electrode of the second driving transistor M2 is connected as the second terminal 123 of the second driving circuit 120 and the second power source terminal ELVSS to receive the second power source voltage VSS.

For example, the first driving transistor M1 and the second driving transistor M2 may be composed of the same material, and may also be simultaneously formed on the array substrate of the display panel through the same semiconductor process step, and embodiments of the present disclosure include, but are not limited to, this. For example, the threshold voltage Vth1 of the first driving transistor M1 and the threshold voltage Vth2 of the second driving transistor M2 may be the same or different. For example, in some examples, the threshold voltage Vth1 of the first driving transistor M1 may be less than or equal to the threshold voltage Vth2 of the second driving transistor M2.

For example, as shown in fig. 4, the voltage regulating circuit 130 may be implemented as a first switching transistor T1. For example, as shown in fig. 4, the gate and the first pole of the first switching transistor T1 are both connected to the first node P1, and thus to the gate of the first driving transistor M1 (i.e., the control terminal 111 of the first driving circuit 110); the second pole of the first switching transistor T1 is connected to the second node P2, and thus to the gate of the second driving transistor M2 (i.e., the control terminal 121 of the second driving circuit 120). Thus, the first switch transistor T1 forms a diode structure, and the turn-on voltage drop thereof is the threshold voltage Vtht1 of the first switch transistor T1. For example, in some examples, during the data writing phase, the first switching transistor T1 may generate the control signal Vctrl at the second node P2 according to the magnitude comparison relationship between the data signal Vdata received at the first node P1 (i.e., the gate of the first driving transistor M1) and the Vtht1, and provide the control signal Vctrl to the gate of the second driving transistor M2. For example, in some examples, Vdata > Vctrl > 0.

For example, in some examples, when Vdata ≦ Vtht1, the first switching transistor T1 is turned off, and the control signal Vctrl cannot be generated according to the data signal Vdata (the generated control signal Vctrl may also be considered to be 0), at which time the voltage of the gate of the second driving transistor M2 is maintained at a low voltage (e.g., ground voltage, i.e., zero voltage), for example, in the reset phase; the first driving transistor M1 may generate a first driving current according to the data signal Vdata to make the first light emitting element L1 emit light, and the second driving transistor M2 does not generate a second driving current (i.e., the second driving current is zero), so that the second light emitting element L2 does not emit light; in this case, the first light emitting element L1 displays a gray scale to be displayed. When Vtht1< Vdata is not less than Vtht1+ Vth2, the first switching transistor T1 is turned on, and a control signal Vctrl is generated as Vdata-Vtht1, where Vctrl is not less than Vth2, at this time, the voltage of the gate of the second driving transistor M2 is Vctrl, and the second driving transistor M2 is turned off; the first driving transistor M1 may generate a first driving current according to the data signal Vdata to make the first light emitting element L1 emit light, and the second driving transistor M2 does not generate a second driving current (i.e., the second driving current is zero), so that the second light emitting element L2 does not emit light; in this case, the first light emitting element L1 displays a gray scale to be displayed. When Vdata > Vtht1+ Vth2, the first switching transistor T1 is turned on, and a control signal Vctrl is generated as Vdata-Vtht1, where Vctrl > Vth2, at this time, the voltage of the gate of the second driving transistor M2 is Vctrl, and the second driving transistor M2 is turned on; the first driving transistor M1 may generate a first driving current according to the data signal Vdata to make the first light emitting element L1 emit light, and the second driving transistor M2 may generate a second driving current according to the control signal Vctrl to make the second light emitting element L2 emit light; in this case, the second light emitting element L2 and the first light emitting element L1 collectively display a gray scale to be displayed.

For example, as shown in fig. 4, the input circuit 140 may be implemented as a second switching transistor T2. For example, as shown in fig. 4, the gate of the second switching transistor T2 is connected to the first scan signal terminal to receive the first scan signal SN1, the first pole of the second switching transistor T2 is connected to the DATA signal terminal DATA to receive the DATA signal Vdata, and the second pole of the second switching transistor T2 is connected to the first node P1 (i.e., the gate of the first driving transistor M1, i.e., the control terminal 111 of the first driving circuit 110). For example, the level range of the DATA signal Vdata supplied from the DATA signal terminal DATA includes a first range and a second range. For example, the first range corresponds to a first gray scale range (e.g., [0, n ] as described above) of gray scales to be displayed, and for example, for the pixel circuit shown in FIG. 4, in the first range, Vdata ≦ Vtht1+ Vth2 is satisfied for the data signal; for example, the second range corresponds to a second gray scale range of gray scales to be displayed, for example, for the pixel circuit shown in fig. 4, in the second range, the data signal satisfies Vdata > Vtht1+ Vth 2. For example, in some examples, when the gray scale to be displayed is n (n is a boundary point between the first gray scale range and the second gray scale range), the data signal corresponding to the gray scale n is vdata (n), and vdata (n) ≦ Vtht1+ Vth2, at this time, the first driving current is greater than zero, the first light emitting element L1 emits light, the second driving current is equal to zero, the second light emitting element L2 does not emit light, and the light emitting luminance of the first light emitting element L1 meets the requirement of the gray scale n to be displayed; when the gray scale to be displayed is n +1, the data signal corresponding to the gray scale n +1 is Vdata (n +1), and Vdata (n +1) > Vtht1+ Vth2, at this time, both the first driving current and the second driving current are greater than zero, both the first light-emitting element L1 and the second light-emitting element L2 emit light, and the superposition of the light-emitting luminance of the second light-emitting element L2 and the light-emitting luminance of the first light-emitting element L1 meets the requirement of the gray scale n +1 to be displayed.

For example, as shown in fig. 4, the first storage circuit 150 may be implemented as a first storage capacitor Cs 1. For example, as shown in fig. 4, a first terminal of the first storage capacitor Cs1 is coupled to the gate of the first driving transistor M1 (i.e., the control terminal 111 of the first driving circuit 110), and a second terminal of the first storage capacitor Cs1 is connected to the second power source terminal ELVSS. For example, the potential of the first terminal of the first storage capacitor Cs1 may be maintained at the potential of the first node P1, and the potential of the second terminal of the first storage capacitor Cs1 may be maintained at the second power supply voltage VSS. For example, in some examples, during the data writing phase, the data signal Vdata may be applied to the first node P1 (i.e., the first end of the first storage capacitor Cs 1) through the second switching transistor T2, and thus, the first storage capacitor Cs1 may store the data signal Vdata.

For example, as shown in fig. 4, the first reset circuit 160 may be implemented as a third switching transistor T3. For example, as shown in fig. 4, the gate of the third switching transistor T3 is connected to the second scan signal terminal to receive the second scan signal SN2, the first pole of the third switching transistor T3 is connected to the gate of the first driving transistor M1 (i.e., the control terminal 111 of the first driving circuit 110), and the second pole of the third switching transistor T3 is connected to the second power source terminal ELVSS. For example, in some examples, the third switching transistor T3 may be turned on in response to an active level (e.g., a high level) of the second scan signal SN2 in a reset phase, thereby applying the second power supply voltage VSS to the gate of the first driving transistor M1 to perform a reset operation on the first driving transistor M1 and the first storage capacitor Cs 1.

For example, as shown in fig. 4, the second storage capacitance 170 may be implemented as a second storage capacitance Cs 2. For example, as shown in fig. 4, a first terminal of the second storage capacitor Cs2 is coupled to the gate of the second driving transistor M2 (i.e., the control terminal 121 of the second driving circuit 120), and a second terminal of the second storage capacitor Cs2 is connected to the second power source terminal ELVSS. For example, the potential of the first terminal of the second storage capacitor Cs2 may be maintained at the potential of the second node P2, and the potential of the second terminal of the second storage capacitor Cs2 may be maintained at the second power supply voltage VSS. For example, in some examples, in the data writing phase, the control signal Vctrl generated by the first switching transistor T1 according to the data signal Vdata is applied to the second node P2 (i.e., the first end of the second storage capacitor Cs 2), and thus, the second storage capacitor Cs2 may store the control signal Vctrl.

For example, as shown in fig. 4, the second reset circuit 180 may be implemented as a fourth switching transistor T4. For example, as shown in fig. 4, the gate electrode of the fourth switching transistor T4 is connected to the second scan signal terminal to receive the second scan signal SN2, the first electrode of the fourth switching transistor T4 is connected to the gate electrode of the second driving transistor M2 (i.e., the control terminal 121 of the second driving circuit 120), and the second electrode of the fourth switching transistor T4 is connected to the second power source terminal ELVSS. For example, in some examples, in the reset phase, the fourth switching transistor T4 may be turned on in response to an active level (e.g., a high level) of the second scan signal SN2, thereby applying the second power supply voltage VSS to the gate of the second driving transistor M2 to perform a reset operation on the second driving transistor M2 and the second storage capacitor Cs 2.

Fig. 5 is a circuit configuration diagram of a specific implementation example of the pixel circuit shown in fig. 3. The pixel circuit shown in fig. 5 is different from the pixel circuit shown in fig. 4 in that: the first storage capacitor Cs1 and the third switching transistor T3 are connected differently. It should be noted that other circuit structures of the pixel circuit shown in fig. 5 are substantially the same as the pixel circuit shown in fig. 4, and repeated parts are not repeated herein. Hereinafter, only differences between the pixel circuit shown in fig. 5 and the pixel circuit shown in fig. 4 will be described.

For example, in the pixel circuit shown in fig. 5, a first terminal of the first storage capacitor Cs1 is coupled to the gate of the first driving transistor M1 (i.e., the control terminal 111 of the first driving circuit 110), and a second terminal of the first storage capacitor Cs1 is coupled to the gate of the second driving transistor M2 (i.e., the control terminal 121 of the second driving circuit 120). For example, the potential of the first terminal of the first storage capacitor Cs1 may still be held at the potential of the first node P1, and the potential of the second terminal of the first storage capacitor Cs1 may be held at the potential of the second node P2. For example, in the pixel circuit shown in fig. 5, in the data writing phase, the data signal Vdata may be applied to the first node P1 (i.e., the first end of the first storage capacitor Cs 1) through the second switching transistor T2, so that the first storage capacitor Cs1 may still store the data signal Vdata, i.e., although the connection manner of the first storage capacitor Cs1 changes, the function of the first storage capacitor Cs1 for storing the data signal is not affected, and the normal operation of the pixel circuit 200 is not affected.

For example, in the pixel circuit shown in fig. 5, the gate of the third switching transistor T3 is connected to the second scan signal terminal to receive the second scan signal SN2, the first pole of the third switching transistor T3 is connected to the gate of the first driving transistor M1 (i.e., the control terminal 111 of the first driving circuit 110), and the second pole of the third switching transistor T3 is connected to the gate of the second driving transistor M2 (i.e., the control terminal 121 of the second driving circuit 120). For example, in the pixel circuit shown in fig. 5, in the reset phase, the third switching transistor T3 and the fourth switching transistor T4 may be turned on simultaneously in response to the active level (e.g., high level) of the second scan signal SN2, so that the third switching transistor T3 may apply the second power supply voltage VSS to the gate of the first driving transistor M1 through the fourth switching transistor T4 to perform the reset operation on the first driving transistor M1 and the first storage capacitor Cs1, i.e., although the connection manner of the third switching transistor T3 is changed, the third switching transistor T3 is not affected to realize its function of performing the reset operation on the first driving transistor M1 and the first storage capacitor Cs1, and thus the normal operation of the pixel circuit 200 is not affected.

It should be noted that, in the embodiment of the present disclosure, the connection modes of the first storage capacitor Cs1 (i.e., the first storage circuit 150), the third switching transistor T3 (i.e., the first reset circuit 160), the second storage capacitor Cs2 (i.e., the second storage circuit 170), and the fourth switching transistor T4 (i.e., the second reset circuit 180) include, but are not limited to, the connection modes shown in fig. 4 and 5, as long as the necessary functions of the first storage capacitor Cs1 (i.e., the first storage circuit 150), the second storage capacitor Cs2 (i.e., the second storage circuit 170), and the.

It is to be understood that, since the first switching transistor T1 forms a diode structure in the pixel circuit shown in fig. 4 and 5, the first switching transistor T1 may be replaced with a diode D0 to obtain the pixel circuit shown in fig. 6 and 7, respectively. For example, the interconnected gate and first pole of the first switching transistor T1 in the pixel circuit shown in fig. 4 and 5 may be used as the first pole (e.g., positive pole) of the diode D0, and the second pole of the first switching transistor T1 may be used as the second pole (e.g., negative pole) of the diode D0, so that the pixel circuit shown in fig. 6 and 7 can be obtained by replacing the first switching transistor T1 in the pixel circuit shown in fig. 4 and 5 with the diode D0, and connecting the first pole of the diode D0 with the first node P1 (i.e., the gate of the first driving transistor M1, i.e., the control terminal 111 of the first driving circuit 110), and connecting the second pole of the diode D0 with the second node P2 (i.e., the gate of the second driving transistor M2, i.e., the control terminal 121 of the second driving circuit 120).

It should be noted that other structures of the pixel circuit shown in fig. 6 are substantially the same as those of the pixel circuit shown in fig. 4, and other structures of the pixel circuit shown in fig. 7 are substantially the same as those of the pixel circuit shown in fig. 5, and are not repeated herein.

In the pixel circuit provided by the embodiment of the present disclosure, the first light emitting element L1 and the second light emitting element L2 are located in the same sub-pixel and have the same emission color. In comparison with a typical sub-pixel including only 1 light-emitting element L0, assuming that the area and the aperture ratio of the sub-pixel are the same, the sum of the areas of the light-emitting regions of the first light-emitting element L1 and the second light-emitting element L2 should be equal to the area of the light-emitting region of the light-emitting element L0. For example, at the time of low gray scale display, only the first light emitting element L1 emits light, and in order to make the light emission luminance of the first light emitting element L1 coincide with the light emission luminance of the light emitting element L0, since the area of the light emitting region of the first light emitting element L1 is smaller than that of the light emitting region of the light emitting element L0, the first driving transistor M1 needs to operate at a high Vgs (i.e., a voltage difference between the gate and the source); thus, even if there is fluctuation of Vgs (i.e., d (Vgs)) due to electrical noise, the influence thereof on the display screen is relatively reduced, whereby the display effect can be improved. For example, in some examples, the area of the light emitting region of the first light emitting element L1 may be smaller than that of the second light emitting element L2, so that Vgs of the first driving transistor M1 in low gray scale display may be further increased, and the influence of electrical noise on the display screen may be further reduced to further improve the display effect.

It should be noted that, in the embodiment of the present disclosure, the storage capacitors Cs1 and Cs2 may be capacitor devices fabricated by a process, for example, the capacitor devices are implemented by fabricating dedicated capacitor electrodes, each electrode of the capacitor may be implemented by a metal layer, a semiconductor layer (e.g., doped polysilicon), and the like, and the storage capacitors Cs1 and Cs2 may also be parasitic capacitors between each device, which may be implemented by the transistor itself and other devices and lines. The connection manner of the storage capacitors Cs1 and Cs2 is not limited to the above-described manner, and may be other suitable connection manners as long as the levels of the corresponding nodes can be stored.

It should be noted that, in the description of the embodiment of the present disclosure, the first node P1 and the second node P2 do not represent actually existing components, but represent a junction of related electrical connections in a circuit diagram.

It should be noted that all the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics, and all the embodiments of the present disclosure are described by taking thin film transistors as examples. The source and drain of the transistor used herein may be symmetrical in structure, so that there may be no difference in structure between the source and drain. In the embodiments of the present disclosure, in order to distinguish two poles of a transistor except for a gate, one of them is directly described as a first pole, and the other is a second pole.

In addition, the transistors in the embodiments of the present disclosure are all described by taking N-type transistors as an example, in this case, the first electrode of the transistor is a drain electrode, the second electrode is a source electrode, the first electrode of the diode is an anode electrode, and the second electrode of the diode is a cathode electrode. It is noted that the present disclosure includes but is not limited thereto. For example, one or more transistors in the pixel circuit provided in the embodiments of the present disclosure may also be P-type transistors, where the first pole of the transistor is a source, the second pole of the transistor is a drain, the first pole of the diode is a cathode, and the second pole of the diode is an anode, and it is only necessary to connect the poles of the selected type of transistor correspondingly with reference to the poles of the corresponding transistor in the embodiments of the present disclosure, and to enable the corresponding voltage terminal to provide the corresponding high voltage or low voltage. When an N-type transistor is used, Indium Gallium Zinc Oxide (IGZO) may be used as an active layer of the thin film transistor, which may effectively reduce the size of the transistor and prevent leakage current, compared to using Low Temperature Polysilicon (LTPS) or amorphous Silicon (e.g., hydrogenated amorphous Silicon) as an active layer of the thin film transistor.

In the embodiments of the present disclosure, the anode of each of the light emitting elements L1 and L2 is connected to the first power voltage VDD (high voltage) for example, but the embodiments of the present disclosure include but are not limited thereto. For example, the cathodes of the light emitting elements L1 and L2 may be connected to a second power voltage VSS (low voltage), and the anodes thereof may be directly or indirectly connected to the driving circuit, for example, refer to the 2T1C pixel circuit shown in fig. 1A.

It should be noted that, in the pixel circuit provided in the embodiment of the present disclosure, an "active level" refers to a level at which an operated transistor included therein can be turned on, and correspondingly, an "inactive level" refers to a level at which an operated transistor included therein cannot be turned on (i.e., the transistor is turned off). The active level may be higher or lower than the inactive level depending on factors such as the type (N-type or P-type) of transistors in the circuit structure of the pixel circuit. For example, in the embodiment of the present disclosure, when each transistor is an N-type transistor, the active level is a high level, and the inactive level is a low level.

At least one embodiment of the present disclosure further provides a driving method of the pixel circuit. Fig. 8 is a signal timing diagram of a driving method of a pixel circuit according to at least one embodiment of the present disclosure. A driving method of the pixel circuit 100 according to the embodiment of the present disclosure is described below with reference to a signal timing chart shown in fig. 8. It should be noted that the levels of the potentials of the signal timing chart shown in fig. 8 are only schematic and do not represent actual potential values or relative proportions, and a high level signal corresponds to an on signal of an N-type transistor and a low level signal corresponds to an off signal of the N-type transistor, corresponding to the embodiment of the present disclosure.

For example, the driving method of the pixel circuit includes: and providing a data signal for the pixel circuit, so that the first light-emitting element and the second light-emitting element jointly display a gray scale to be displayed corresponding to the data signal. A driving method of the pixel circuit shown in fig. 3 (the pixel circuit shown in fig. 3 is specifically realized as the circuit configuration shown in fig. 5) will be described in detail below.

For example, as shown in fig. 8, the driving method provided by the present embodiment may include three stages, namely, a reset stage t1, a data writing stage t2 and a light emitting stage t3, and the timing waveforms of the respective signals in each stage are shown in fig. 8.

In the reset phase t1, when the second scan signal SN2 is input, and the second scan signal SN2 is at an active level (i.e., a high level), both the first reset circuit 160 and the second reset circuit 180 are turned on, and the control terminal 111 of the first driving circuit 110 and the control terminal 121 of the second driving circuit 120 are reset by the first reset circuit 160 and the second reset circuit 180, respectively.

For example, in the pixel circuit shown in fig. 5, in the reset period T1, the third switching transistor T3 and the fourth switching transistor T4 are both turned on by the high level of the second scan signal SN 2; meanwhile, the second switching transistor T2 is turned off by the low level of the first scan signal SN 1. Since the second power supply voltage VSS supplied from the second power supply terminal ELVSS is a low voltage (e.g., may be a ground voltage or other low voltage, such as a zero voltage or a negative voltage), the first storage capacitor Cs1 may be discharged through the third switching transistor T3 (and the fourth switching transistor T4) so that the potentials of the first end of the first storage capacitor Cs1 and the gate of the first driving transistor M1 (i.e., the first node P1) become VSS, and the second storage capacitor Cs2 may be discharged through the fourth switching transistor T4 so that the potentials of the first end of the second storage capacitor Cs2 and the gate of the second driving transistor M2 (i.e., the second node P2) become VSS, that is, the gate of the first driving transistor M1 and the gate of the second driving transistor M2 are reset at the same time. At this time, the first switching transistor T1 is turned off by the second power supply voltage VSS.

In the data writing stage t2, the first scan signal SN1 is input, and at this time, the first scan signal SN1 is at a high level, the input circuit 140 is turned on, and the data signal Vdata is written into the first memory circuit 150 through the input circuit 140; meanwhile, the voltage regulating circuit 130 generates a control signal Vctrl according to the data signal Vdata, and writes the control signal Vctrl into the second memory circuit 170.

For example, in the pixel circuit shown in fig. 5, in the data writing period T2, the second switching transistor T2 is turned on by the high level of the first scan signal SN1, and both the third switching transistor T3 and the fourth switching transistor T4 are turned off by the low level of the second scan signal SN 2. The DATA signal terminal DATA charges the first terminal (i.e., the first node P1) of the first storage capacitor Cs1 through the second switching transistor T2, so that the potential of the first terminal of the first storage capacitor Cs1 becomes Vdata. Since the first switch transistor T1 is diode-connected, the first switch transistor T1 can generate the control signal Vctrl at the second node P2 according to the magnitude comparison relationship between the potential Vdata of the first node P1 (i.e., the first end of the first storage capacitor Cs 1) and the threshold voltage Vtht1 of the first switch transistor T1, and write the control signal Vctrl into the second storage capacitor Cs 2.

For example, when Vdata ≦ Vtht1, the first switching transistor T1 is turned off, and the control signal generated thereby can be considered to be Vctrl equal to 0, and at this time, the potential of the second node P2 is held at VSS, and the control signal stored in the second storage capacitor Cs2 can be considered to be VSS, for example, VSS < Vth2, and VSS equal to 0. When Vtht1< Vdata ≦ Vtht1+ Vth2, the first switching transistor T1 is turned on, and a control signal Vctrl ≦ Vdata-Vtht1 is generated, where Vctrl ≦ Vth2, at this time, the DATA signal terminal DATA charges the first terminal (i.e., the second node P2) of the second storage capacitor Cs2 through the second switching transistor T2 and the first switching transistor T1, and when the potential of the second node P2 reaches Vctrl, the first switching transistor T1 is turned off, and the charging process is ended. When Vdata > Vtht1+ Vth2, the first switching transistor T1 is turned on, and a control signal Vctrl is generated as Vdata-Vtht1, where Vctrl > Vth2, at this time, the DATA signal terminal DATA charges the first terminal (i.e., the second node P2) of the second storage capacitor Cs2 through the second switching transistor T2 and the first switching transistor T1, and when the potential of the second node P2 reaches Vctrl, the first switching transistor T1 is turned off, and the charging process is ended.

In the light emitting period t3, the first driving circuit 110 generates a first driving current according to the data signal Vdata stored in the first storage circuit 150 to make the first light emitting element 210 emit light, the second driving circuit 120 generates a second driving current (for example, the second driving current may be 0) according to the control signal Vctrl stored in the second storage circuit 170 to make the second light emitting element 220 emit light or not, and the superposition of the light emitting luminances of the first light emitting element 210 and the second light emitting element 220 meets the requirement of the gray scale to be displayed corresponding to the data signal Vdata.

For example, in the pixel circuit shown in fig. 5, the first drive current can be expressed as:

the second drive current may be expressed as:

wherein, I₁Denotes a first drive current, I₂Represents the second drive current, beta₁Represents a constant value, β, associated with the first drive circuit 110 (i.e., the first drive transistor M1)₂Which represents a constant value associated with the second driving circuit 120 (i.e., the second driving transistor M2), Vth1 represents the threshold voltage of the first driving circuit 110 (i.e., the first driving transistor M1), and Vth2 represents the threshold voltage of the second driving circuit 120 (i.e., the second driving transistor M2).

For example, in the pixel circuit shown in fig. 5, in the light emitting period T3, the second switching transistor T2 is turned off by the low level of the first scan signal SN1, and the third switching transistor T3 and the fourth switching transistor T4 are both turned off by the low level of the second scan signal SN 2. The first driving transistor M1 generates a first driving current under the control of the data signal Vdata stored in the first storage capacitor Cs1 to drive the first light emitting element L1 to emit light, the second driving transistor M2 generates a second driving current (for example, the second driving current may be 0) under the control of the control signal Vctrl stored in the second storage capacitor Cs2 to drive or not drive the second light emitting element L2 to emit light, and the superposition of the light emitting luminances of the first light emitting element L1 and the second light emitting element L2 meets the requirement of the gray scale to be displayed corresponding to the data signal Vdata.

For example, in some examples, the gray scale range of gray scales to be displayed includes a first gray scale range (e.g., a low gray scale range, such as the aforementioned [0, n ]) and a second gray scale range (e.g., a high gray scale range, such as the aforementioned (n,255]), and the level range of the data signal Vdata includes a first range and a second range.

Thus, when the gray scale to be displayed is within the first gray scale range, the data signal Vdata provided to the pixel circuit in the data writing phase should be within the first range, so that the control signal Vctrl is not less than Vth2, thereby making the first light emitting element L1 emit light (the first driving current is not 0) and the second light emitting element L2 not emit light (the second driving current is 0); at this time, the superposition of the light emitting luminances of the first light emitting element L1 and the second light emitting element L2 is the luminance of the first light emitting element L1, that is, the luminance of the first light emitting element L1 should satisfy the requirement of the gray scale to be displayed corresponding to the data signal Vdata. When the gray scale to be displayed is in the second gray scale range, the data signal Vdata provided to the pixel circuit in the data writing phase should be in the second range, so that the control signal satisfies Vctrl > Vth2, thereby making both the first light emitting element L1 and the second light emitting element L2 emit light (both the first driving current and the second driving current are not 0); at this time, the superposition of the light emitting luminances of the first light emitting element L1 and the second light emitting element L2 should satisfy the requirement of the gray scale to be displayed corresponding to the data signal Vdata.

It should be noted that the signal timing chart shown in fig. 8 is schematic, and the signal timing of the pixel circuit provided in the embodiment of the present disclosure in operation may be determined according to actual needs, which is not limited by the present disclosure. For example, in some examples, considering the influence of the voltage DROP of the data signal line (IR DROP) and the first scan signal SN1 actually provided may not be a standard square wave signal, the actually provided data signal may be Vdata _ r as shown by a dotted line in fig. 8 (for clarity, Vdata _ r shown in fig. 8 is lower than Vdata, but Vdata _ r is Vdata), the falling edge of which is located in the light emitting phase (i.e., the falling edge of the data signal Vdata _ r lags the falling edge of the first scan signal SN 1), so that the data signal written to the first end of the first storage capacitor Cs1 may be determined as Vdata at the end of the data writing phase even if there is an influence of the voltage DROP or/and the actually provided first scan signal SN1 deviating from the standard square wave signal.

It should be noted that the division of the reset phase t1, the data writing phase t2 and the light emitting phase t3 is for convenience of description, and in practical applications, there may be no clear time boundary between different phases. For example, in some examples, the first light emitting element L1 may start emitting light before the voltage of the first terminal of the first storage capacitor reaches Vdata during the data writing phase. For example, in order to avoid this situation, a light emission control circuit may be added to the pixel circuit provided in the embodiments of the present disclosure to enable the pixel circuit to have a light emission control function, which is not limited in the embodiments of the present disclosure.

For technical effects of the driving method of the pixel circuit provided by the embodiments of the present disclosure, reference may be made to corresponding descriptions about the pixel circuit in the above embodiments, and details are not repeated here.

At least one embodiment of the present disclosure also provides a display panel. Fig. 9 is a schematic view of a display panel according to at least one embodiment of the present disclosure.

For example, as shown in fig. 9, the display panel 10 includes a plurality of sub-pixels 50 arranged in an array, a plurality of scan signal lines, and a plurality of data signal lines. In fig. 9, only a part of the sub-pixels 50, the scanning signal lines, and the data signal lines are shown. For example, G _ N-1, G _ N, G _ N +1, and G _ N +2 represent scan signal lines for the (N-1) th, N +1 th, and N +2 th rows of the array, respectively, and D _ M +1 represent data signal lines for the (M) th and (M +1) th columns of the array, respectively. Here, N is, for example, an integer greater than 1, and M is, for example, an integer greater than 1.

For example, each sub-pixel 50 includes a pixel circuit provided by any of the above embodiments of the present disclosure, such as the pixel circuit 100 shown in fig. 2 or fig. 3, but is not limited thereto.

For example, the input circuit 140 in the pixel circuit 100 of each row is connected to the scan signal line of the present row to receive the first scan signal SN 1; the first reset circuit 160 and the second reset circuit 180 in the pixel circuit 100 of each row are connected to the scan signal line of the previous row to receive the second scan signal SN 2. For another example, for the first reset circuit 160 and the second reset circuit 180 in the pixel circuit 100 of the first row, there may be one additional scan signal line for which the second scan signal SN2 is supplied.

For example, one data signal line corresponds to each column of sub-pixels, and for example, the input circuit 140 in the pixel circuit 100 of each column of sub-pixels is connected to the corresponding data signal line, so that the input circuit 140 in each pixel circuit 100 can receive the data signal Vdata from the data signal line connected thereto.

For technical effects of the display panel 10 provided by at least one embodiment of the present disclosure, reference may be made to corresponding descriptions about the pixel circuit in the above embodiments, and details are not repeated here.

At least one embodiment of the present disclosure also provides a display device. Fig. 10 is a schematic view of a display device according to at least one embodiment of the present disclosure. For example, as shown in fig. 10, the display device 1 may include the display panel 10 provided in any of the above embodiments of the present disclosure, and may further include a scan driving circuit 20 and a data driving circuit 30.

For example, the scan driving circuit 20 may be connected to a plurality of scan signal lines GL (i.e., G _ N-1, G _ N, G _ N +1, G _ N +2, etc.) to provide scan signals (e.g., a first scan signal SN1, a second scan signal SN 2). It should be noted that the first scan signal SN1 and the second scan signal SN2 are relative, and for example, the first scan signal SN1 of a certain row of the pixel circuits 100 may be the second scan signal SN2 of a next row of the pixel circuits 100. For example, the scan driving circuit 20 may be implemented by a bonded integrated circuit driving chip, or the scan driving circuit 20 may be directly integrated On the display panel to form a goa (gate driver On array).

For example, the data driving circuit 30 may be connected to a plurality of data signal lines DL (i.e., D _ M, D _ M +1, etc.) to provide the data signal Vdata. For example, the data driving circuit 30 may be implemented by a bonded integrated circuit driving chip.

The display device 1 may further include other components, such as a timing controller, a signal decoding circuit, a voltage conversion circuit, etc., and these components may adopt conventional components or structures, for example, and are not described herein again.

For example, the display device 1 in the present embodiment may be: the display, the television, the mobile phone, the tablet computer, the notebook computer, the digital photo frame, the navigator and other products or components with the display function. It should be noted that the display device 1 may further include other conventional components or structures, for example, in order to implement the necessary functions of the display device, a person skilled in the art may set other conventional components or structures according to a specific application scenario, and the embodiment of the disclosure is not limited thereto.

For technical effects of the display device provided by at least one embodiment of the present disclosure, reference may be made to corresponding descriptions about the pixel circuit in the above embodiments, and details are not repeated here.

For the present disclosure, there are the following points to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design.

(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only exemplary of the present disclosure and is not intended to limit the scope of the present disclosure, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present disclosure and shall be covered by the scope of the present disclosure. Accordingly, the scope of the disclosure is to be determined by the claims that follow.

Claims

1. A pixel circuit includes a first driving circuit, a second driving circuit, and a voltage adjusting circuit,

the first driving circuit is configured to generate a first driving current for driving the first light emitting element to emit light according to a data signal,

the second driving circuit is configured to generate a second driving current for driving the second light emitting element to emit light according to a control signal derived from the data signal and different from the data signal,

the voltage regulation circuit is configured to generate the control signal based on the data signal, wherein,

the voltage regulating circuit comprises a first switching transistor, a grid electrode and a first electrode of the first switching transistor are both connected with the control end of the first driving circuit, and a second electrode of the first switching transistor is connected with the control end of the second driving circuit to form a diode structure; alternatively, the first and second electrodes may be,

the voltage regulating circuit comprises a diode, a first pole of the diode is connected with the control end of the first driving circuit, and a second pole of the diode is connected with the control end of the second driving circuit.

2. The pixel circuit according to claim 1, further comprising the first light emitting element, wherein,

a first electrode of the first light emitting element is connected to a first power supply terminal to receive a first power supply voltage,

the first drive circuit comprises a first drive transistor,

the gate of the first driving transistor is used as a control terminal of the first driving circuit, the first pole of the first driving transistor is connected with the second pole of the first light-emitting element, and the second pole of the first driving transistor is connected with the second power supply terminal to receive the second power supply voltage.

3. The pixel circuit according to claim 2, further comprising the second light emitting element, wherein,

a first electrode of the second light emitting element is connected to the first power source terminal to receive the first power source voltage,

the second drive circuit comprises a second drive transistor,

a gate of the second driving transistor is used as a control terminal of the second driving circuit, a first pole of the second driving transistor is connected with a second pole of the second light emitting element, and the second pole of the second driving transistor is connected with the second power supply terminal to receive the second power supply voltage.

4. The pixel circuit of claim 1, further comprising an input circuit, wherein,

the input circuit is configured to apply the data signal to a control terminal of the first driving circuit in response to a first scan signal.

5. The pixel circuit of claim 4, wherein the input circuit comprises a second switching transistor,

the gate of the second switching transistor is connected to the first scan signal terminal to receive the first scan signal, the first pole of the second switching transistor is connected to the data signal terminal to receive the data signal, and the second pole of the first switching transistor is connected to the control terminal of the first driving circuit.

6. The pixel circuit according to claim 1, further comprising a first storage circuit and a first reset circuit, wherein,

the first storage circuit is configured to store the data signal,

the first reset circuit is configured to reset a control terminal of the first driving circuit in response to a second scan signal.

7. The pixel circuit according to claim 6, wherein the first storage circuit includes a first storage capacitor, the first reset circuit includes a third switching transistor,

a first terminal of the first storage capacitor is coupled to the control terminal of the first driving circuit, a second terminal of the first storage capacitor is coupled to the control terminal of the second driving circuit, a gate of the third switching transistor is connected to the second scan signal terminal to receive the second scan signal, a first terminal of the third switching transistor is connected to the control terminal of the first driving circuit, and a second terminal of the third switching transistor is connected to the control terminal of the second driving circuit; alternatively, the first and second electrodes may be,

the first terminal of the first storage capacitor is coupled to the control terminal of the first driving circuit, the second terminal of the first storage capacitor is connected to the second power terminal, the gate of the third switching transistor is connected to the second scan signal terminal to receive the second scan signal, the first terminal of the third switching transistor is connected to the control terminal of the first driving circuit, and the second terminal of the third switching transistor is connected to the second power terminal.

8. The pixel circuit according to claim 1, further comprising a second storage circuit and a second reset circuit, wherein,

the second storage circuit is configured to store the control signal,

the second reset circuit is configured to reset the control terminal of the second driving circuit in response to a second scan signal.

9. The pixel circuit according to claim 8, wherein the second storage circuit comprises a second storage capacitor, the second reset circuit comprises a fourth switching transistor,

the first end of the second storage capacitor is coupled with the control end of the second driving circuit, the second end of the second storage capacitor is connected with a second power supply end,

the grid electrode of the fourth switching transistor is connected with the second scanning signal end to receive the second scanning signal, the first electrode of the fourth switching transistor is connected with the control end of the second driving circuit, and the second electrode of the fourth switching transistor is connected with the second power supply end.

10. The pixel circuit of claim 1, wherein the range of levels of the data signal includes a first range and a second range,

the first driving current is greater than zero, the second driving current is equal to zero when the level of the data signal is in the first range,

when the level of the data signal is in the second range, the first driving current and the second driving current are both greater than zero.

11. The pixel circuit according to claim 10, wherein the first light-emitting element and the second light-emitting element emit light of the same color, and an area of a light-emitting region of the first light-emitting element is smaller than an area of a light-emitting region of the second light-emitting element.

12. A display panel includes a plurality of sub-pixels arranged in an array, wherein,

each of the sub-pixels comprising a pixel circuit according to any one of claims 1-11.

13. A display device comprising the display panel according to claim 12.

14. A driving method of the pixel circuit according to claim 1, comprising:

and providing the data signal for the pixel circuit, so that the first light-emitting element and the second light-emitting element jointly display the gray scale to be displayed corresponding to the data signal.

15. The driving method according to claim 14,

the gray scale range of the gray scale to be displayed comprises a first gray scale range and a second gray scale range, and the level range of the data signal comprises a first range and a second range;

when the gray scale to be displayed is in the first gray scale range, providing the data signal in the first range for the pixel circuit, so that the first light-emitting element emits light and the second light-emitting element does not emit light;

and when the gray scale to be displayed is in the second gray scale range, providing the data signal in the second range for the pixel circuit, so that the first light-emitting element and the second light-emitting element emit light.