CN110212873B - Low-noise high-input impedance amplifier applied to wearable dry electrode electrocardiograph monitoring - Google Patents
Low-noise high-input impedance amplifier applied to wearable dry electrode electrocardiograph monitoring Download PDFInfo
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Abstract
The invention discloses a low-noise high-input impedance amplifier applied to wearable dry electrode electrocardiograph monitoring. The amplifier circuit adopts a novel chopper stabilization technology to reduce the flicker noise of the circuit, and can effectively amplify the ultralow-frequency electrocardiosignal; meanwhile, a sampling input structure is adopted, so that the input impedance of an amplifier is not reduced while a chopper stabilization technology is used, an electrocardiosignal can be effectively obtained from a high-resistance dry electrode, and the application of wearable dry electrode electrocardiosignal detection is facilitated; the electrode imbalance suppression circuit adopting digital-analog mixed regulation provides the electrode imbalance suppression capability of +/-300 mV without increasing the noise of the overall circuit; the rapid recovery circuit is adopted, so that the recovery time of the electrode imbalance inhibition loop is prolonged, the application of all-weather continuous electrocardiograph detection is facilitated, and a good solution is provided for the Internet of things and medical treatment.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a low-noise high-input impedance amplifier applied to wearable dry electrode electrocardiograph monitoring.
Background
With the development of society and the advancement of technology, health problems have become a focus of attention. According to WHO statistics, the number of people dying from non-infectious diseases per year is about 4100 ten thousand, and the proportion of people dying from cardiovascular diseases exceeds 50%. At the same time WHO predicts that in 2020, the number of people worldwide WHO die from cardiovascular disease will be as high as 2600 tens of thousands. The conventional clinical electrocardiogram detection can only judge myocardial ischemia, arrhythmia, premature beat and other diseases, and can not prevent sudden heart disease. With the formation of novel technologies such as the Internet of things and the cloud platform, a brand new pattern of 'Internet of things + medical treatment' is generated. The wearable continuous electrocardiograph detection combined with the Internet of things+ can monitor electrocardiograph signals of a human body all-weather, and analyze the electrocardiograph signals in real time through the cloud, so that the death rate of sudden heart diseases can be greatly reduced.
Because the traditional clinical electrocardiogram adopts wet electrodes with lower internal resistance and smaller electrode imbalance, the input impedance of an electrocardio amplifier and the electrode imbalance inhibition capability are not required to be high. However, the wet electrode can cause skin itch, eczema and other problems after being worn for a long time, so that the wet electrode can not be directly applied to wearable electrocardiograph detection. The dry electrode does not require skin preparation and application of a conductive paste as compared to the wet electrode, and is therefore theoretically more suitable for use in wearable electrocardiographic devices that require long-term wear. However, in view of the fact that the dry electrode has a large output impedance (1 mΩ to 100mΩ) and an electrode offset (±300 mV), the input impedance of the conventional electrocardiograph amplifier is difficult to be well matched with the impedance of the dry electrode, and the output of the conventional electrocardiograph amplifier is easily saturated under the condition that the dry electrode is large, so that the dry electrode cannot be normally applied to the wearable device. For this reason, improvements are needed to conventional electrocardiographs.
Disclosure of Invention
The invention aims to solve the problem that the traditional electrocardio amplifier cannot be matched with a dry electrode with high output impedance and high electrode imbalance in wearable electrocardio detection equipment for use, and provides a low-noise high-input impedance amplifier applied to wearable dry electrode electrocardio monitoring.
In order to solve the problems, the invention is realized by the following technical scheme:
be applied to wearable dry electrode electrocardioThe monitored low noise high input impedance amplifier includes a chopper amplifier, a ripple suppression loop, and a gain control loop. The input end of the ripple suppression loop is connected with the output end of the chopper amplifier, and the output end of the ripple suppression loop is connected with the output end of the first-stage transconductance amplifier in the chopper amplifier. The input end of the gain control loop is connected with the output end of the chopper amplifier, and the output end of the ripple suppression loop is connected with the output end of the first-stage transconductance amplifier in the chopper amplifier. The circuit is characterized by further comprising a sampling input stage circuit, an analog electrode imbalance suppression loop and a digital electrode imbalance suppression circuit. Input terminal V of sampling input stage circuit inn And V inp Forming the input end of the low-noise high-input impedance electrocardio amplifier. Output terminal V of sampling input stage circuit ampn And V ampp Is connected with the input end of the chopper amplifier. The output end of the chopper amplifier is the output end of the low-noise high-input-impedance electrocardio amplifier. The analog electrode misalignment suppression loop includes a low pass filter and an attenuator. A set of inputs of the low pass filter form inputs of the analog electrode imbalance suppression loop and are connected to the output of the chopper amplifier. The output of the low pass filter is connected to the input of the attenuator. The output end of the attenuator is connected with the input end V of the sampling input stage circuit ADSLn And V ADSLp . The input end of the digital electrode imbalance suppression circuit is connected with the output end of the low-pass filter of the analog electrode imbalance suppression loop, and the output end of the digital electrode imbalance suppression circuit is connected with the input end V of the sampling input stage circuit DDSLn And V DDSLp . The sampling input stage circuit performs sampling and preprocessing of an external input signal, and removes electrode mismatch and baseline wander interference in the input signal before the input signal enters the chopper amplifier without reducing the input impedance of the circuit. The analog electrode imbalance suppression loop firstly utilizes a low-pass filter to carry out low-pass filtering on the output signal of the chopper amplifier to take out electrode imbalance and baseline drift interference, and outputs an analog feedback signal after amplification, and then utilizes an attenuator to attenuate the analog feedback signal and send the attenuated analog feedback signal into the sampling input stage circuit so as to offset the electrode imbalance and the baseline drift interference of an external input signal. Digital electrode imbalance suppression circuit detectionThe voltage of the analog feedback signal output by the active low-pass filter of the analog electrode imbalance suppression loop is measured, and a digital compensation signal is generated according to the voltage and is sent to the sampling input stage circuit so as to prevent the output of the low-pass filter from being saturated.
In the above scheme, the sampling input stage circuit includes 16 NMOS transistors K 11 ～K 18 、K 21 ～K 28 And 4 sampling capacitances C in1 ～C in4 . NMOS tube K 11 ～K 18 The grid electrode of the NMOS transistor K is connected with a clock signal phi 1 21 ～K 28 Is connected to the clock signal phi 2. The clock signal phi 1 and the clock signal phi 2 are a set of non-overlapping clocks. Capacitor C in1 One end of (2) is connected with NMOS tube K 11 And K 21 Is connected with the source electrode of the capacitor C in1 The other end of (2) is connected with NMOS tube K 12 And K 22 Is connected to the drain of the transistor. Capacitor C in2 One end of (2) is connected with NMOS tube K 13 And K 23 Is connected with the source electrode of the capacitor C in2 The other end of (2) is connected with NMOS tube K 14 And K 24 Is connected to the drain of the transistor. Capacitor C in3 One end of (2) is connected with NMOS tube K 15 And K 25 Is connected with the source electrode of the capacitor C in3 The other end of (2) is connected with NMOS tube K 16 And K 26 Is connected to the drain of the transistor. Capacitor C in4 One end of (2) is connected with NMOS tube K 17 And K 27 Is connected with the source electrode of the capacitor C in4 The other end of (2) is connected with NMOS tube K 18 And K 28 Is connected to the drain of the transistor. NMOS tube K 11 And K 25 Form the input terminal V of the sampling input stage circuit inn . NMOS tube K 13 And K 27 Form the input terminal V of the sampling input stage circuit inp . NMOS tube K 15 And K 21 The drain of which forms the output V of the sampling input stage circuit ampn . NMOS tube K 17 And K 23 The drain of which forms the output V of the sampling input stage circuit ampp . NMOS tube K 16 And K 22 Form the input V of the sampling input stage circuit ADSLn . NMOS tube K 18 And K 24 Form the input V of the sampling input stage circuit ADSLp . NMOS tube K 12 And K 26 Source electrode formation of (1)Input terminal V of sample input stage circuit DDSLn . NMOS tube K 14 And K 28 Form the input V of the sampling input stage circuit DDSLp 。
In the above scheme, the low-pass filter of the analog electrode imbalance suppression loop comprises a hysteresis comparator I 1 、I 2 NAND gate I 3 PMOS tube M 1 –M 3 NMOS tube M 4 Amplifier A 3 And a capacitor C 61 、C 62 . Hysteresis comparator I 1 And hysteresis comparator I 2 Form a set of inputs of a low pass filter. Hysteresis comparator I 1 And hysteresis comparator I 2 The non-inverting input terminal of (2) is connected with the reference voltage V ref . Hysteresis comparator I 1 And hysteresis comparator I 2 The output ends of (a) are respectively connected with the NAND gate I 3 Is provided, 2 inputs of (c) are provided. NOT gate I 3 The output end of (a) is connected with the NMOS tube M at the same time 3 And PMOS tube M 4 Is formed on the substrate. NMOS tube M 4 Is connected with a reference voltage V b . PMOS tube M 3 The source electrode of the transistor is connected with a power supply. NMOS tube M 3 And PMOS tube M 4 Is connected with the drain electrode of the PMOS tube M 1 And PMOS tube M 2 Is connected to the gate of the transistor. PMOS tube M 1 Drain and hysteresis comparator I 2 Is connected with the inverting input end of the PMOS tube M 1 Source connection amplifier a of (2) 3 Is provided. PMOS tube M 2 Drain and hysteresis comparator I 1 Is connected with the inverting input end of the PMOS tube M 2 Source connection amplifier a of (2) 3 Is provided. Capacitor C 61 Is connected with the amplifier A at two ends respectively 3 An inverting input terminal and an inverting output terminal. Capacitor C 62 Is connected with the amplifier A at two ends respectively 3 A non-inverting input terminal and an inverting output terminal of (a). Amplifier A 3 The in-phase output and the anti-phase output of (c) form a set of outputs of the low-pass filter.
In the scheme, the attenuator of the analog electrode imbalance suppression loop comprises chopper choppers chopping1 and chopping2 and a capacitor C 71 、C 72 、C 81 、C 82 . Attenuation is formed at 2 input ends of chopper chopping1A set of inputs of the device. One output end of chopper capacitor C 71 Capacitance C 71 The other end of (2) is divided into 2 paths, one path is connected with the capacitor C 81 And the other path is connected with one input end of the chopper 2. The other output end of chopper chopping1 is connected with capacitor C 72 Capacitance C 72 The other end of (2) is divided into 2 paths, one path is connected with the capacitor C 82 And the other path is connected with the other input end of the chopper 2. The 2 outputs of chopper chopping2 form a set of outputs of the attenuator.
In the above scheme, the digital electrode imbalance suppression circuit includes a comparator U 1 、U 2 Shift register, constant current source I 1 Resistance R 1 ～R 3 NMOS tube M 11 ～M 14 、M 21 ～M 24 、M 5 And a reset module Rest. Comparator U 1 Sum comparator U 2 Is provided with a group of input ends of the digital electrode imbalance suppression circuit. Comparator U 1 Sum comparator U 2 The inverting input terminal of (C) is simultaneously connected with the reference voltage VCM. Comparator U 1 An output end of the (B) is connected with a rising input end up of the Shift register (Shift), and a comparator U 2 The output end of the (a) is connected with the falling input end down of the Shift register Shift. The clock of the Shift register Shift is terminated by an external clock signal. The reset end Rest of the Shift register Shift is connected with the output end of the reset module Rest. A first group of four-bit output terminals A of the shift register<4:1>Is divided into 2 paths, one path is sent to a reset module Rest, and the other path is respectively connected with an NMOS tube M 21 ～M 24 Is formed on the substrate. Second group of four-bit output terminals B of shift register<4:1>Is divided into 2 paths, one path is sent to a reset module Rest, and the other path is respectively connected with an NMOS tube M 11 ～M 14 Is formed on the substrate. Current source I 1 Is connected with a power supply and a current source I 1 Is connected with the NMOS tube M 14 And NMOS tube M 24 Source of (d), and resistor R 1 Is provided. Resistor R 1 NMOS tube M at the other end of (2) 13 And NMOS tube M 23 Source of (d), and resistor R 2 Is provided. Resistor R 2 NMOS tube M at the other end of (2) 12 And NMOS tube M 22 Source of (d), and resistor R 3 Is provided. Resistor R 3 NMOS tube M at the other end of (2) 11 And NMOS tube M 12 Source electrode of (d), and NMOS transistor M 5 A gate and a drain of (a). NMOS tube M 5 The drain of (2) is grounded. NMOS tube M 11 ～M 14 After the drains of the digital electrode imbalance suppression circuits are connected, one of a group of output ends of the digital electrode imbalance suppression circuit is formed, and an NMOS tube M 21 ～M 24 After the drains of the digital electrode imbalance suppression circuits are connected, another one of a set of output terminals of the digital electrode imbalance suppression circuits is formed.
Compared with the prior art, the invention has the following characteristics:
1. the digital and analog mixed electrode imbalance suppression circuit is adopted, so that the amplifier can suppress electrode imbalance of up to +/-300 mV, and the input impedance of the amplifier is not reduced; the noise introduced by the electrode imbalance inhibition loop is greatly reduced;
2. the novel capacitance sampling input structure is adopted, so that the low-frequency equivalent input impedance of the amplifier is more than 1G omega without using positive feedback and an auxiliary amplifier, and no extra noise is introduced.
Drawings
Fig. 1 is a schematic diagram of a low noise high input impedance amplifier for use in wearable dry electrode electrocardiograph monitoring.
Fig. 2 is a schematic diagram of a sampling input stage circuit.
Fig. 3 is a schematic diagram of a low pass filter.
Fig. 4 is a schematic diagram of an attenuator.
Fig. 5 is a schematic diagram of a digital electrode imbalance suppression circuit.
Fig. 6 is a shift register workflow diagram.
Fig. 7 is a graph of periodic steady state alternating current (PAC) simulation results of fig. 1.
Fig. 8 is a graph of the periodic steady state noise (PNOISE) simulation results of fig. 1.
Fig. 9 is a graph of simulation results of the relationship between the input equivalent impedance and the input frequency of fig. 1.
Fig. 10 is a diagram of the time domain simulation result of fig. 1.
Detailed Description
The present invention will be further described in detail with reference to specific examples in order to make the objects, technical solutions and advantages of the present invention more apparent.
Referring to fig. 1, a low-noise high-input impedance amplifier applied to wearable dry electrode electrocardiograph monitoring mainly comprises a sampling input stage circuit, a chopper amplifier, a ripple suppression loop, a gain control loop, an analog electrode imbalance suppression loop and a digital electrode imbalance suppression circuit. The sampling input stage circuit comprises 3 groups of input ends, and a group of input ends V inn 、V inp Form the input end of the whole low-noise high-input impedance electrocardio amplifier and the other group of input ends V ADSLn 、V ADSLp The output end of the analog electrode disturbance suppression loop is connected with the input end V of the other group DDSLn 、V DDSLp The output end of the digital electrode imbalance suppression circuit is connected. Output terminal V of sampling input stage circuit ampn 、V ampp The input end of the chopper amplifier is connected. Output terminal V of chopper amplifier outn 、V outp Forming the output end of the whole low-noise high-input impedance electrocardio amplifier. The input end of the ripple suppression loop is connected with the output end V of the chopper amplifier outn 、V outp The method comprises the steps of carrying out a first treatment on the surface of the The output end of the ripple suppression loop is connected with the transconductance amplifier G inside the chopper amplifier m1 Is provided. The input end of the gain control loop is connected with the output end V of the chopper amplifier outn 、V outp The method comprises the steps of carrying out a first treatment on the surface of the An output end of the gain control loop is connected with a transconductance amplifier G inside the chopper amplifier m1 Is provided. The input end of the analog electrode maladjustment suppression loop is connected with the output end V of the chopper amplifier outn 、V outp . The output end of the analog electrode imbalance suppression loop is connected with the input end V of the sampling input stage circuit ADSLn 、V ADSLp . The input end of the digital electrode imbalance suppression circuit is connected with the output ends TESTn and TESTp of the low-pass filter in the analog electrode imbalance suppression loop; the output end of the digital electrode imbalance suppression circuit is connected with the input end V of the sampling input stage circuit DDSLp 、V DDSLn 。
The sampling input stage circuit, as shown in FIG. 2, comprises 16 switches K 11 ～K 18 、K 21 ～K 28 4 sampling capacitors C in1 ～C in4 . Since the source and drain of the NMOS in the integrated chip are symmetrical, a more ideal switch can be constructed, so in the preferred embodiment of the invention, 16 switches K 11 ～K 18 、K 21 ～K 28 Are each made of NMOS. Wherein 16 switches of the sampling input stage circuit are respectively controlled by a group of non-overlapping clocks phi 1 and phi 2, and the clock signal phi 1 controls the switch K 11 ～K 18 Clock signal phi 2 controls switch K 21 ～K 28 . NMOS tube K 11 ～K 18 The grid electrode of the NMOS transistor K is connected with a clock signal phi 1 21 ～K 28 The grid of which is connected with a clock signal phi 2; the clock signal phi 1 and the clock signal phi 2 are a set of non-overlapping clocks. Capacitor C in1 One end of (2) is connected with NMOS tube K 11 And K 21 Is connected with the source electrode of the capacitor C in1 The other end of (2) is connected with NMOS tube K 12 And K 22 Is connected with the drain electrode of the transistor; capacitor C in2 One end of (2) is connected with NMOS tube K 13 And K 23 Is connected with the source electrode of the capacitor C in2 The other end of (2) is connected with NMOS tube K 14 And K 24 Is connected with the drain electrode of the transistor; capacitor C in3 One end of (2) is connected with NMOS tube K 15 And K 25 Is connected with the source electrode of the capacitor C in3 The other end of (2) is connected with NMOS tube K 16 And K 26 Is connected with the drain electrode of the transistor; capacitor C in4 One end of (2) is connected with NMOS tube K 17 And K 27 Is connected with the source electrode of the capacitor C in4 The other end of (2) is connected with NMOS tube K 18 And K 28 Is connected to the drain of the transistor. NMOS tube K 11 And K 25 Form the input terminal V of the sampling input stage circuit inn The method comprises the steps of carrying out a first treatment on the surface of the NMOS tube K 13 And K 27 Form the input terminal V of the sampling input stage circuit inp The method comprises the steps of carrying out a first treatment on the surface of the NMOS tube K 15 And K 21 The drain of which forms the output V of the sampling input stage circuit ampn The method comprises the steps of carrying out a first treatment on the surface of the NMOS tube K 17 And K 23 The drain of which forms the output V of the sampling input stage circuit ampp The method comprises the steps of carrying out a first treatment on the surface of the NMOS tube K 16 And K 22 Form the input V of the sampling input stage circuit ADSLn The method comprises the steps of carrying out a first treatment on the surface of the NMOS tube K 18 And K 24 Form the sampling input by the source of (a)Input terminal V of stage circuit ADSLp The method comprises the steps of carrying out a first treatment on the surface of the NMOS tube K 12 And K 26 Form the input V of the sampling input stage circuit DDSLn The method comprises the steps of carrying out a first treatment on the surface of the NMOS tube K 14 And K 28 Form the input V of the sampling input stage circuit DDSLp 。
Chopper amplifier comprising chopper MX1, MX2, transconductance amplifier G m1 、G m4 And by amplifier A 1 And capacitor C 31 、C 32 An integrator is formed. The 2 inputs of chopper MX1 form a set of inputs V of the chopper amplifier ampn 、V ampp . 2 output ends of chopper MX1 are respectively connected with transconductance amplifier G m1 Is the same as or different from the input terminal of the transconductance amplifier G m1 The in-phase and the anti-phase output terminals of (a) are respectively connected with the transconductance amplifier G m4 Is provided, the inverting and non-inverting inputs of (a) are provided. Transconductance amplifier G m4 Is respectively connected with 2 input ends of the chopper MX2 in the same phase and in opposite phase, and 2 output ends of the chopper MX2 are respectively connected with the amplifier A 1 Is provided, the non-inverting and inverting inputs of (a) are provided. Capacitor C 31 Is connected with the amplifier A at two ends respectively 1 An inverting output and a non-inverting input. Capacitor C 32 Is connected with the amplifier A at two ends respectively 1 In-phase and anti-phase inputs of (a). Amplifier A 1 Is formed into a set of output terminals V of a chopper amplifier outn 、V outp . Input terminal V of chopper amplifier ampp And V ampn An output end of the sampling input stage circuit is connected with an input end V ampp And V ampn Differential input signal V amp Modulated to chopping frequency by chopper MX1 and then passed through transconductance amplifier G m1 、G m4 Amplifying, demodulating to baseband by chopper MX2, and passing through C 31 、C 32 、A 1 The integrator is constructed to filter the amplified output.
Gain control loop including capacitor C 11 、C 12 、C 21 、C 22 Transconductance amplifier G m2 . Capacitor C 11 One end of (2) is connected with the output end V of the chopper amplifier outn The other end is divided into two paths, one path is connected with electricityCapacitor C 21 Connected to ground, the other way is connected to a transconductance amplifier G m2 Is provided. Capacitor C 12 One end of (2) is connected with the output end V of the chopper amplifier outp The other end is divided into two paths, one path passes through the capacitor C 22 Connected to ground, the other way is connected to a transconductance amplifier G m2 Is provided. Transconductance amplifier G m2 The in-phase output end and the anti-phase output end of the (a) are respectively connected with the transconductance amplifier G of the chopper amplifier m1 In-phase and anti-phase outputs of (a) are provided. Through capacitor C 11 、C 12 、C 21 、C 22 For output voltage V outn 、V outp Dividing the voltage to output the voltage C 11 /(C 11 +C 21 ) The voltage of multiple magnitude is fed back to the transconductance amplifier G m2 If G m2 And G m1 Is equal, the gain of the amplifier can be controlled to be C 21 /C 11 +1。
Ripple suppression loop comprising capacitor C 41 、C 42 Chopper MX3, formed by capacitor C 51 、C 52 And amplifier A 2 Integrator, transconductance amplifier G m3 . Output terminals V of chopper amplifier outp 、V outn Respectively via the capacitor C 41 、C 42 2 inputs of chopper MX3 are connected. The 2 output ends of the chopper MX3 are respectively connected with the amplifier A 2 In-phase and anti-phase inputs of (a). Amplifier A 2 Is connected with the transconductance amplifier G m3 An inverting input and a non-inverting input. Capacitor C 51 Is connected with the amplifier A at two ends respectively 2 In-phase and anti-phase inputs of (a). Capacitor C 52 Is connected with the amplifier A at two ends respectively 2 An inverting output and a non-inverting input. Transconductance amplifier G m3 Is connected with a mid-span guide amplifier G of the chopper amplifier through the in-phase output end and the anti-phase output end m1 In-phase and anti-phase outputs of (a) are provided. The input end of the ripple suppression loop is connected with the output end V of the chopper amplifier outn 、V outp The output end of the ripple suppression loop is connected with the feedback node of the chopper amplifier, namely the transconductance amplifier G m4 Is provided. Due to the transconductance amplifier G m1 、G m4 Is modulated by chopper MX2 into a square wave at the chopping frequency and then passed through the amplifier a 1 And capacitor C 31 、C 32 The integrator is formed to form triangular wave with chopping frequency, and to eliminate the triangular wave, the ripple suppressing loop first makes V out The triangular wave voltage is subjected to capacitance differentiation to form square wave current with chopping frequency, then the square wave current is demodulated into direct current through a chopper MX3, and the direct current is processed through A 2 、C 51 、C 52 The integrator forms a DC voltage which is fed back to G through a transconductance amplifier m4 Offset G m1 And G m4 Is used for the detuning and low frequency noise.
The analog electrode imbalance suppression loop includes a low pass filter LPF1 and an attenuator.
The low pass filter, as shown in FIG. 3, comprises a hysteresis comparator I 1 、I 2 NAND gate I 3 PMOS tube M 3 And NMOS tube M 4 The rapid recovery circuit consists of a PMOS tube M 1 And M 2 Composed pseudo-resistor P-RES, amplifier A 3 And a capacitor C 61 、C 62 . Hysteresis comparator I 1 And hysteresis comparator I 2 Form a set of inputs of a low pass filter. Hysteresis comparator I 1 And hysteresis comparator I 2 The non-inverting input terminal of (2) is connected with the reference voltage V ref . Hysteresis comparator I 1 And hysteresis comparator I 2 The output ends of (a) are respectively connected with the NAND gate I 3 Is provided, 2 inputs of (c) are provided. NAND gate I 3 The output end of (a) is connected with the NMOS tube M at the same time 3 And PMOS tube M 4 Is formed on the substrate. NMOS tube M 4 Is connected with a reference voltage V b . PMOS tube M 3 The source electrode of the transistor is connected with a power supply. NMOS tube M 3 And PMOS tube M 4 Is connected with the drain electrode of the PMOS tube M 1 And PMOS tube M 2 Is connected to the gate of the transistor. PMOS tube M 1 Drain and hysteresis comparator I 2 Is connected with the inverting input end of the PMOS tube M 1 Source connection amplifier a of (2) 3 Is provided. PMOS tube M 2 Drain and hysteresis comparator I 1 Is connected with the inverting input end of the PMOS tube M 2 Source connection amplifier a of (2) 3 Is provided. Capacitor C 61 Is connected with the amplifier A at two ends respectively 3 An inverting input terminal and an inverting output terminal. Capacitor C 62 Is connected with the amplifier A at two ends respectively 3 A non-inverting input terminal and an inverting output terminal of (a). Amplifier A 3 The in-phase output and the anti-phase output of (c) form a set of outputs of the low-pass filter.
The attenuator, as shown in FIG. 4, comprises chopper choppers chopping1, chopping2, and capacitor C 71 、C 72 、C 81 、C 82 . The 2 inputs of chopper chopping1 form a set of inputs of the attenuator. One output end of chopper capacitor C 71 Capacitance C 71 The other end is divided into 2 paths, one path passes through a capacitor C 81 And the other path is connected with one input end of the chopper 2. The other output end of chopper chopping1 is connected with capacitor C 72 Capacitance C 72 The other end is divided into 2 paths, one path passes through a capacitor C 82 And the other path is connected with the other input end of the chopper 2. The 2 outputs of chopper chopping2 form a set of outputs of the attenuator.
The digital electrode imbalance suppression circuit, as shown in FIG. 5, includes a comparator U 1 、U 2 Shift register, constant current source I 1 Resistance R 1 ～R 3 NMOS tube M 11 ～M 14 、M 21 ～M 24 、M 5 And a reset module Rest. Comparator U 1 Sum comparator U 2 Is provided with a group of input ends of the digital electrode imbalance suppression circuit. Comparator U 1 Sum comparator U 2 The inverting input terminal of (C) is simultaneously connected with the reference voltage VCM. Comparator U 1 An output end of the (B) is connected with a rising input end up of the Shift register (Shift), and a comparator U 2 The output end of the (a) is connected with the falling input end down of the Shift register Shift. The clock of the Shift register Shift is terminated by an external clock signal. The reset end Rest of the Shift register Shift is connected with the output end of the reset module Rest. Of shift registersA first group of four-bit output terminals A<4:1>Is divided into 2 paths, one path is sent to a reset module Rest, and the other path is respectively connected with an NMOS tube M 21 ～M 24 Is formed on the substrate. Second group of four-bit output terminals B of shift register<4:1>Is divided into 2 paths, one path is sent to a reset module Rest, and the other path is respectively connected with an NMOS tube M 11 ～M 14 Is formed on the substrate. Current source I 1 Is connected with a power supply and a current source I 1 Is connected with the NMOS tube M 14 And NMOS tube M 24 Source of (d), and resistor R 1 Is provided. Resistor R 1 NMOS tube M at the other end of (2) 13 And NMOS tube M 23 Source of (d), and resistor R 2 Is provided. Resistor R 2 NMOS tube M at the other end of (2) 12 And NMOS tube M 22 Source of (d), and resistor R 3 Is provided. Resistor R 3 NMOS tube M at the other end of (2) 11 And NMOS tube M 12 Source electrode of (d), and NMOS transistor M 5 A gate and a drain of (a). NMOS tube M 5 The drain of (2) is grounded. NMOS tube M 11 ～M 14 After the drains of the digital electrode imbalance suppression circuits are connected, one of a group of output ends of the digital electrode imbalance suppression circuit is formed, and an NMOS tube M 21 ～M 24 After the drains of the digital electrode imbalance suppression circuits are connected, another one of a set of output terminals of the digital electrode imbalance suppression circuits is formed.
The working principle of the invention is as follows:
the electrocardiosignal firstly passes through a sampling input stage circuit to eliminate electrode imbalance and a baseline drift part, and then the operated voltage is input into a chopper amplifier for amplification; wherein the ripple suppression loop is used for suppressing the ripple generated by the chopper amplifier; the gain control loop is used to control the gain of the entire circuit. Input terminal V of chopper amplifier ampp And V ampn The output end of the sampling input stage circuit is connected with V outn And V outp Is the output of the amplifier. Input terminal V ampp And V ampn Differential input signal V amp Modulated at chopping frequency by chopper MX1 and then passed through transconductance amplifier G m1 、G m4 Amplifying, demodulating to baseband frequency by chopper MX2, and passing through C 31 、C 32 、A 1 Constitution ofSignal filtering is performed by an integrator of the (a); the input end of the ripple suppression loop is connected with the output end V of the chopper amplifier outn 、V outp The output end of the ripple suppression loop is connected with the feedback node of the chopper amplifier, namely the transconductance amplifier G m4 Is provided. Due to the transconductance amplifier G m1 、G m4 Is modulated by chopper MX2 into square wave with chopping frequency, and then passes through C 31 、C 32 、A 1 The integrator is configured to form a triangular wave having a chopping frequency, and to eliminate the triangular wave, the ripple suppression loop first uses V out The triangular wave voltage is divided into square wave current with chopping frequency by capacitance differentiation, then the square wave current is demodulated into direct current by a chopper MX2, and the direct current is transmitted through A 2 、C 51 、C 52 The integrator forms a DC voltage which is fed back to G through a transconductance amplifier m4 Offset G m1 And G m4 Is a low frequency noise and detuning of the same; gain control loop, through capacitor C 11 、C 12 、C 21 、C 22 For output voltage V outn 、V outp Dividing the voltage to output the voltage C 11 /(C 11 +C 21 ) The voltage of multiple magnitude is fed back to the transconductance amplifier G m2 If G m2 And G m1 Is equal, the gain of the amplifier can be controlled to be C 21 /C 11 +1。
And the sampling input stage circuit is used for completing the sampling and preprocessing of the input signal, and removing electrode mismatch and baseline wander components in the input signal before the input signal enters the chopper amplifier without reducing the input impedance of the circuit. The sampling input stage circuit of the fully differential ping-pong structure capacitor carries out signal conditioning before signals enter the amplifier, electrode imbalance and baseline drift components are eliminated, and input impedance of the amplifier is improved. The circuit controls the switch K by two-phase non-overlapping clocks phi 1 and phi 2 respectively 11 ～K 14 ，K 21 ～K 24 Because the circuit is based on sampling technology, in order to make the input signal of the circuit continuous, the circuit adopts two modules block1 and block2 to form a ping-pong structure. K when phi 1 is high 11 ～K 14 Conduction, K 21 ～K 24 Cut-off, block1 is in the sampling phase, block2 is in the input phase; conversely, K is high when φ 2 is high 11 ～K 14 Cut-off, K 21 ～K 24 Conducting, wherein block1 is in an input stage, and block2 is in a sampling stage; the input signal is made continuous by alternately operating block1 and block 2. Next, block1 is analyzed with emphasis, and the circuit is divided into two phases:
(1) sampling phase (phi 1 is high):
switch K 11 ～K 14 Conduction and switch K 21 ～K 24 Cut-off, capacitance C in1 And V is equal to inn 、V DDSLn C is connected with in2 And V is equal to inp 、V DDSLp To which C is attached at this time in1 、C in2 The voltages on are respectively as follows:
V cin1 ＝V inn -V DDSLn (1)
V cin2 ＝V inp -V DDSLp (2)
(2) input phase (phi 2 is high):
switch K 11 ～K 14 Cut-off, switch K 21 ～K 24 Conduction and capacitance C in1 And V is equal to ampn 、V ADSLn C is connected with in2 And V is equal to ampp 、V ADSLp The voltage on the capacitor will not change, and the voltage in the sampling stage is maintained, so the input voltage V ampn 、V ampp The voltages are respectively as follows:
V ampn ＝V cin1 +V ADSLn ＝ V inn -V DDSLn +V ADSLn (3)
V ampp ＝ V cin2 +V ADSLp ＝ V inp -V DDSLp +V ADSLp (4)
let input differential mode voltage V in ＝V inp -V inn The method comprises the steps of carrying out a first treatment on the surface of the Output differential mode voltage V amp ＝V ampp -V ampn From (3) and (4):
V amp ＝V in -(V DDSLp -V DDSLn )+(V ADSLp -V ADSLn ) (5)
let V DSL ＝(V DDSLp -V DDSLn )+(V ADSLn -V ADSLp ) Obtained by (5):
V amp ＝V in -V DSL (6)
when the feedback is stable, V DSL And input V in The electrode mismatch and baseline wander components of the amplifier are equal, so the differential input V of the amplifier amp Not including V in Electrode misalignment and baseline wander components of the electrode assembly are effectively inhibited.
The analog electrode imbalance suppression loop firstly utilizes a low-pass filter to carry out low-pass filtering on the output signal of the chopper amplifier to take out electrode imbalance and baseline drift interference, and outputs an analog feedback signal after amplification, and then utilizes an attenuator to attenuate the analog feedback signal and send the attenuated analog feedback signal into the sampling input stage circuit so as to offset the electrode imbalance and the baseline drift interference which are input from the outside. The fast recovery circuit is used for improving the voltage recovery speed of the high-resistance node. When the two hysteresis comparators detect that the output voltage is higher than V ref At the time, the gate voltage of the pseudo-resistor is pulled down to V b The pseudo resistance is reduced, and the charging of the capacitor node is quickened. Because the cut-off frequency of the low-pass filter is positioned at the ultra-low frequency and is out of band of the electrocardiosignal, the capacitor C is arranged in the band 61 、C 62 The impedance of (a) is much lower than the impedance of the pseudo-resistor P-RES, the amplifier a 3 For in-band signals, the signal corresponds to a follower, and thus an amplifier A 3 Output noise of (A) and A 3 Is always equal to A regardless of the gain of (2) 3 Is an input equivalent noise of (a). Therefore, the attenuator is designed to attenuate noise introduced by the analog electrode imbalance suppression loop, but to increase A in design so as not to reduce the ability to suppress electrode imbalance 3 An extra 10-time attenuator is added, the noise contribution of the analog electrode imbalance suppression loop is reduced by 10 times while the loop gain is not reduced. In order to avoid introducing extra noise and power consumption, the attenuator modulates DC to high-frequency channelThe DC is demodulated after the capacitive voltage division, so that the problems of noise increase and power consumption increase caused by the use of resistor voltage division are avoided.
The digital electrode imbalance suppression circuit detects the voltage of an analog feedback signal output by an active low-pass filter of the analog electrode imbalance suppression loop, generates a digital compensation signal according to the voltage, and sends the digital compensation signal to the sampling input stage circuit so as to prevent the output saturation of the low-pass filter and expand the electrode imbalance suppression range. TESTn signal is from inside A of analog electrode offset circuit 3 TESTp is led from the inner part A of the analog electrode disturbance suppression loop 3 Is derived from the in-phase output of (C), clk_100Hz is a clock signal of 100 Hz. The analog electrode disturbance suppression loop is connected with a 10-time attenuator, and when 1.8V power is supplied, the amplifier A 3 The output swing of the attenuator is +/-1V, and the output swing of the attenuator is only +/-100 mV. To compensate for the loss of suppression amplitude, the digital electrode imbalance workflow is as follows:
four-bit output end A of shift register<4:1>And B<4:1>To MOS tube M 21 ～M 24 、M 11 ～M 14 The control modes of (a) are shown in tables 1 and 2
Shifting register pair MOS tube M 11 ～M 14 、M 21 ～M 24 The control relation of (2) is as follows:
TABLE 1 four bit output A <4:1> control logic
| Binary value | A<4> | A<3> | A<2> | A<1> | Conductive pipe |
| 0001 | 0 | 0 | 0 | 1 | M 21 |
| 0010 | 0 | 0 | 1 | 0 | M 22 |
| 0100 | 0 | 1 | 0 | 0 | M 23 |
| 1000 | 1 | 0 | 0 | 0 | M 24 |
TABLE 2 four bit output B <4:1> control logic
| Binary value | B<4> | B<3> | B<2> | B<1> | Conductive pipe |
| 0001 | 0 | 0 | 0 | 1 | M 11 |
| 0010 | 0 | 0 | 1 | 0 | M 12 |
| 0100 | 0 | 1 | 0 | 0 | M 13 |
| 1000 | 1 | 0 | 0 | 0 | M 14 |
Under the condition that the circuit works normally, the MOS tube M 21 ～M 24 Only one tube is conducted, and simultaneously, the MOS tube M 11 ～M 14 Only one tube is in communication. Therefore, in order to prevent circuit errors, a reset module Rest is added in the digital electrode imbalance suppression circuit, and the module detects A<4:1>、B<4:1>If M 21 ～M 24 Wherein two MOS tubes are simultaneously conducted, the A is then carried out<4:1>And B<4:1>Simultaneously reset to 0001; also if M 11 ～M 14 Wherein two MOS tubes are simultaneously conducted, A is also conducted<4:1>And B<4:1>And meanwhile, the circuit is reset to 0001, so that the fault tolerance of the circuit is improved.
The workflow of the shift register can be illustrated by fig. 6:
(1) when TESTn detects amplifier A 3 When the voltage of the inverting output terminal is higher than the threshold VCM, the shift register determines whether the four-bit output terminal B is 1 (0001):
if the clock is not 1, the four-bit output end B is shifted to the right by one bit on the next clock rising edge, and the switch controlled by the four-bit output end B can enable V DDSLn The output voltage drops by 70mV, as can be seen by equation (5), because of V in The near DC component of (C) will not be suddenly changed in a short time due to the characteristic of ultra-low frequency, namely V DSL Unchanged, V DDSLn Descent will cause V ADSLn Dropping, i.e., TESTn dropping;
if the four bit output terminal B is 1, the four bit output terminal A is controlled to shift one bit left on the next clock rising edge so that V DDSLp Rise by 70mV, likewise by formulae (5) and V DSL Invariably see V DDSLp Rise also results in V ADSLn Drop, TESTn drop.
(2) When TESTp detects amplifier A 3 When the voltage at the in-phase output is higher than the threshold VCM, the shift register judges whether the four-bit output end A is1 (0001):
if not 1, the four-bit output A is shifted to the right by one bit on the next clock rising edge, so that V DDSLp The output voltage drops by 70mV, passing through (5) and V DSL Invariably see V DDSLp The drop will lead to V ADSLp Descent, TESTp descent;
if the four-bit output A is 1, the four-bit output B is controlled to shift one bit left on the next clock rising edge so that V DDSLn Ascending, through formulas (5) and V DSL Invariably see V DDSLn Rise also results in V ADSLp Drop, TESTp drop.
The digital electrode disturbance suppression part provides 7 different differential voltages, so that the amplitude compensation of +/-210 mV is provided for the analog electrode disturbance suppression loop, and the analog electrode disturbance suppression loop has the suppression capacity of +/-100 mV, so that the total suppression capacity is expanded to +/-310 mV.
Fig. 7 shows the simulation result of periodic steady-state alternating current (PAC) of the present low noise high input impedance amplifier, and the simulation result shows that the circuit has a high pass angle of 0.6Hz, so that electrode mismatch and baseline drift interference can be effectively filtered.
FIG. 8 shows the simulation result of the periodic stationary noise (PNOISE) of the low-noise high-input-impedance amplifier, and the circuit hasThe ultra-low noise of the CMOS circuit effectively solves the problem of larger flicker noise of the CMOS circuit, and satisfies the ultra-low frequency and low noise application of biomedicine.
Fig. 9 shows the simulation result of the relationship between the input impedance and the frequency of the low-noise high-input impedance amplifier, and the simulation result shows that the circuit has the input impedance of 7GΩ@0.1-250 Hz, thereby meeting the application of the wearable biomedical dry electrode.
FIG. 10 shows the time domain function verification of the low noise high input impedance amplifier, wherein a 300mV electrode imbalance is added to the input of the low noise high input impedance amplifier at 1s, and the simulation result shows that the circuit effectively inhibits the 300mV electrode imbalance, and the recovery time of the system is less than 100ms.
The invention adopts a novel capacitance sampling input stage circuit, a feedback mode based on capacitance operation and a novel double-loop mixed regulation mode based on combination of digital regulation and analog regulation by capacitance, thereby effectively avoiding the problem of input impedance reduction caused by feedback. Under the condition of 20KHz chopper frequency, the input impedance is 7GΩ@0.6-250 Hz.
The proposed wearable dry electrode low-noise high-input-impedance continuous electrocardiograph monitoring amplifier circuit is subjected to software simulation under the 180nm CMOS process standard, and the result shows that under the condition of 1.8V power supply, the total power consumption is 18uW, the input impedance is 7GΩ@0.6-250 Hz, the gain is 46dB, the high-pass cut-off frequency of 0.6Hz is achieved, and the equivalent input noise isThe effective value of the integrated noise in the 0.6-250 Hz band is 1.9uVrms.
The invention is suitable for detecting weak electric signals during biomedical signal acquisition, such as electrocardio and electroencephalogram monitoring, and the like, and can amplify other bioelectric signals through adjusting the low-pass cut-off frequency in the analog electrode imbalance inhibition loop so as to meet the application requirements of the biomedical field on low noise, ultralow frequency, high impedance, high precision and low power consumption of the bioelectric signals.
It is achieved that a high input impedance is maintained after the introduction of the chopper stabilization technique, and that there is a high input impedance from within the passband to dc, and no additional noise is introduced. The capacitive sampling input structure is characterized in that a novel capacitive operation-based electrode imbalance suppression circuit is adopted, the problem that input impedance is reduced due to the fact that an electrode imbalance suppression circuit is connected to an input end conventionally is solved, the input impedance is improved without an additional positive feedback circuit, meanwhile, a mode of mixing and adjusting a digital electrode imbalance suppression circuit and an analog electrode imbalance suppression circuit is adopted, and noise of the electrode imbalance suppression circuit is effectively reduced under the condition that an electrode imbalance suppression range of +/-300 mV is guaranteed. The circuit also comprises a chopper main amplifier for amplifying weak electrocardiosignals; a ripple suppression loop for suppressing a ripple generated by the chopper amplifier; the gain control loop is used to determine the gain of the amplifier.
It should be noted that, although the examples described above are illustrative, this is not a limitation of the present invention, and thus the present invention is not limited to the above-described specific embodiments. Other embodiments, which are apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein, are considered to be within the scope of the invention as claimed.
Claims (5)
1. The low-noise high-input impedance amplifier applied to the wearable dry electrode electrocardiograph monitoring comprises a chopper amplifier, a ripple suppression loop and a gain control loop;
the input end of the ripple suppression loop is connected with the output end of the chopper amplifier, and the output end of the ripple suppression loop is connected with the output end of the first-stage transconductance amplifier in the chopper amplifier; the input end of the gain control loop is connected with the output end of the chopper amplifier, and the output end of the ripple suppression loop is connected with the output end of a first-stage transconductance amplifier in the chopper amplifier;
the circuit is characterized by further comprising a sampling input stage circuit, an analog electrode imbalance suppression loop and a digital electrode imbalance suppression circuit;
input terminal V of sampling input stage circuit inn And V inp Forming the input end of the low-noise high-input impedance electrocardio amplifier; output terminal V of sampling input stage circuit ampn And V ampp The input end of the chopper amplifier is connected; the output end of the chopper amplifier is provided with the output end of the low-cost high-input impedance electrocardio amplifier;
the analog electrode imbalance suppression loop comprises a low-pass filter and an attenuator; a group of input ends of the low-pass filter form an input end of an analog electrode imbalance suppression loop and are connected with an output end of the chopper amplifier; the output end of the low-pass filter is connected with the input end of the attenuator; the output end of the attenuator is connected with the input end V of the sampling input stage circuit ADSLn And V ADSLp ；
Digital electrode imbalanceThe input end of the suppression circuit is connected with the output end of the low-pass filter of the analog electrode imbalance suppression loop, and the output end of the digital electrode imbalance suppression circuit is connected with the input end V of the sampling input stage circuit DDSLn And V DDSLp ；
The sampling input stage circuit finishes sampling and preprocessing an external input signal, and electrode mismatch and baseline drift interference in the input signal are removed without reducing the input impedance of the circuit before the input signal enters the chopper amplifier;
the analog electrode imbalance suppression loop firstly utilizes a low-pass filter to carry out low-pass filtering on the output signal of the chopper amplifier to take out electrode imbalance and baseline drift interference, amplifies the electrode imbalance and baseline drift interference and outputs an analog feedback signal, and then utilizes an attenuator to attenuate the analog feedback signal and sends the attenuated analog feedback signal to the sampling input stage circuit so as to offset the electrode imbalance and baseline drift interference of an external input signal;
the digital electrode imbalance suppression circuit detects the voltage of the analog feedback signal output by the active low-pass filter of the analog electrode imbalance suppression loop, and generates a digital compensation signal accordingly to be sent to the sampling input stage circuit so as to prevent the output of the low-pass filter from being saturated.
2. The low noise high input impedance amplifier for wearable dry electrode electrocardiograph monitoring of claim 1 characterized by: the sampling input stage circuit comprises 16 NMOS tubes K 11 ～K 18 、K 21 ～K 28 And 4 sampling capacitances C in1 ～C in4 ；
NMOS tube K 11 ～K 18 The grid electrode of the NMOS transistor K is connected with a clock signal phi 1 21 ～K 28 The grid of which is connected with a clock signal phi 2; the clock signal phi 1 and the clock signal phi 2 are a group of non-overlapping clocks;
capacitor C in1 One end of (2) is connected with NMOS tube K 11 And K 21 Is connected with the source electrode of the capacitor C in1 The other end of (2) is connected with NMOS tube K 12 And K 22 Is connected with the drain electrode of the transistor; capacitor C in2 One end of (2) is connected with NMOS tube K 13 And K 23 Is connected with the source electrode of the capacitor C in2 The other end of (2) is connected with NMOS tube K 14 And K 24 Is connected with the drain electrode of the transistor; capacitor C in3 One end of (2) is connected with NMOS tube K 15 And K 25 Is connected with the source electrode of the capacitor C in3 The other end of (2) is connected with NMOS tube K 16 And K 26 Is connected with the drain electrode of the transistor; capacitor C in4 One end of (2) is connected with NMOS tube K 17 And K 27 Is connected with the source electrode of the capacitor C in4 The other end of (2) is connected with NMOS tube K 18 And K 28 Is connected with the drain electrode of the transistor;
NMOS tube K 11 And K 25 Form the input terminal V of the sampling input stage circuit inn The method comprises the steps of carrying out a first treatment on the surface of the NMOS tube K 13 And K 27 Form the input terminal V of the sampling input stage circuit inp The method comprises the steps of carrying out a first treatment on the surface of the NMOS tube K 15 And K 21 The drain of which forms the output V of the sampling input stage circuit ampn The method comprises the steps of carrying out a first treatment on the surface of the NMOS tube K 17 And K 23 The drain of which forms the output V of the sampling input stage circuit ampp The method comprises the steps of carrying out a first treatment on the surface of the NMOS tube K 16 And K 22 Form the input V of the sampling input stage circuit ADSLn The method comprises the steps of carrying out a first treatment on the surface of the NMOS tube K 18 And K 24 Form the input V of the sampling input stage circuit ADSLp The method comprises the steps of carrying out a first treatment on the surface of the NMOS tube K 12 And K 26 Form the input V of the sampling input stage circuit DDSLn The method comprises the steps of carrying out a first treatment on the surface of the NMOS tube K 14 And K 28 Form the input V of the sampling input stage circuit DDSLp 。
3. The low noise high input impedance amplifier for wearable dry electrode electrocardiograph monitoring of claim 1 characterized by: the low-pass filter of the analog electrode imbalance suppression loop comprises a hysteresis comparator I 1 、I 2 NAND gate I 3 PMOS tube M 1 –M 3 NMOS tube M 4 Amplifier A 3 And a capacitor C 61 、C 62 ；
Hysteresis comparator I 1 And hysteresis comparator I 2 Form a set of inputs of a low pass filter; hysteresis comparator I 1 And hysteresis comparator I 2 The non-inverting input terminal of (2) is connected with the reference voltage V ref The method comprises the steps of carrying out a first treatment on the surface of the Delay timeHysteresis comparator I 1 And hysteresis comparator I 2 The output ends of (a) are respectively connected with the NAND gate I 3 2 inputs of (a); NOT gate I 3 The output end of (a) is connected with the NMOS tube M at the same time 3 And PMOS tube M 4 A gate electrode of (a); NMOS tube M 4 Is connected with a reference voltage V b The method comprises the steps of carrying out a first treatment on the surface of the PMOS tube M 3 The source electrode of the transistor is connected with a power supply; NMOS tube M 3 And PMOS tube M 4 Is connected with the drain electrode of the PMOS tube M 1 And PMOS tube M 2 Is connected with the grid electrode; PMOS tube M 1 Drain and hysteresis comparator I 2 Is connected with the inverting input end of the PMOS tube M 1 Source connection amplifier a of (2) 3 Is provided; PMOS tube M 2 Drain and hysteresis comparator I 1 Is connected with the inverting input end of the PMOS tube M 2 Source connection amplifier a of (2) 3 Is provided with a non-inverting input terminal; capacitor C 61 Is connected with the amplifier A at two ends respectively 3 An inverting input terminal and an inverting output terminal; capacitor C 62 Is connected with the amplifier A at two ends respectively 3 A non-inverting input terminal and an inverting output terminal; amplifier A 3 The in-phase output and the anti-phase output of (c) form a set of outputs of the low-pass filter.
4. The low noise high input impedance amplifier for wearable dry electrode electrocardiograph monitoring of claim 1 characterized by: the attenuator of the analog electrode disturbance suppression loop comprises chopper choppers chopping1 and chopping2 and a capacitor C 71 、C 72 、C 81 、C 82 ；
The 2 inputs of chopper chopping1 form a set of inputs of the attenuator; one output end of chopper capacitor C 71 Capacitance C 71 The other end of (2) is divided into 2 paths, one path is connected with the capacitor C 81 The other path is connected with one input end of the chopper 2; the other output end of chopper chopping1 is connected with capacitor C 72 Capacitance C 72 The other end of (2) is divided into 2 paths, one path is connected with the capacitor C 82 The other path is connected with the other input end of the chopper 2; the 2 outputs of chopper chopping2 form a set of outputs of the attenuator.
5. The low noise high input impedance amplifier for wearable dry electrode electrocardiograph monitoring of claim 1 characterized by: the digital electrode imbalance suppression circuit comprises a comparator U 1 、U 2 Shift register, constant current source I 1 Resistance R 1 ～R 3 NMOS tube M 11 ～M 14 、M 21 ～M 24 、M 5 And a reset module Rest;
comparator U 1 Sum comparator U 2 A group of input ends of the digital electrode imbalance suppression circuit are arranged at the same phase input ends of the digital electrode imbalance suppression circuit; comparator U 1 Sum comparator U 2 The inverting input terminal of (2) is simultaneously connected with the reference voltage VCM; comparator U 1 An output end of the (B) is connected with a rising input end up of the Shift register (Shift), and a comparator U 2 The output end of the (a) is connected with the descending input end down of the Shift register Shift; the clock end of the Shift register Shift is connected with an external clock signal; the reset end Rest of the Shift register Shift is connected with the output end of the reset module Rest; a first group of four-bit output terminals A of the shift register<4:1>Is divided into 2 paths, one path is sent to a reset module Rest, and the other path is respectively connected with an NMOS tube M 21 ～M 24 A gate electrode of (a); second group of four-bit output terminals B of shift register<4:1>Is divided into 2 paths, one path is sent to a reset module Rest, and the other path is respectively connected with an NMOS tube M 11 ～M 14 A gate electrode of (a); current source I 1 Is connected with a power supply and a current source I 1 Is connected with the NMOS tube M 14 And NMOS tube M 24 Source of (d), and resistor R 1 Is a member of the group; resistor R 1 NMOS tube M at the other end of (2) 13 And NMOS tube M 23 Source of (d), and resistor R 2 Is a member of the group; resistor R 2 NMOS tube M at the other end of (2) 12 And NMOS tube M 22 Source of (d), and resistor R 3 Is a member of the group; resistor R 3 NMOS tube M at the other end of (2) 11 And NMOS tube M 12 Source electrode of (d), and NMOS transistor M 5 Gate and drain of (a); NMOS tube M 5 The drain electrode of the transistor is grounded;
NMOS tube M 11 ～M 14 After the drains of (a) are connected, digital electricity is formedOne of a group of output ends of the polar disturbance suppression circuit, NMOS tube M 21 ～M 24 After the drains of the digital electrode imbalance suppression circuits are connected, another one of a set of output terminals of the digital electrode imbalance suppression circuits is formed.
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| CN110638443A (en) * | 2019-11-07 | 2020-01-03 | 福州大学 | Electrocardiosignal reading circuit |
| JP7456284B2 (en) * | 2020-05-25 | 2024-03-27 | セイコーエプソン株式会社 | PHYSICAL QUANTITY DETECTION CIRCUIT, PHYSICAL QUANTITY DETECTION DEV |
| CN111697963B (en) * | 2020-06-15 | 2023-03-21 | 电子科技大学 | Integrator suitable for ripple eliminating loop |
| CN111839500B (en) * | 2020-07-10 | 2023-01-31 | 中国科学院深圳先进技术研究院 | Fast recovery circuit and fast recovery method |
| US11918377B2 (en) | 2021-01-19 | 2024-03-05 | Medtronic, Inc. | Dry electrodes in a wearable garment |
| CN114531120A (en) * | 2022-01-04 | 2022-05-24 | 电子科技大学 | High-performance 8-channel bioelectric signal instrument amplifier |
| CN115005842B (en) * | 2022-08-09 | 2022-11-15 | 之江实验室 | Frequency-modulated brain-computer interface chip input impedance enhancing method and system |
| CN115337021B (en) * | 2022-10-19 | 2023-01-24 | 之江实验室 | Method and system for removing baseline drift applied to electrocardio acquisition |
| CN116169967A (en) * | 2022-12-29 | 2023-05-26 | 杭州万高科技股份有限公司 | Control circuit and control method of fully differential capacitive feedback amplifier |
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