CN110197266B

CN110197266B - Integrated circuit chip device and related product

Info

Publication number: CN110197266B
Application number: CN201810164230.XA
Authority: CN
Inventors: 不公告发明人
Original assignee: Shanghai Cambricon Information Technology Co Ltd
Current assignee: Shanghai Cambricon Information Technology Co Ltd
Priority date: 2018-02-27
Filing date: 2018-02-27
Publication date: 2020-08-04
Anticipated expiration: 2038-02-27
Also published as: CN110197266A

Abstract

The present disclosure provides an integrated circuit chip device and related products, the integrated circuit chip device comprising: the device comprises a main processing circuit, K branch processing circuits and K groups of basic processing circuits; the main processing circuit comprises a first mapping circuit, each branch processing circuit in the K branch processing circuits comprises a second mapping circuit, and the first mapping circuit and the second mapping circuit are used for executing compression processing of each data in neural network operation. The technical scheme provided by the disclosure has the advantages of small calculation amount and low power consumption.

Description

Integrated circuit chip device and related product

Technical Field

The present disclosure relates to the field of neural networks, and more particularly to an integrated circuit chip device and related products.

Background

Artificial Neural Networks (ANN) are a research hotspot in the field of Artificial intelligence since the 80 s of the 20 th century. The method abstracts the human brain neuron network from the information processing angle, establishes a certain simple model, and forms different networks according to different connection modes. It is also often directly referred to in engineering and academia as neural networks or neural-like networks. A neural network is an operational model, which is formed by connecting a large number of nodes (or neurons). The operation of the existing neural network is realized based on a Central Processing Unit (CPU) or a Graphics Processing Unit (GPU), and the operation has a large amount of calculation and high power consumption.

Disclosure of Invention

Embodiments of the present disclosure provide an integrated circuit chip device and related products, which can increase the processing speed and efficiency of a computing device.

In a first aspect, an integrated circuit chip device is provided, the integrated circuit chip device comprising: the system comprises a main processing circuit, k branch processing circuits and k groups of basic processing circuits, wherein the main processing circuit is respectively connected with the k branch processing circuits, each branch processing circuit in the k branch processing circuits corresponds to one group of basic processing circuits in the k groups of basic processing circuits, and the group of basic processing circuits comprises at least one basic processing circuit;

the main processing circuit comprises a first mapping circuit, the branch processing circuit comprises a second mapping circuit, and the first mapping circuit and the second mapping circuit are used for executing compression processing of each data in neural network operation;

the main processing circuit is used for executing each continuous operation in the neural network operation and transmitting data with the k branch processing circuits connected with the main processing circuit;

the k branch processing circuits are used for forwarding the transmission data between the main processing circuit and the k groups of basic circuits and controlling whether to start the second mapping circuit to process the transmission data according to the operation of the transmission data;

the k basic processing circuits are used for executing operation in the neural network in a parallel mode according to the transmission data or the processed transmission data and transmitting an operation result to the main processing circuit through the branch processing circuit connected with the main processing circuit.

In a second aspect, a neural network computing device is provided, which includes one or more integrated circuit chip devices provided in the first aspect.

In a third aspect, there is provided a combined processing apparatus comprising: the neural network arithmetic device, the universal interconnection interface and the universal processing device are provided by the second aspect;

the neural network operation device is connected with the general processing device through the general interconnection interface.

In a fourth aspect, a chip is provided that integrates the apparatus of the first aspect, the apparatus of the second aspect, or the apparatus of the third aspect.

In a fifth aspect, an electronic device is provided, which comprises the chip of the fourth aspect.

In a sixth aspect, a method for operating a neural network is provided, where the method is applied in an integrated circuit chip device, and the integrated circuit chip device includes: the integrated circuit chip apparatus of the first aspect, configured to perform an operation of a neural network.

It can be seen that, according to the embodiment of the disclosure, the mapping circuit is provided to compress the data blocks and then perform the operation, so that the transmission resource and the calculation resource are saved, and therefore, the mapping circuit has the advantages of low power consumption and small calculation amount.

Drawings

FIG. 1a is a schematic diagram of an integrated circuit chip device.

FIG. 1b is a schematic diagram of another integrated circuit chip device.

FIG. 1c is a schematic diagram of a basic processing circuit.

FIG. 2 is a schematic diagram of a process for multiplying a matrix by a vector.

Fig. 2a is a schematic representation of a matrix multiplied by a vector.

FIG. 2b is a schematic diagram of a process of multiplying a matrix by a matrix.

Fig. 2c is a schematic diagram of the matrix Ai multiplied by the vector B.

Fig. 2d is a schematic diagram of matrix a multiplied by matrix B.

Fig. 2e is a schematic diagram of matrix Ai multiplied by matrix B.

FIG. 3a is a schematic diagram of neural network training.

FIG. 3b is a schematic diagram of convolution operation.

Fig. 4 is a schematic structural diagram of a neural network chip according to an embodiment of the present disclosure.

Fig. 5 a-5 b are schematic structural diagrams of two mapping circuits provided in the present embodiment.

Detailed Description

In order to make the technical solutions of the present disclosure better understood by those skilled in the art, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only a part of the embodiments of the present disclosure, not all of the embodiments. All other embodiments, which can be derived by one of ordinary skill in the art from the embodiments disclosed herein without making any creative effort, shall fall within the scope of protection of the present disclosure.

In the apparatus provided in the first aspect, the main processing circuit is configured to obtain a data block to be calculated and an operation instruction, divide the data block to be calculated into a distribution data block and a broadcast data block according to the operation instruction, start the first mapping circuit to process the distribution data block and the broadcast data block to obtain a processed distribution data block and an identification data block associated with the distribution data block, a processed broadcast data block and an identification data block associated with the broadcast data block, split the processed distribution data block and the identification data block associated with the distribution data block to obtain a plurality of basic data blocks and identification data blocks associated with the plurality of basic data blocks, distribute the plurality of basic data blocks and the identification data blocks associated with the plurality of basic data blocks to the k branch processing circuits connected thereto, broadcast the broadcast data block and the identification data block associated with the broadcast data block to the k branch processing circuits connected thereto, wherein the data blocks may be represented by a direct index or an identification data block index, and may be represented by a hylist (539, 6754, a Sparse list (csridge, 3626, csridge.

Taking the identification data block represented by a direct index as an example, the identification data block may specifically be a data block composed of 0 and 1, where 0 represents that an absolute value of data (such as a weight or an input neuron) included in the data block is less than or equal to a first threshold, 1 represents that an absolute value of data (such as a weight or an input neuron) included in the data block is greater than a first threshold, and the first threshold is randomly set by a user side or a device side in a customized manner, for example, 0.05, 0, and so on.

In order to save data transmission amount and improve data transmission efficiency, in the process that the main processing circuit sends data to the basic processing circuit, target data in the plurality of basic data blocks and identification data blocks respectively associated with the plurality of basic data blocks can be specifically distributed to branch processing circuits connected with the main processing circuit; optionally, the target data in the processed broadcast data block and the identification data block associated with the broadcast data block may also be broadcast to a branch processing circuit connected thereto. The target data refers to data with an absolute value greater than a first threshold in a data block, or refers to non-0 data in a data block (which may be specifically a processed distribution data block or a processed broadcast data block).

Correspondingly, the k branch processing circuits are configured to start the second mapping circuit to obtain a connection identification data block according to the identification data block associated with the basic data block and the identification data block associated with the broadcast data block; processing the basic data block and the broadcast data block according to the connection identification data block, and distributing the processed basic data block and the processed broadcast data block to a basic processing circuit connected with the basic data block and the processed broadcast data block;

the basic processing circuit is used for executing inner product operation on the processed basic data block and the processed broadcast data block to obtain an operation result, and sending the operation result to the main processing circuit through the branch processing circuit;

and the main processing circuit is used for processing the operation result to obtain the data block to be calculated and an instruction result corresponding to the operation instruction.

For example, distributing the data block to M₁Line N₁Matrix of columns, basic data block M₂Line N₂A matrix of columns, wherein M₁>M₂，N₁>N₂. Correspondingly, the identification data block associated with the distribution data block is also M₁Line N₁A matrix of columns, the identification data block associated with the basic data block being likewise M₂Line N₂A matrix of columns. Take the matrix with 2 x 2 as the basic data block as an example, set as

If the first threshold is 0.05, the identification data block associated with the basic data block is

The processing of the data blocks with respect to the first mapping circuit and the second mapping circuit will be described in detail later.

Optionally, the main processing circuit may be further configured to split the processed broadcast data block and the identification data block associated with the broadcast data block to obtain a plurality of partial broadcast data blocks and identification data blocks associated with the plurality of partial broadcast data blocks; and broadcast them one or more times to the k branch processing circuits connected to it. Correspondingly, the k branch processing circuits are specifically configured to start the second mapping circuit to obtain a connection identification data block according to the identification data block associated with the partial broadcast data block and the identification data block associated with the basic data block, process the partial broadcast data block and the basic data block by using the connection identification data block, and distribute the processed partial broadcast data block and the processed basic data block to a basic processing circuit connected thereto, so as to perform inner product operation subsequently.

In the apparatus provided in the first aspect, the main processing circuit is configured to obtain a data block to be calculated and an operation instruction, and divide the data block to be calculated into a distribution data block and a broadcast data block according to the operation instruction; starting the first mapping circuit to process the distribution data block to obtain a processed distribution data block and an identification data block associated with the distribution data block, or starting the first mapping circuit to process the distribution data block according to a prestored identification data block associated with the distribution data block to obtain a processed distribution data block; splitting the processed distribution data block and the identification data block associated with the distribution data block to obtain a plurality of basic data blocks and identification data blocks associated with the basic data blocks; distributing the plurality of elementary data blocks and the identification data blocks associated with each of the plurality of elementary data blocks to the k branch processing circuits connected thereto; broadcasting the broadcast data block to the k branch processing circuits connected thereto;

the k branch processing circuits are used for starting the second mapping circuit to process the broadcast data block according to the identification data block associated with the basic data block, and distributing the processed broadcast data block and the basic data block to a basic processing circuit connected with the basic processing circuit;

the basic processing circuit is used for executing inner product operation on the processed broadcast data block and the basic data block to obtain an operation result, and forwarding the operation result to the main processing circuit through the branch processing circuit;

and the main processing circuit is used for processing the operation result to obtain the data block to be calculated and an instruction result of the operation instruction.

Optionally, the main processing circuit may be further configured to split the broadcast data block to obtain a plurality of partial broadcast data blocks, and broadcast the partial broadcast data blocks to the k branch processing circuits connected thereto one or more times. Correspondingly, the k branch processing circuits are specifically configured to start the second mapping circuit to process the partial broadcast data block according to the identification data block associated with the basic data block, and distribute the processed partial broadcast data block and the basic data block to a basic processing circuit connected thereto, so as to perform inner product operation subsequently.

In an aspect of the apparatus, the main processing circuit is configured to obtain a data block to be calculated and an operation instruction, and divide the data block to be calculated into a distribution data block and a broadcast data block according to the operation instruction; starting the first mapping circuit to process the broadcast data block to obtain a processed broadcast data block and an identification data block associated with the broadcast data block, or starting the first mapping circuit to process the broadcast data block according to a pre-stored identification data block associated with the broadcast data block to obtain a processed broadcast data block; splitting the distribution data block to obtain a plurality of basic data blocks; distributing the plurality of basic data blocks to the k branch processing circuits connected thereto; broadcasting the processed broadcast data block and the identification data block related to the broadcast data block to the k branch processing circuits connected with the processed broadcast data block;

the k branch processing circuits are configured to start the second mapping circuit to process the basic data block according to the identification data block associated with the broadcast data block to obtain a processed basic data block, and send the processed basic data block and the processed broadcast data block to a basic processing circuit connected to the basic processing circuit;

the basic processing circuit is configured to perform inner product operation on the processed basic data block and the processed broadcast data block to obtain an operation result, and send the operation result to the main processing circuit through the branch processing circuit;

Optionally, the main processing circuit may be further configured to split the processed broadcast data block and the identification data block associated with the broadcast data block to obtain a plurality of partial broadcast data blocks and identification data blocks associated with the plurality of partial broadcast data blocks; and broadcast them one or more times to the k branch processing circuits connected to it. Correspondingly, the k branch processing circuits are specifically configured to start the second mapping circuit to process the basic data block according to the identification data block associated with the partial broadcast data block, and distribute the processed basic data block and the partial broadcast data block to a basic processing circuit connected thereto, so as to perform inner product operation subsequently.

In the apparatus provided in the first aspect, the main processing circuit is specifically configured to broadcast the broadcast data block or the processed broadcast data block to the k branch processing circuits at a time.

In the apparatus provided in the first aspect, the main processing circuit is specifically configured to divide the broadcast data block or the processed broadcast data block into a plurality of partial broadcast data blocks, and broadcast the plurality of partial broadcast data blocks to the K branch processing circuits by multiple times.

In the apparatus provided in the first aspect, the basic processing circuit is specifically configured to perform inner product processing on the basic data block and the broadcast data block to obtain an inner product result, accumulate the inner product processing result to obtain an operation result, and send the operation result to the main processing circuit.

Optionally, the main processing circuit is configured to, when the operation result is a result of inner product processing, accumulate the operation result to obtain an accumulation result, and arrange the accumulation result to obtain the data block to be calculated and an instruction result corresponding to the operation instruction.

In the apparatus provided in the first aspect, the basic processing circuit is specifically configured to perform an inner product process on the partial broadcast data block and the basic data block once to obtain an inner product process result, accumulate the inner product process result to obtain a partial operation result, and send the partial operation result to the main processing circuit.

In the apparatus provided in the first aspect, the basic processing circuit is specifically configured to multiplex n times the partial broadcast data block to perform an inner product operation on the partial broadcast data block and n basic data blocks to obtain n partial processing results, accumulate the n partial processing results respectively to obtain n partial operation results, and send the n partial operation results to the main processing circuit, where n is an integer greater than or equal to 2.

In an apparatus provided in the first aspect, the main processing circuit includes: a master register or on-master cache circuit;

or the branch processing circuit comprises: a basic register or a basic on-chip cache circuit;

or the base processing circuit comprises: basic registers or basic on-chip cache circuits.

In an apparatus provided in the first aspect, the main processing circuit includes: one or any combination of a vector operator circuit, an arithmetic logic unit circuit, an accumulator circuit, a matrix transposition circuit, a direct memory access circuit, a first mapping circuit or a data rearrangement circuit.

In the apparatus provided in the first aspect, the data block may be represented by a tensor, which may be specifically: one or any combination of vectors, matrices, three-dimensional data blocks, four-dimensional data blocks, and n-dimensional data blocks.

In the apparatus provided in the first aspect, if the operation instruction is a multiplication instruction, the main processing circuit determines that the multiplier data block is a broadcast data block and the multiplicand data block is a distribution data block;

if the operation instruction is a convolution instruction, the main processing circuit determines that the input data block is a broadcast data block and the convolution kernel is a distribution data block.

In a method provided in a fourth aspect, the operation of the neural network comprises: one or any combination of convolution operation, matrix multiplication matrix operation, matrix multiplication vector operation, partial execution operation, full connection operation, GEMM operation, GEMV operation and activation operation.

Referring to fig. 1a, fig. 1a is a schematic structural diagram of an integrated circuit chip device, as shown in fig. 1a, the chip device includes: a main processing circuit, a basic processing circuit and a branch processing circuit. Specifically, the integrated circuit chip device includes: a main processing circuit, k branch processing circuits (as shown in fig. 1a, k is 4, but may be other values in practical applications, such as 8, 16, and so on), and k sets of basic processing circuits, wherein the main processing circuit is connected to the k branch processing circuits, each branch processing circuit in the k branch processing circuits corresponds to one set of basic processing circuits in the k sets of basic processing circuits, and the set of basic processing circuits includes at least one basic processing circuit. The main processing circuit is used for executing each continuous operation in the neural network operation and transmitting data with the k branch processing circuits connected with the main processing circuit; the branch processing circuit includes: a second mapping circuit for performing data processing in a neural network operation; the k branch processing circuits are used for forwarding the transmission data between the main processing circuit and the k groups of basic circuits and controlling whether to start the second mapping circuit to execute conversion on the type of the transmission data according to the operation of the transmission data; the k basic processing circuits are used for executing operation in the neural network in a parallel mode according to the transmission data or the converted transmission data and transmitting an operation result to the main processing circuit through the branch processing circuit connected with the main processing circuit.

The main processing circuit (as shown in fig. 1 c) may include a register and/or an on-chip cache circuit, and may further include a control circuit, a vector operator circuit, an a L U (arithmetic and logic unit) circuit, an accumulator circuit, a DMA (Direct Memory Access) circuit, and other circuits, and in practical applications, the main processing circuit may also be added with a conversion circuit (e.g., a matrix transpose circuit), a data rearrangement circuit, or an activation circuit;

optionally, the main processing circuit may include: the first mapping circuit may be configured to process received or transmitted data to obtain processed data and mask data associated with the data, where the mask data is used to indicate whether an absolute value of the data is greater than a preset threshold, and optionally, the mask data may be 0 or 1, where 0 indicates that the absolute value of the data is less than or equal to the preset threshold; conversely, a 1 indicates that the absolute value of the data is greater than the preset threshold. The preset threshold is set by the user side or the terminal device side in a self-defined manner, for example, 0.1 or 0.05, and the like. In practical applications, the first mapping circuit may be used to eliminate data that is 0 or not greater than a predetermined threshold (e.g., 0.1), or set these data to 0. The method has the advantages that the data volume transmitted from the main processing circuit to the basic processing circuit is reduced, the calculated amount of data operation in the basic processing circuit is reduced, and the data processing efficiency is improved. The present invention is not limited to the specific form of the first mapping circuit described above. Specific implementations for the first mapping circuit are set forth below.

For example, the input data of the main processing circuit is a matrix data block

After being processed by the first mapping circuit, the processed matrix data block can be obtained as

The identification data block associated with the matrix data block is

The specific processing of the first mapping circuit will be described in detail later.

Accordingly, when the main processing circuit distributes data to the k branch processing circuits connected thereto, only two data of 1 and 0.5 may be transmitted, instead of transmitting the processed matrix data block, 8 data; meanwhile, the identification data block associated with the matrix data block needs to be sent to the corresponding branch processing circuit together, so that the branch processing circuit correspondingly knows the positions of the two data in the original matrix data block according to the received identification data block and the received two data (1 and 0.5). That is, the branch processing circuit may correspondingly restore the matrix data block processed in the main processing circuit according to the received identification data block and the received data.

The main processing circuit further includes a data transmitting circuit, a data receiving circuit or an interface, the data transmitting circuit may integrate the data distributing circuit and the data broadcasting circuit, and certainly in practical application, the data distributing circuit and the data broadcasting circuit may also be separately configured; in practical applications, the data transmitting circuit and the data receiving circuit may be integrated together to form a data transmitting/receiving circuit. For broadcast data, i.e., data that needs to be sent to each branch processing circuit or base processing circuit. For the distribution data, i.e. the data that needs to be selectively sent to part of the basic processing circuits, the specific selection mode can be specifically determined by the main processing circuit according to the load and the calculation mode. For the broadcast transmission mode, broadcast data is transmitted to each base processing circuit in a broadcast form. (in practical applications, broadcast data is transmitted to each basic processing circuit by one-time broadcasting, or broadcast data is transmitted to each basic processing circuit by multiple-time broadcasting, and the specific embodiments of the present invention do not limit the number of times of broadcasting), the distribution transmission method is to selectively transmit the distribution data to a part of the basic processing circuits.

When data distribution is realized, the control circuit of the main processing circuit transmits data to part or all of the basic processing circuits (the data may be the same or different, specifically, if the data is transmitted in a distribution mode, the data received by each basic processing circuit receiving the data may be different, and certainly, the data received by some basic processing circuits may be the same;

specifically, when data is broadcast, the control circuit of the main processing circuit transmits data to part or all of the basic processing circuits, and each basic processing circuit receiving data can receive the same data.

Optionally, the vector operator circuit of the main processing circuit may perform vector operations, including but not limited to: two vectors are added, subtracted, multiplied, divided, the vectors are added, subtracted, multiplied, divided with a constant, or any operation is performed on each element in the vector. The continuous operation may be, for example, addition, subtraction, multiplication, division, activation, accumulation, and the like of the vector and the constant.

Each base processing circuit may include a base register and/or a base on-chip cache circuit; each base processing circuit may further include: an inner product operator circuit, a vector operator circuit, an accumulator circuit, or the like, in any combination. The inner product operator circuit, the vector operator circuit, and the accumulator circuit may be integrated circuits, or the inner product operator circuit, the vector operator circuit, and the accumulator circuit may be circuits provided separately.

The chip device may optionally further include one or more branch processing circuits, for example, when the branch processing circuit is provided, the main processing circuit is connected to the branch processing circuit, the branch processing circuit is connected to the basic processing circuit, the inner product operator circuit of the basic processing circuit is configured to perform inner product operation between data blocks, the control circuit of the main processing circuit controls the data receiving circuit or the data transmitting circuit to receive and transmit external data, and controls the data transmitting circuit to distribute the external data to the branch processing circuit, and the branch processing circuit is configured to receive and transmit data from the main processing circuit or the basic processing circuit. The structure shown in fig. 1a is suitable for the computation of complex data, because the number of units connected to the main processing circuit is limited, so that a branch processing circuit needs to be added between the main processing circuit and the basic processing circuit to realize the access of more basic processing circuits, thereby realizing the computation of complex data blocks. The connection structure of the branch processing circuit and the basic processing circuit may be arbitrary and is not limited to the H-type structure of fig. 1 a. Optionally, the main processing circuit to the basic processing circuit is a broadcast or distributed structure, and the basic processing circuit to the main processing circuit is a gather structure. Broadcast, distribution and collection are defined as follows, for a distribution or broadcast configuration, the number of basic processing circuits is greater than that of the main processing circuits, i.e. 1 main processing circuit corresponds to a plurality of basic processing circuits, i.e. a configuration for broadcasting or distribution from the main processing circuit to the plurality of basic processing circuits, whereas a configuration for collection from the plurality of basic processing circuits to the main processing circuit may be provided.

The branch processing circuit receives data distributed or broadcast by the main processing circuit, stores the data into an on-chip cache of the branch processing circuit, forwards the data to the basic processing circuit for operation to generate a result, and can also send the operation result generated by the basic processing circuit to the main processing circuit. Optionally, the branch processing circuit may further process the received data, store the processed data in an on-chip cache, and send the processed data to a corresponding basic processing circuit, so as to generate a result by performing an operation on the processed data in the basic processing circuit, and optionally send the processed data to other basic processing circuits or a main processing circuit, and the like, which is not limited in this application.

Optionally, each branch processing circuit may include a second mapping circuit, or a part of the branch processing circuits may be configured with the second mapping circuit; the second mapping circuit may be used to process (i.e., compress) the received or transmitted data. The present invention is not limited to the specific form of the second mapping circuit described above. The specific implementation of the second mapping circuit will be described in detail below.

And the basic processing circuit receives data distributed or broadcasted by the branch processing circuit, stores the data into an on-chip cache of the basic processing circuit, can perform operation to generate a result, and can send the data to the main processing circuit.

Optionally, the vector operator circuit of the basic processing circuit may perform a vector operation on two vectors (any one or both of the two vectors may be processed vectors), and in practical applications, the inner product operator circuit of the basic processing circuit may perform an inner product operation on the two vectors, and the accumulator circuit may also accumulate results of the inner product operation.

In one alternative, the two vectors may be stored in on-chip caches and/or registers, and the underlying processing circuitry may fetch the two vectors to perform the operation as needed for the actual computation. This operation includes, but is not limited to: inner product operations, multiplication operations, addition operations, or other operations.

In one alternative, the result of the inner product operation may be accumulated onto an on-chip cache and/or register; the alternative scheme has the advantages of reducing the data transmission quantity between the basic processing circuit and the main processing circuit, improving the operation efficiency and reducing the data transmission power consumption.

In one alternative, the result of the inner product operation is not accumulated and is directly transmitted as a result; the technical scheme has the advantages that the internal operation amount of the basic processing circuit is reduced, and the operation efficiency of the basic processing circuit is improved.

In an alternative, each basic processing circuit can execute inner product operations of a plurality of groups of two vectors, and can also respectively accumulate the results of the inner product operations of the plurality of groups;

in one alternative, multiple sets of two vector data may be stored in on-chip caches and/or registers;

in one alternative, the results of multiple sets of inner product operations may be accumulated in an on-chip cache and/or a register, respectively;

in one alternative, the results of the inner product operations in each group can be directly transmitted as results without accumulation;

in one alternative, each base processing circuit may perform an inner product operation of the same vector with multiple vectors (a "one-to-many" inner product, i.e., one vector of two vectors of each group of inner products is shared), and accumulate the inner product results corresponding to each vector separately. According to the technical scheme, the same set of weight can be used for calculating different input data for multiple times, data multiplexing is increased, the data transmission quantity of data in a basic processing circuit is reduced, the calculation efficiency is improved, and the power consumption is reduced.

Specifically, in the data used to compute the inner product, the data sources of the vector shared by the groups and the other vector of each group (i.e., the vector that differs between each group) may differ:

in one alternative, the sets of shared vectors are broadcast or distributed from the main processing circuit or the branch processing circuit when calculating the inner product;

in one alternative, the sets of shared vectors come from an on-chip cache when computing the inner product;

in one alternative, the sets of shared vectors come from registers when computing the inner product;

in one alternative, in calculating the inner product, the other unshared vector of each group is broadcast or distributed from the main processing circuit or the branch processing circuit;

in one alternative, in computing the inner product, the other unshared vector of each group is from the slave on-chip cache;

in one alternative, the other unshared vector of each group comes from a register when calculating the inner product;

in one alternative, when performing inner product operation of multiple groups, each group of shared vectors keeps any number of parts in an on-chip cache and/or a register of the basic processing circuit;

in one alternative, the shared vector may be reserved one for each set of inner products;

in one alternative, the shared vector may be reserved only one copy;

specifically, the results of the multiple sets of inner product operations may be accumulated in an on-chip cache and/or a register, respectively;

specifically, the result of each group of inner product operations can be directly transmitted as a result without accumulation;

referring to FIG. 1a, the architecture includes a main processing circuit (which can perform vector operations) and multiple basic processing circuits (which can perform inner product operations). The benefits of such a combination are: the device can not only use the basic processing circuit to execute matrix and vector multiplication operation, but also use the main processing circuit to execute other arbitrary vector operation, so that the device can complete more operations more quickly under the configuration of limited hardware circuit, thereby reducing the times of data transmission with the outside of the device, improving the calculation efficiency and reducing the power consumption. In addition, the chip may be provided with a first mapping circuit in the main processing circuit to execute processing of data in the neural network, for example, first input data smaller than or equal to a preset threshold is removed, and at the same time, mark mask data associated with the first input data may be obtained, where the mask data is used to indicate whether an absolute value of the first input data is greater than the preset threshold. For details, reference may be made to the foregoing embodiments, which are not described herein again. The design has the advantages of reducing the data volume transmitted to the basic processing circuit, reducing the calculation amount of the basic processing circuit data, improving the data processing speed and reducing the power consumption.

A second mapping circuit may be provided in the base processing circuit to perform processing of data in the neural network, such as processing the second input data according to mask data associated with the first input data or selecting the first input data and the second input data having absolute values greater than a preset threshold according to mask data associated with the first input data and mask data associated with the second input data to perform corresponding arithmetic operations, and so on. For the specific processing of the data by the first mapping circuit and the second mapping circuit, reference may be made to the following detailed description.

Optionally, the first mapping circuit and the second mapping circuit are both used for processing data, and may be specifically designed into any one or more of the following circuits: a main processing circuit, a branch processing circuit, a base processing circuit, and the like. Therefore, the data calculation amount can be reduced when the neural network calculation is carried out, and the chip can dynamically allocate which circuit converts the data type according to the calculation amount (namely the load amount) of each circuit (mainly a main processing circuit and a basic processing circuit), so that the complex program of the data calculation can be reduced, the power consumption can be reduced, and the dynamic allocation data processing can be realized without influencing the calculation efficiency of the chip. The manner of this assignment includes, but is not limited to: load balancing, load minimum distribution, and the like.

Referring to the apparatus shown in FIG. 1b, the apparatus shown in FIG. 1b is a computing apparatus in which branch processing circuits are individually connected to a base processing circuit, such as the apparatus shown in FIG. 1b, which includes: a main processing circuit and N basic processing circuits, where the main processing circuit (a specific structure is shown in fig. 1 c) and the N basic processing circuits may be directly or indirectly connected, for example, in an indirect connection manner, an optional scheme may include, as shown in fig. 1a, N/4 branch processing circuits, each branch processing circuit is connected to 4 basic processing circuits, and for the circuits included in the main processing circuit and the N basic processing circuits, reference may be made to the description shown in fig. 1a, which is not described herein again, where it is to be noted that the basic processing circuits may also be disposed in the branch processing circuits, and in addition, the number of the basic processing circuits connected to each branch processing circuit may also be not limited to 4, and a manufacturer may configure the basic processing circuits according to actual needs. The main processing circuit and the N/4 branch processing circuits may be respectively designed with a first mapping circuit and a second mapping circuit, specifically, the main processing circuit may include the first mapping circuit, and the N/4 branch processing circuits or a part thereof includes the second mapping circuit; the main processing circuit may include a first mapping circuit and a second mapping circuit, and the N/4 branch processing circuits or a part thereof may include a first mapping circuit and a second mapping circuit. The main processing circuit may dynamically allocate an operation entity of a data compression processing step according to the neural network computation instruction, specifically, the main processing circuit may determine whether to execute the data compression processing step on the received data according to its own load, specifically, a value of the load may be set to a plurality of intervals, each interval corresponds to an execution subject of the data compression processing step, for example, 3 intervals are taken as an example, a load value of an interval 1 is lower, and N basic processing circuits may execute the data compression processing step. The main processing circuit performs the data compression processing step independently, the section 2 load value is between the section 1 and the section 3, the main processing circuit can perform the data compression processing step independently, the section 3 load value is higher, and the main processing circuit or the N/4 branch processing circuits can perform the data compression processing step together. In this regard, the processing may be performed in an explicit manner, for example, the main processing circuit may be configured with a special instruction or instruction, and when the branch processing circuit receives the special instruction or instruction, the branch processing circuit determines to perform the data compression processing step, for example, when the branch processing circuit does not receive the special instruction or instruction, the branch processing circuit determines not to perform the data compression processing step. As another example, the compression may be performed in an implied manner, for example, when the branch processing circuit receives sparse data (i.e. containing 0, or containing more than a preset number of data smaller than a preset threshold value) and determines that the inner product operation needs to be performed, the branch processing circuit compresses the sparse data.

The data compression processing to which the present application relates is specifically performed in the first mapping circuit and the second mapping circuit described above. It should be understood that, since the neural network is an algorithm with high computation amount and high memory access, the more the weight is, the more the computation amount and the memory access amount are increased. Particularly, in the case of a small weight (e.g. 0, or a weight smaller than a set value), the data with a small weight needs to be compressed to increase the calculation rate and reduce the overhead. In practical application, the data compression processing is applied to the sparse neural network, and the effect is most obvious, such as reducing the workload of data calculation, reducing the data overhead, improving the data calculation rate and the like.

The specific embodiment related to the data compression processing is explained by taking input data as an example. The input data includes, but is not limited to, at least one input neuron and/or at least one weight.

In a first embodiment:

after the first mapping circuit receives first input data (specifically, a data block to be calculated, such as a distribution data block or a broadcast data block, sent by the main processing circuit), the first mapping circuit may process the first input data to obtain identification mask data associated with the processed first input data by the first input data, where the mask data is used to indicate whether an absolute value of the first input data is greater than a first threshold, such as 0.5, 0, or the like.

Specifically, when the absolute value of the first input data is greater than a first threshold, the input data is retained; otherwise, deleting the first input data or setting the first input data to be 0. E.g. inputtedThe matrix data block is

The first threshold is 0.05, and the processed matrix data block can be obtained after the processing of the first mapping circuit

The identification data block (also called mask matrix) associated with the matrix data block is

Further, in order to reduce the data transmission amount, when the main processing circuit distributes data to the basic processing circuit connected to the main processing circuit, the target data (in this case, 1,0.06, and 0.5) in the processed matrix data block and the identification data block associated with the matrix data block may be sent. In a specific implementation, the main processing circuit may distribute the target data in the processed matrix data block to the basic processing circuit according to a set rule, for example, the target data is sequentially sent according to a row order or sequentially sent according to a column order, and the like, which is not limited in this application. Accordingly, after receiving the target data and the identification data block associated with the target data, the basic processing circuit restores the target data and the identification data block to the processed matrix data block according to a set rule (for example, a row sequence). For example, in this example, the base processing circuit may be based on the received data (1,0.06 and 0.5) and the identification data block

The matrix data block corresponding to the data (i.e. the matrix data block processed by the first mapping circuit in the main processing circuit) can be known as

In an embodiment of the present invention, the first input data may be a distribution data block and/or a broadcast data block.

Correspondingly, the second mapping circuit can process the second input data by using the identification data associated with the first input data, thereby obtaining the processed second input data; wherein the first input data is different from the second input data. For example, when the first input data is at least one weight, then the second input data may be at least one input neuron; alternatively, when the first input data is at least one input neuron, then the second input data may be at least one weight.

In an embodiment of the present invention, the second input data is different from the first input data, and the second input data may be any one of the following: distribution data blocks, basic data blocks, broadcast data blocks, and partial broadcast data blocks.

For example, when the first input data is a distribution data block, then the second input data is a partial broadcast data block. Assuming the second input data as a matrix data block

Using mask matrix in the above example accordingly

After processing, obtaining a processed partial broadcast data block as

Since the dimension of the matrix data block related to the input data is large in practical application, the present application is only illustrative and should not be construed as limiting.

In a second embodiment:

the first mapping circuit may be configured to process first input data and second input data to obtain processed first input data and first identification mask data associated with the first input data, processed second input data and second identification mask data associated with the second input data. Wherein, the first mask data or the second mask data is used to indicate whether the absolute value of the first or the second input data is greater than a second threshold, and the second threshold is set by the user side or the device side in a self-defined way, such as 0.05, 0, etc.

The processed first input data or the second input data may be processed input data or unprocessed input data. For example, the first input data is a distribution data block, such as a matrix data block as in the above example

The processed distribution data block can be obtained after being processed by the first mapping circuit, and the processed distribution data block can be an original matrix data block

Or the compressed matrix data block

It should be understood that, in order to reduce the transmission of data amount and the data processing efficiency in the basic processing circuit, it is preferable that the processed input data (such as the processed basic data block or the partial broadcast data block) should be the compressed data. Preferably, the data sent by the main processing circuit to the basic processing circuit may specifically be target data in the processed input data, and the target data may specifically be data whose absolute value is greater than a preset threshold, and may also be non-0 data, and the like.

Correspondingly, in the basic processing circuit, the second mapping circuit may obtain connection identification data according to the first identification data associated with the first input data and the second identification data associated with the second input data; the connection identification data is used to indicate data whose absolute value is greater than a third threshold in the first input data and the second input data, where the third threshold is set by a user or a device in a user-defined manner, such as 0.05, 0, or the like. Further, the second mapping circuit may process the received first input data and the second input data according to the connection identification data, respectively, so as to obtain processed first input data and processed second input data.

For example, the first input data is a matrix data block

The second input data block is likewise a matrix data block

After being processed by the first mapping circuit, the first identification data block related to the first input data can be obtained

And a processed first input data block

Correspondingly obtaining a second identification data block associated with the second input data

The second input data block after processing is

Correspondingly, in order to improve the data transmission rate, only the target data 1,0.06 and 0.5 in the processed first input data block and the first identification data block associated with the first input data block can be sent to the basic processing circuit in the main processing circuit; meanwhile, the target data 1,1.1,0.6,0.3 and 0.5 in the processed second input data block and a second identification data block associated with the second input data block are sent to the branch processing circuit or the basic processing circuit.

Correspondingly, after receiving the data, the branch/base processing circuit may perform element-by-element and operation on the first identification data block and the second identification data block through the second mapping circuit to obtain a connection identification data block

Correspondingly, the second mapping circuit respectively processes the processed first input data block and the processed second input data block by using the connection identification data block, so as to obtain the processed first input data block as

The second input data block after processing is

The branch/basic processing circuit can determine a first data block (i.e. the first data block processed by the first mapping circuit) corresponding to the target data according to the first identification data block and the received target data in the first data block; correspondingly, according to the second identification data block and the received target data in the second data block, determining a second data block (namely, the second data block processed by the first mapping circuit) corresponding to the target data; then, after the second mapping circuit learns the connection identification data block, the connection identification data block is used to perform element-by-element and operation with the determined first data block and the determined second data block respectively, so as to obtain the first data block processed by the second mapping circuit and the processed second data block.

In the third embodiment:

the first mapping circuit is not arranged in the main processing circuit, but the main processing circuit can send third input data and third identification data which is pre-stored and associated with the third input data to a basic processing circuit connected with the main processing circuit. A second mapping circuit is provided in the branch/base processing circuit. A specific example of the data compression process involved in the second mapping circuit is set forth below.

It should be understood that the third input data includes, but is not limited to, a basic data block, a partial broadcast data block, a broadcast data block, and the like. Similarly, in the neural network processor, the third input data may also be at least one weight, and/or at least one input nerve, which is not limited in this application.

In the second mapping circuit, the second mapping circuit may process the third input data according to third identification data associated with the received third input data, so as to obtain processed third input data, so as to subsequently perform a correlation operation, such as an inner product operation, on the processed third input data.

For example, the third input data received by the second mapping circuit is a matrix data block

A third identification data block (also referred to as a mask matrix data block) associated with the third input data, which is prestored correspondingly

Further, the second mapping circuit processes the third input data block according to the third identification data block to obtain a processed third input data block, which is specifically the processed third input data block

In addition, the input neurons and the output neurons mentioned in the embodiments of the present invention do not refer to neurons in the input layer and neurons in the output layer of the entire neural network, but for any two adjacent layers of neurons in the neural network, the neurons in the lower layer of the network feedforward operation are input neurons, and the neurons in the upper layer of the network feedforward operation are output neurons.

In the fourth embodiment:

the main processing circuit is not provided with a mapping circuit, and the basic processing circuit is provided with a first mapping circuit and a second mapping circuit. For data processing of the first mapping circuit and the second mapping circuit, reference may be made to the foregoing first embodiment to the third embodiment, which are not described herein again.

Alternatively, a fifth embodiment is also present. In a fifth embodiment, the branch/base processing circuit is not provided with a mapping circuit, and both the first mapping circuit and the second mapping circuit are provided in the main processing circuit, and for data processing of the first mapping circuit and the second mapping circuit, reference may be specifically made to the descriptions of the first embodiment to the third embodiment, and details thereof are not repeated here. That is, the main processing circuit completes the compression processing of data, and sends the processed input data to the branch/base processing circuit, so that the base processing circuit performs corresponding operation operations using the processed input data (specifically, the processed neurons and the processed weights).

The following sets forth a specific structural schematic diagram of the present application relating to a mapping circuit. Two possible mapping circuits are shown in fig. 5a and 5 b. Wherein the mapping circuit as shown in fig. 5a comprises a comparator and a selector. The present application is not limited with respect to the number of comparators and selectors. Fig. 5a shows a comparator and two selectors, wherein the comparator is used to determine whether the input data meets the preset condition. The preset condition may be set by a user or a device, for example, an absolute value of the input data is greater than or equal to a preset threshold. If the preset condition is met, the comparator can determine that the input data is allowed to be output, and the input data corresponds to the associated identification data and is 1; otherwise, it may be determined not to output the input data, or to default the input data to 0. Accordingly, the input data is 0 corresponding to the associated identification data at this time. That is, after passing through the comparator, the identification data associated with the input data can be known.

Further, after the comparator determines the preset condition for the input data, the obtained identification data may be input to the selector, so that the selector uses the identification data to determine whether to output the corresponding input data, that is, to obtain the processed input data.

As shown in fig. 5a, taking the input data as a matrix data block as an example, each data in the matrix data block may be determined by a comparator according to a preset condition, so that an identification data block (mask matrix) associated with the matrix data block may be obtained. Further, the matrix data block can be screened by the identification data block in the first selector, data with an absolute value greater than or equal to a preset threshold (that is, meeting a preset condition) in the matrix data block is retained, and the rest of data is deleted to output the processed matrix data block. Optionally, the second selector may further process other input data (e.g., a second matrix data block) by using the identification data block, for example, perform an element-by-element and operation to reserve data whose absolute value is greater than or equal to a preset threshold in the second matrix data block, so as to output the processed second matrix data block.

It should be understood that, corresponding to the first and second embodiments described above, the specific structure of the first mapping circuit may include at least one comparator and at least one selector, such as the comparator and the first selector in fig. 5a in the above example; the specific result of the second mapping circuit may comprise one or more selectors, such as the second selector of fig. 5a in the example above.

Fig. 5b shows a schematic diagram of another mapping circuit. As shown in fig. 5b, the mapping circuit includes selectors, and the number of the selectors is not limited, and may be one or more. Specifically, the selector is configured to select the input data according to identification data associated with the input data, so as to output data, of which an absolute value is greater than or equal to a preset threshold, from the input data, and delete/not output the remaining data, thereby obtaining processed input data.

Taking the input data as a matrix data block as an example, the matrix data block and an identification data block associated with the matrix data block are input to the mapping circuit, the selector can select the matrix data block according to the identification data block, output data of which the absolute value is greater than or equal to 0, and output no other data, thereby outputting the processed matrix data block.

It will be appreciated that the structure shown in fig. 5b may be applied to the second mapping circuit in the third embodiment described above, i.e. the specific result of the second mapping circuit in the third embodiment described above may comprise at least one selector. Similarly, the first mapping circuit and the second mapping circuit designed in the main processing circuit and the basic processing circuit may be cross-combined or split according to the functional components shown in fig. 5a and 5b, and the present application is not limited thereto.

The following provides a possible method for implementing the calculation by using the apparatus shown in fig. 1a, and the method for implementing the calculation may specifically be a calculation manner of a neural network, such as a forward operation of the neural network, and a training of the neural network, in practical applications, the forward operation may perform matrix multiplication, convolution, activation, transformation, and the like according to different input data, and all the operations may be implemented by using the apparatus shown in fig. 1 a.

The first mapping circuit of the main processing circuit compresses data to be calculated, and then the data is transmitted to the branch processing circuit by the control circuit; the branch processing circuit can control whether to start the second mapping circuit to process the data according to the operation of the data so as to transmit the processed data to the basic processing circuit for operation.

The main processing circuit transmits data to be calculated to all or a part of basic processing circuits; taking the matrix multiplied by the vector calculation as an example, the control circuit of the main processing circuit may split each column of matrix data into one basic data, for example, an m × n matrix, and may split the matrix data into n vectors of m rows, and the control circuit of the main processing circuit distributes the split n vectors of m rows to a plurality of branch processing circuits, and the branch processing circuits send the split vectors to a corresponding plurality of basic processing circuits. For vectors, the control circuitry of the main processing circuitry may broadcast the vector as a whole to each branch processing circuitry. If the value of m is relatively large, the control circuit may first split the m × n matrix into x × n vectors, taking x as an example, 2, specifically, 2n vectors, each vector including m/2 rows, that is, each vector in n m rows is equally divided into 2 vectors, taking the first vector as an example, for n m rows, the first vector is 1000 rows, then equally divided into 2 vectors may be that the first 500 rows are grouped into the first vector, the last 500 rows are grouped into the second vector, and the control circuit broadcasts the 2 vectors to the branch processing circuits through 2 broadcasts, and then sends the vectors to the basic processing circuits.

The data transmission mode can be broadcasting or distribution, or any other possible transmission mode;

after receiving the data, the basic processing circuit executes operation to obtain an operation result;

the basic processing circuit transmits the operation result back to the main processing circuit;

the operation result may be an intermediate operation result or a final operation result.

The operation of multiplying the tensor, which is the same as the data block described above, can be performed by using the apparatus shown in fig. 1a, and the tensor can be any one or a combination of a matrix, a vector, a three-dimensional data block, a four-bit data block and a high-dimensional data block; the following shows a specific implementation of the matrix-by-vector and matrix-by-matrix operations, respectively, as shown in fig. 2 and 2 b.

The operation of multiplying the vector by the matrix is completed by using the device shown in FIG. 1 a;

(the matrix multiplication vector can be that each row in the matrix is respectively subjected to inner product operation with the vector, and the results are arranged into a vector according to the sequence of the corresponding rows.)

The following describes the operation of calculating multiplication of a matrix S with size M rows and L columns and a vector P with length L, as shown in fig. 2a below (each row in the matrix S has the same length as the vector P, and data in the matrix S corresponds to the vector P in a position-to-position manner), where the neural network calculation apparatus has K basic processing circuits (or K branch processing circuits), and the following is detailed by taking the basic processing circuit as an example:

referring to fig. 2, fig. 2 provides a method for implementing matrix multiplication vector, which may specifically include:

step S201, a first mapping circuit of the main processing circuit compresses each row of data in the input matrix S to obtain a compressed matrix S and a first identification matrix (mask matrix) associated with the input matrix S, a control circuit of the main processing circuit distributes data in the compressed matrix S and the first identification matrix to one of K basic processing circuits, and the basic processing circuits store the received distributed data in an on-chip cache and/or a register of the basic processing circuits;

specifically, the first mapping circuit performs compression processing on the input matrix S to obtain a compressed matrix S. For example, data corresponding to the data in the input matrix S and the matrix P being the designated value (e.g., 0) and/or the absolute value being less than or equal to the preset threshold (e.g., 0.1) is removed, and in a specific implementation, the data in the matrix S/P at the same position corresponding to the data in the matrix S and the matrix P being removed may be removed according to the mask matrix corresponding to the matrix S and the matrix P, for example, refer to the related explanation in the foregoing data compression processing embodiment, and no further description is given here. It should be understood that the matrix S and the matrix P may be understood as input neurons (also referred to as input neuron matrices), weights (also referred to as weight matrices), and the like in the foregoing embodiments.

When the main processing circuit sends data to the basic processing circuit, the main processing circuit specifically sends the data with the absolute value larger than the preset threshold value or the non-0 data in the matrix S after the compression processing to the basic processing circuit so as to reduce the data transmission quantity.

In an alternative, if the number M of rows of the matrix S < ═ K, the control circuit of the main processing circuit distributes, to the K basic processing circuits, one row of the S matrix and the row of the first mask matrix associated therewith, respectively; for example, the matrix S is 2 × 2, the control circuit sends data of a first row in the matrix S to the first basic processing circuit, and simultaneously, needs to send mask data of the first row in the mask matrix associated with the matrix S to the first basic processing circuit.

In an alternative, if the number of rows M > K of the matrix S, the control circuit of the main processing circuit distributes to each basic processing circuit the data of one or more rows in the matrix S and the identification data of the corresponding row or rows in the first mask matrix, respectively.

The set of rows in S distributed to the ith basic processing circuit is Ai, and there are Mi rows in total, as fig. 2c shows the calculations to be performed on the ith basic processing circuit. Correspondingly, the identification matrix distributed to the ith basic processing circuit and correspondingly associated with the set Ai is Bi, and is greater than or equal to Mi rows.

In one alternative, in each basic processing circuit, for example, in the ith basic processing circuit, the received dispatch data and the identification data associated with the dispatch data, for example, the matrix Ai and the identification mask matrix Bi associated with the Ai, may be stored in a register and/or an on-chip cache of the ith basic processing circuit; the method has the advantages of reducing the data transmission quantity of the subsequent distribution data, improving the calculation efficiency and reducing the power consumption.

Step S202, a first mapping circuit of a main processing circuit compresses an input vector P to obtain a compressed vector P and a second identification matrix (mask vector) associated with the input vector P, and a control circuit of the main processing circuit transmits the compressed vector P and each part in the second identification matrix to K basic processing circuits in a broadcast manner; for the compression processing of the input vector P and the data transmission of the compressed vector P, reference may be specifically made to the relevant explanation of step S201, and details are not described here again.

In an alternative, the control circuit of the main processing circuit may broadcast the vector P (specifically, the compressed vector P) and each part in the second identification matrix only once to the register or on-chip buffer of each basic processing circuit, and the ith basic processing circuit fully multiplexes the data of the vector P obtained this time, thereby completing the inner product operation corresponding to each row in the matrix Ai. The method has the advantages of reducing the data transmission quantity of repeated transmission of the vector P from the main processing circuit to the basic processing circuit, improving the execution efficiency and reducing the transmission power consumption.

In an alternative, the control circuit of the main processing circuit may broadcast the vector P and each part in the second identification matrix to the register or on-chip cache of each basic processing circuit for multiple times, and the ith basic processing circuit does not multiplex the data of the vector P obtained each time, and completes the inner product operation corresponding to each row in the matrix Ai for multiple times; the method has the advantages of reducing the data transmission quantity of the vector P of single transmission in the basic processing circuit, reducing the capacity of the cache and/or the register of the basic processing circuit, improving the execution efficiency, reducing the transmission power consumption and reducing the cost.

In an alternative, the control circuit of the main processing circuit may broadcast the vector P and each part in the second identification matrix to the register or on-chip cache of each basic processing circuit for multiple times, and the ith basic processing circuit performs partial multiplexing on the data of the vector P obtained each time, and completes the inner product operation corresponding to each row in the matrix Ai; the method has the advantages of reducing the data transmission quantity from the main processing circuit to the basic processing circuit, reducing the data transmission quantity in the basic processing circuit, improving the execution efficiency and reducing the transmission power consumption.

Step S203, calculating the inner product of the matrix S and the data of the vector P by an inner product arithmetic circuit of K basic processing circuits, for example, the ith basic processing circuit, calculating the inner product of the data of the matrix Ai and the data of the vector P;

specifically, a second mapping circuit in the K basic processing circuits obtains a relationship identifier matrix according to the data in the first identifier matrix and the data in the second identifier matrix received by the second mapping circuit; and then calculating the inner product operation of the vector P and the data in the matrix S by using the relation identification matrix. For example, the ith basic processing circuit obtains a relation connection matrix by using the identification matrix Bi of the matrix Ai and the second identification matrix of the vector P; and then, the matrix Ai and the vector P are respectively processed by utilizing the correlation connection matrix to obtain the processed matrix Ai and the processed vector P, for example, the correlation identification matrix is utilized to select the data which is not 0 at the same position from the matrix Ai and the vector P, and then the inner product between the data which is not 0 is calculated by utilizing an inner product arithmetic circuit.

It should be noted that, in the embodiment of the present invention, the function of the basic processing circuit in step S203 may also be implemented in the branch processing circuit. That is, the control circuit of the main processing circuit may also send the processed data in the matrix S and the identification data in the first identification matrix to the k branch processing circuits. Accordingly, the processed data in the matrix P and the identification data in the second identification matrix are sent to the k branch processing circuits. Each branch processing circuit can obtain a relation identification matrix according to the received identification data in the first identification matrix and the received identification data in the second identification matrix; then, the relationship identifier matrix is used to process the received data in the matrix S and the data in the matrix P, and the processed matrix S and the processed matrix P are sent to the basic processing circuit connected to the branch processing circuit, so as to calculate the inner product of the processed matrix S and the data in the matrix P by using the inner product operator circuit of the basic processing circuit.

And S204, accumulating the results of the inner product operation by the accumulator circuits of the K basic processing circuits to obtain accumulated results, and transmitting the accumulated results back to the main processing circuit.

In an alternative, the partial sums (i.e., a portion of the accumulated result, e.g., F1G 1+ F2G 2+ F3G 3+ F4G 4+ F5G 5, then the partial sums may be the values of F1G 1+ F2G 2+ F3G 3) resulting from each inner product operation performed by the basic processing circuit may be transmitted back to the main processing circuit for accumulation; the method has the advantages of reducing the internal operation amount of the basic processing circuit and improving the operation efficiency of the basic processing circuit.

In an alternative, the partial sum obtained by the inner product operation executed by the basic processing circuit each time can be stored in a register and/or an on-chip cache of the basic processing circuit, and the partial sum is transmitted back to the main processing circuit after the accumulation is finished; the method has the advantages of reducing the data transmission quantity between the basic processing circuit and the main processing circuit, improving the operation efficiency and reducing the data transmission power consumption.

In an alternative, the partial sum obtained by the inner product operation executed by the basic processing circuit each time is stored in a register and/or an on-chip cache of the basic processing circuit for accumulation in partial cases, and is transmitted to the main processing circuit for accumulation in partial cases, and is transmitted back to the main processing circuit after the accumulation is finished; the method has the advantages of reducing the data transmission quantity between the basic processing circuit and the main processing circuit, improving the operation efficiency, reducing the data transmission power consumption, reducing the operation quantity in the basic processing circuit and improving the operation efficiency of the basic processing circuit.

Referring to FIG. 2b, the matrix multiplication operation is performed using the apparatus shown in FIG. 1 a;

the following describes the operation of calculating the multiplication of a matrix S of size M rows and L columns and a matrix P of size L rows and N columns, (each row in matrix S being the same length as each column of matrix P, as shown in fig. 2 d) the neural network computing device possesses K basic processing circuits:

step S201b, the control circuit of the main processing circuit distributes each row of data in the matrix S and the identification data corresponding to and associated with the first identification matrix to one of K basic processing circuits, and the basic processing circuits store the received data in the on-chip cache and/or the register; the first identifier matrix is an identifier matrix of the matrix S, and may be pre-stored or obtained through processing by the first mapping circuit, which is not limited in this application.

In an alternative, the matrix S is a matrix obtained after a compression process. Specifically, the first mapping circuit of the main processing circuit compresses the input matrix S to correspondingly obtain the compressed matrix S and the first identifier matrix associated with the input matrix S. For the compression process of the data, reference may be made to the related explanations in the foregoing embodiments, and details are not repeated here.

In an alternative, if the number M of rows of S < ═ K, the control circuit of the main processing circuit distributes, to the M basic processing circuits, one row of the S matrix and the row of the first mask matrix associated therewith, respectively;

in an alternative, if the number of rows M > K of S, the control circuit of the main processing circuit distributes the data of one or more rows in the S matrix and the identification data of the corresponding row or rows in the first mask matrix to each basic processing circuit, respectively.

In S, Mi rows are distributed to the ith basic processing circuit, and the set of Mi rows is called Ai, as shown in fig. 2e, which represents the calculation to be performed on the ith basic processing circuit. Correspondingly, the identification matrix distributed to the i-th basic processing circuit and correspondingly associated with the set Ai is Bi, and the number of rows of Bi is greater than or equal to Mi rows.

In one alternative, in each base processing circuit, for example, in the ith base processing circuit: the matrix Ai and the associated identification matrix of the matrix Ai distributed by the main processing circuit are received and stored in the ith basic processing circuit register and/or on-chip cache; the method has the advantages of reducing the subsequent data transmission quantity, improving the calculation efficiency and reducing the power consumption.

Step S202b, the control circuit of the main processing circuit transmits each part in the matrix P and the corresponding associated identification data in the second identification matrix to each basic processing circuit in a broadcasting mode; the second identification data is an identification matrix of the matrix P, which may be pre-stored or obtained by processing by the first mapping circuit.

In an alternative, the matrix P is a compressed matrix. Specifically, the first mapping circuit of the main processing circuit compresses the input matrix P to correspondingly obtain the compressed matrix P and the second identifier matrix associated with the input matrix P. For the compression process of the data, reference may be made to the related explanations in the foregoing embodiments, and details are not repeated here.

In an alternative, each part in the matrix P and the identification data correspondingly associated in the second identification matrix may be broadcast only once to the register or on-chip buffer of each basic processing circuit, and the ith basic processing circuit fully multiplexes the data of the matrix P obtained this time, thereby completing the inner product operation corresponding to each row in the matrix Ai; the multiplexing in this embodiment may be specifically that the basic processing circuit is repeatedly used in the calculation, for example, the multiplexing of the data of the matrix P may be that the data of the matrix P is used multiple times.

In an alternative, the control circuit of the main processing circuit may broadcast each part of the matrix P and the identification data associated correspondingly in the second identification matrix to the registers or on-chip caches of the respective basic processing circuits for multiple times, and the ith basic processing circuit does not multiplex the data of the matrix P obtained each time, and completes the inner product operation corresponding to each row of the matrix Ai in multiple times;

in an alternative, the control circuit of the main processing circuit may broadcast each part of the matrix P and the identification data associated correspondingly in the second identification matrix to the registers or on-chip buffers of each basic processing circuit for multiple times, and the ith basic processing circuit performs partial multiplexing on the data of the matrix P obtained each time, and completes the inner product operation corresponding to each row in the matrix Ai;

in one alternative, the inner product operator of each basic processing circuit calculates the inner product of the data of matrix S and matrix P, for example, the i-th basic processing circuit calculates the inner product of the data of matrix Ai and the data of matrix P;

specifically, each basic processing circuit may obtain a relationship identifier matrix according to the received data of the first identifier matrix and the received data of the second identifier matrix, process the data of the matrix S and the matrix P by using the relationship identifier matrix, and perform inner product operation on the processed data of the matrix S and the processed data of the matrix P. For example, the ith basic processing circuit obtains a relation connection matrix by using the identification matrix Bi associated with the matrix Ai and the second identification matrix associated with the matrix P; and then, the matrix Ai and the matrix P are respectively processed by utilizing the correlation connection matrix to obtain the processed matrix Ai and the processed matrix P, for example, the correlation identification matrix is utilized to select data which is not 0 at the same position from the matrix Ai and the matrix P, and then an inner product arithmetic circuit is utilized to calculate the inner product of the data of the processed matrix Ai and the processed matrix P.

In the embodiment of the present invention, the data processing function in the basic processing circuit may be implemented in the branch processing circuit. That is, the control circuit of the main processing circuit may also send the processed data in the matrix S and the identification data in the first identification matrix to the k branch processing circuits. Accordingly, the processed data in the matrix P and the identification data in the second identification matrix are sent to the k branch processing circuits. Each branch processing circuit can obtain a relation identification matrix according to the received identification data in the first identification matrix and the received identification data in the second identification matrix; then, the relationship identifier matrix is used to process the received data in the matrix S and the data in the matrix P, and the processed matrix S and the processed matrix P are sent to the basic processing circuit connected to the branch processing circuit, so as to calculate the inner product of the processed matrix S and the data in the matrix P by using the inner product operator circuit of the basic processing circuit.

In step S203b, the accumulator circuit of each basic processing circuit accumulates the result of the inner product operation and transmits it back to the main processing circuit.

In one alternative, the base processing circuit may transmit the partial sums obtained by performing the inner product operation each time back to the main processing circuit for accumulation;

in an alternative, the partial sum obtained by the inner product operation executed by the basic processing circuit each time can be stored in a register and/or an on-chip cache of the basic processing circuit, and the partial sum is transmitted back to the main processing circuit after the accumulation is finished;

in an alternative, the partial sum obtained by the inner product operation performed by the basic processing circuit each time may be stored in a register and/or an on-chip buffer of the basic processing circuit in some cases for accumulation, and transmitted to the main processing circuit for accumulation in some cases, and transmitted back to the main processing circuit after the accumulation is finished.

Referring to FIG. 3a, a full join operation is performed using the apparatus shown in FIG. 1 a:

if the input data of the fully-connected layer is a vector (namely the input of the neural network is the case of a single sample), taking the weight matrix of the fully-connected layer as a matrix S and the input vector as a vector P, and performing the matrix multiplication vector operation as shown in FIG. 2 according to the first using method of the device;

if the input data of the fully connected layer is a matrix (i.e. the input of the neural network is the case of multiple samples as the batch), then the weight matrix of the fully connected layer is used as the matrix S and the input vector is used as the matrix P, or the weight matrix of the fully connected layer is used as the matrix P and the input vector is used as the matrix S, and the execution operation of the matrix multiplication matrix shown in fig. 2c is performed according to the device;

referring to FIG. 3b, the convolution operation is performed using the apparatus shown in FIG. 1 a:

for a convolution layer, recording the number of convolution kernels as M;

step S301, a control circuit of a main processing circuit distributes the weight of each convolution kernel in the convolution layer weight and correspondingly associated identification data in a first identification matrix to one of K basic processing circuits, and stores the weight and the identification data in an on-chip cache and/or a register of the basic processing circuits; the first identification matrix is an identification matrix of the convolutional layer weight, and can be pre-stored or obtained by processing through a first mapping circuit in the main processing circuit.

In an alternative, the weight of each convolution kernel in the convolutional layer weights is a weight obtained after compression processing. Specifically, the first mapping circuit of the main processing circuit compresses the weight of each convolution kernel in the convolutional layer weights to obtain the weight of each convolution kernel in the convolutional layer weights after compression and the first identifier matrix associated with the convolutional layer weights. For the compression process of the data, reference may be made to the related explanations in the foregoing embodiments, and details are not repeated here.

In an alternative scheme, if the number M < ═ K of convolution kernels, the control circuit of the main processing circuit distributes a weight of one convolution kernel and identification data associated with the convolution kernel in the first identification matrix to the M basic processing circuits respectively;

in an alternative, if the number M > K of convolution kernels, the control circuit of the main processing circuit distributes the weight values of one or more convolution kernels and one or more rows of associated identification data of the convolution kernels in the first identification matrix to each basic processing circuit respectively.

There are a total of Mi convolution kernels distributed to the ith base processing circuit, and the set of these convolution kernel weights is called Ai. Correspondingly, the identification data associated in the first identification matrix corresponding to each of the Mi convolution kernels is also distributed to the ith basic processing circuit, and the set of the identification data in the identification matrices can be called Bi, that is, Ai corresponds to the associated identification matrix Bi.

In one alternative, in each base processing circuit, for example, in the ith base processing circuit: storing the received convolution kernel weight Ai distributed by the main processing circuit and the identification matrix Bi corresponding to the Ai in a register and/or an on-chip cache of the main processing circuit;

step S302, the control circuit of the main processing circuit transmits each part in the input data P and the corresponding associated identification data in the second identification matrix to each basic processing circuit in a broadcasting mode;

in one alternative, the input data P is input neurons obtained after a compression process. Specifically, the first mapping circuit of the main processing circuit compresses the input data P to obtain the compressed input data P and the identification data associated with the input data P, and then transmits each part of the compressed input data P and the identification data associated with the compressed input data P to each basic processing circuit in a broadcast manner by using the control circuit. For the compression process of the data, reference may be made to the related explanations in the foregoing embodiments, and details are not repeated here.

In an alternative, the control circuit of the main processing circuit may broadcast each part of the input data P and the corresponding associated identification data only once to the register or on-chip cache of each basic processing circuit, and the ith basic processing circuit fully multiplexes the data of the input data P obtained this time, and completes the inner product operation corresponding to each convolution kernel in Ai;

in an alternative, the control circuit of the main processing circuit may broadcast each part of the input data P and the identification data associated with each part for multiple times to the register or on-chip cache of each basic processing circuit, and the ith basic processing circuit does not multiplex the data of the input data P obtained each time, and completes the inner product operation corresponding to each convolution kernel in Ai in multiple times;

step S303, each basic processing circuit calculates a data inner product of the convolution kernel and the input data P, for example, the ith basic processing circuit calculates an inner product of each convolution kernel of Ai and the data of the input data P;

specifically, the second mapping circuit in each basic processing circuit obtains a relational connection matrix according to the received identification data associated with the convolution kernel (i.e., the identification data in the first identification matrix) and the identification data associated with the input data P (i.e., the identification data in the second identification matrix), processes the received convolution kernel and the input data by using the relational connection matrix, and performs inner product operation on the processed convolution kernel and the processed input data. For example, the ith basic processing circuit obtains a relation connection matrix by using the identification matrix Bi associated with the convolution kernel Ai and the second identification matrix (i.e. identification data) associated with the input data P; and then, the matrix Ai and the input data P are respectively processed by utilizing the correlation connection matrix to obtain the processed matrix Ai and the processed input data P, for example, the data which is not 0 at the same position is selected from the matrix Ai and the input data P by utilizing the correlation identification matrix, and then the inner product between the data which is not 0 is calculated by utilizing an inner product arithmetic circuit.

In the embodiment of the present invention, the data processing function in the basic processing circuit may be implemented in the branch processing circuit. That is, the control circuit of the main processing circuit may also send the weight of the processed convolution kernel and the identification data associated with the convolution kernel to the k branch processing circuits; the processed input data P and the corresponding associated identification data are sent to the k branch processing circuits. Accordingly, the branch processing circuit may start the second mapping circuit to obtain a relational connection matrix according to the received identification data associated with the convolution kernel (i.e., the identification data in the first identification matrix) and the identification data associated with the input data P (i.e., the identification data in the second identification matrix), then process the received convolution kernel and the input data using the relational connection matrix, and then send the processed convolution kernel and the processed input data to the basic processing circuit connected to the branch processing circuit, so as to perform an inner product operation on the processed convolution kernel and the processed input data, which may be referred to the related explanation of the foregoing embodiments and is not described herein again.

Step S304, the accumulator circuit of each basic processing circuit accumulates the result of the inner product operation and transmits it back to the main processing circuit:

in one alternative, the base processing circuitry may be configured to transmit the partial sum resulting from each inner product operation back to the main processing circuitry for accumulation;

in an alternative, the basic processing circuit may also store the partial sum obtained by the inner product operation performed each time in a register and/or an on-chip cache of the basic processing circuit, and transmit the partial sum back to the main processing circuit after the accumulation is finished;

in an alternative, the basic processing circuit may also store the partial sum obtained by the inner product operation performed each time in a register and/or an on-chip cache of the basic processing circuit for accumulation in some cases, transmit the partial sum to the main processing circuit for accumulation in some cases, and transmit the partial sum back to the main processing circuit after the accumulation is finished;

the invention also provides a chip comprising a computing device, the computing device comprising:

the data involved in the main processing circuit may be compressed data, and in an alternative embodiment, the compressed data includes at least one input neuron or at least one weight value, and each neuron in the at least one neuron is greater than a first threshold value or each weight value in the at least one weight value is greater than a second threshold value. The first threshold and the second threshold are set by a user side in a self-defined way, and can be the same or different.

In one alternative, the main processing circuit includes a first mapping circuit;

in one alternative, the main processing circuit includes an arithmetic unit such as a vector arithmetic unit or the like that performs data compression processing;

specifically, the system comprises a data input interface for receiving input data;

in one alternative, the source of the received data may be: part or all of a basic processing circuit outside the neural network operation circuit device or the neural network operation circuit device;

in one alternative, there may be a plurality of the data input interfaces; specifically, a data output interface that outputs data may be included;

in one alternative, the destination of the output data may be: a part or all of branch processing circuits or basic processing circuits outside the neural network operation device or the neural network operation circuit device;

in one alternative, the number of the data output interfaces may be plural;

in one alternative, the main processing circuitry comprises on-chip caches and/or registers;

in an alternative, the main processing circuit comprises an arithmetic unit which can execute data arithmetic;

in one alternative, an arithmetic operation unit is included in the main processing circuit;

in an alternative, the main processing circuit comprises a vector operation unit which can simultaneously perform operation on a group of data; in particular, the arithmetic operations and/or vector operations may be any type of operations, including but not limited to: two numbers are added, subtracted, multiplied, divided, one number is added, subtracted, multiplied, divided with a constant, an exponential operation, a power operation, a logarithmic operation are performed on one number, and various nonlinear operations, a comparison operation, a logical operation, etc. are performed on two numbers. Two vectors are added, subtracted, multiplied, divided, each element in one vector is added, subtracted, multiplied, divided with a constant, exponential, logarithmic, and various nonlinear operations are performed on each element in one vector, comparison operations, logical operations, and the like are performed on each two corresponding elements in one vector.

In one alternative, the main processing circuit includes a data rearranging unit for transferring data to the base processing circuit in a certain order or rearranging data in place in a certain order;

in one alternative, the order in which the data is arranged includes: carrying out dimension sequence transformation on a multi-dimensional data block; the order of the data arrangement may further include: a block of data is partitioned for transmission to different underlying processing circuits.

The computing device also includes a plurality of basic processing circuits: each basic processing circuit is used for calculating the inner product of two vectors, and the calculation method is that the basic processing circuit receives two groups of numbers, correspondingly multiplies elements in the two groups of numbers, and accumulates the multiplication results; the result of the inner product is transmitted, where it is possible to transmit it to other basic processing circuits, depending on the position of the basic processing circuit, or directly to the main processing circuit.

The data involved in the base processing circuit may be compressed data, and in an alternative embodiment, the compressed data includes at least one input neuron or at least one weight value, each of the at least one neuron is greater than a first threshold value or each of the at least one weight value is greater than a second threshold value. The first threshold and the second threshold are set by a user side in a self-defined way, and can be the same or different.

In one alternative, the base processing circuit includes a second mapping circuit;

in one alternative, the base processing circuit includes a vector operation unit that performs data compression processing;

specifically, the memory unit comprises an on-chip cache and/or a register;

in particular, one or more data input interfaces to receive data;

in one alternative, two data input interfaces are included, one or more data being respectively available from the two data input interfaces at a time;

in one alternative, the base processing circuit may store the input data received from the data input interface in a register and/or an on-chip cache;

the data input interface may receive data from: other basic processing circuitry and/or main processing circuitry.

A main processing circuit of the neural network arithmetic circuit device;

other basic processing circuits of the neural network operation circuit device (the neural network operation circuit device has a plurality of basic processing circuits);

specifically, one or more data output interfaces for transmitting output data are included;

in one alternative, one or more data may be transmitted out of the data output interface;

specifically, the data transmitted through the data output interface may be: one or any combination of data received from the data input interface, data stored in an on-chip cache and/or register, a multiplier operation result, an accumulator operation result or an inner product operator operation result.

In one alternative, the system comprises three data output interfaces, wherein two of the three data output interfaces correspond to two data input interfaces respectively, a layer above each layer is used for outputting data received from the data input interfaces, and the third data output interface is used for outputting an operation result;

specifically, the destination of the data output interface to transmit data may be: the above data sources and the data destinations herein determine the connection relationships of the underlying processing circuitry in the device.

A main processing circuit of the neural network arithmetic circuit device;

a further basic processing circuit of the neural network arithmetic circuit device, the neural network arithmetic circuit device having a plurality of basic processing circuits;

specifically, an arithmetic operation circuit is included: the arithmetic operation circuit may specifically be: one or more multiplier circuits, one or more accumulator circuits, one or more circuits that perform two sets of inner product operations, or any combination thereof.

In an alternative, a multiplication operation of two numbers can be executed, and the result can be stored in an on-chip cache and/or a register or can be directly added into the register and/or the on-chip cache;

in an alternative, an inner product operation of two groups of data can be executed, and the result can be stored in an on-chip cache and/or a register or directly added into the register and/or the on-chip cache;

in one alternative, an accumulation operation of data may be performed, accumulating the data into an on-chip cache and or register;

specifically, the data accumulated by the accumulator circuit may be: one or any combination of data received from the data input interface, data stored in an on-chip cache and/or register, a multiplier operation result, an accumulator operation result, and an inner product operator operation result.

It should be noted that the "data input interface" and the "data output interface" used in the above description of the basic processing circuit refer to the data input and output interface of each basic processing circuit, not the data input and output interface of the whole device.

In one embodiment, the present invention discloses a neural network computing device, which includes functional units for executing all or part of the embodiments provided in the method embodiments described above.

In one embodiment, the present invention discloses a chip for performing all or part of the embodiments provided in the method embodiments described above.

In one embodiment, the invention discloses an electronic device comprising functional units for performing all or part of the embodiments of the method as described above.

Electronic devices include data processing devices, robots, computers, printers, scanners, tablets, smart terminals, cell phones, tachographs, navigators, sensors, cameras, servers, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, vehicles, home appliances, and/or medical devices.

The vehicle comprises an airplane, a ship and/or a vehicle; the household appliances comprise a television, an air conditioner, a microwave oven, a refrigerator, an electric cooker, a humidifier, a washing machine, an electric lamp, a gas stove and a range hood; the medical equipment comprises a nuclear magnetic resonance apparatus, a B-ultrasonic apparatus and/or an electrocardiograph.

The above-described embodiments, objects, technical solutions and advantages of the present disclosure are further described in detail, it should be understood that the above-described embodiments are only illustrative of the embodiments of the present disclosure, and are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.

Claims

1. An integrated circuit chip apparatus, comprising: the system comprises a main processing circuit, k branch processing circuits and k groups of basic processing circuits, wherein the main processing circuit is respectively connected with the k branch processing circuits, each branch processing circuit in the k branch processing circuits corresponds to one group of basic processing circuits in the k groups of basic processing circuits, and the group of basic processing circuits comprises at least one basic processing circuit;

the k groups of basic processing circuits are used for executing operation in a neural network in a parallel mode according to the transmission data or the processed transmission data and transmitting an operation result to the main processing circuit through a branch processing circuit connected with the main processing circuit;

the main processing circuit is used for acquiring a data block to be calculated and an operation instruction, and dividing the data block to be calculated into a distribution data block and a broadcast data block according to the operation instruction; starting the first mapping circuit to process the distribution data block and the broadcast data block to obtain a processed distribution data block, an identification data block associated with the distribution data block, a processed broadcast data block and an identification data block associated with the broadcast data block; splitting the processed distribution data block and the identification data block associated with the distribution data block to obtain a plurality of basic data blocks and identification data blocks associated with the basic data blocks; distributing the plurality of basic data blocks and the identification data blocks associated with the plurality of basic data blocks to the k branch processing circuits connected with the basic data blocks, and broadcasting the broadcast data blocks and the identification data blocks associated with the broadcast data blocks to the k branch processing circuits connected with the basic data blocks;

the k branch processing circuits are used for starting the second mapping circuit to obtain a connection identification data block according to the identification data block associated with the basic data block and the identification data block associated with the broadcast data block; processing the basic data block and the broadcast data block according to the connection identification data block, and distributing the processed basic data block and the processed broadcast data block to a basic processing circuit connected with the basic data block and the processed broadcast data block;

2. The integrated circuit chip apparatus of claim 1, wherein the identification data block is a matrix data block consisting of 0 and 1 when the identification data block is represented by a direct index, wherein 0 represents that an absolute value of data in the identification data block is less than or equal to a first threshold, and 1 represents that the absolute value of data in the identification data block is greater than the first threshold.

3. The integrated circuit chip apparatus of claim 1 or 2,

the main processing circuit is specifically configured to broadcast the broadcast data block or the processed broadcast data block to the k branch processing circuits at a time; alternatively, the first and second electrodes may be,

the main processing circuit is specifically configured to divide the broadcast data block or the processed broadcast data block into a plurality of partial broadcast data blocks, and broadcast the plurality of partial broadcast data blocks to the K branch processing circuits by multiple times.

4. The integrated circuit chip apparatus of claim 1 or 2,

the basic processing circuit is specifically configured to perform inner product processing on the basic data block and the broadcast data block to obtain an inner product result, accumulate the inner product processing result to obtain an operation result, and send the operation result to the main processing circuit;

and the main processing circuit is used for accumulating the operation results to obtain accumulation results when the operation results are the results of inner product processing, and arranging the accumulation results to obtain the data blocks to be calculated and the instruction results corresponding to the operation instructions.

5. The integrated circuit chip apparatus of claim 1 or 2,

the main processing circuit is further specifically configured to split the processed broadcast data block and the identification data block associated with the broadcast data block to obtain a plurality of partial broadcast data blocks and identification data blocks associated with the plurality of partial broadcast data blocks; broadcasting the plurality of partial broadcast data blocks and the identification data blocks associated with each of the plurality of partial broadcast data blocks to the k branch processing circuits; the plurality of partial broadcast data blocks are combined to form the processed broadcast data block;

the k branch processing circuits are specifically configured to start the second mapping circuit to obtain a connection identification data block according to the identification data block associated with the partial broadcast data block and the identification data block associated with the basic data block; processing the partial broadcast data block and the basic data block according to the connection identification data block to obtain a processed broadcast data block and a processed basic data block; distributing the processed broadcast data block and the processed basic data block to a basic processing circuit connected with the processed broadcast data block so as to execute inner product operation;

or, the k branch processing circuits are specifically configured to start the second mapping circuit to process the basic data block according to the identification data block associated with the partial broadcast data block to obtain a processed basic data block, and distribute the processed basic data and the partial broadcast data block to a basic processing circuit connected thereto to perform an inner product operation.

6. The integrated circuit chip apparatus of claim 1 or 2,

the basic processing circuit is specifically configured to perform an inner product processing on the partial broadcast data block and the basic data block once to obtain an inner product processing result, accumulate the inner product processing result to obtain a partial operation result, and send the partial operation result to the main processing circuit; alternatively, the first and second electrodes may be,

the basic processing circuit is specifically configured to multiplex n times the partial broadcast data block to perform inner product operation between the partial broadcast data block and n basic data blocks to obtain n partial processing results, accumulate the n partial processing results respectively to obtain n partial operation results, and send the n partial operation results to the main processing circuit, where n is an integer greater than or equal to 2.

7. The integrated circuit chip apparatus of claim 1 or 2,

if the operation instruction is a multiplication instruction, the main processing circuit determines that the multiplier data block is a broadcast data block and the multiplicand data block is a distribution data block;

8. A chip integrating the device according to any of claims 1-7.

9. A smart device, characterized in that it comprises a chip according to claim 8.

10. A method of operation of a neural network, the method being implemented within an integrated circuit chip device, the integrated circuit chip device comprising: the integrated circuit chip apparatus of any one of claims 1-7, the integrated circuit chip apparatus to perform operations of a neural network; the operation of the neural network comprises: one or any combination of convolution operation, matrix multiplication matrix operation, matrix multiplication vector operation, bias operation, full connection operation, GEMM operation, GEMV operation and activation operation.