CN110098895B - LDPC code decoding method based on variable node dynamic block updating - Google Patents

LDPC code decoding method based on variable node dynamic block updating Download PDF

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CN110098895B
CN110098895B CN201910289893.9A CN201910289893A CN110098895B CN 110098895 B CN110098895 B CN 110098895B CN 201910289893 A CN201910289893 A CN 201910289893A CN 110098895 B CN110098895 B CN 110098895B
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CN110098895A (en
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刘星成
郭婷
梁硕
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National Sun Yat Sen University
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    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G06F11/1056—Updating check bits on partial write, i.e. read/modify/write
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    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
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    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
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Abstract

The invention relates to an LDPC code decoding method aiming at MLC type NAND-Flash and based on variable node dynamic block update, which comprises the following steps: s1, in a NAND-Flash storage channel, dividing variable nodes in a non-overlapping region into Data blocks, and dividing variable nodes in an overlapping region into overlay sub-blocks: s2, continuously subdividing the Data block into a plurality of Data sub-blocks; s3, skipping a plurality of data sub-blocks, sequentially updating the variable nodes in the remaining data sub-blocks and overlay sub-blocks in sequence, respectively searching low-value variable nodes in the data sub-blocks and the overlay sub-blocks, and sequentially updating the low-value variable nodes; s4, judging whether the judgment condition is met, if so, sequentially updating the variable nodes of the data sub-blocks skipped in the step S3 and repeating the step S3, and if not, repeating the step S3; s5, judging whether the decoding is successful, if not, continuing to the step S4, and if so, ending. And the information generated by updating the reliable nodes is utilized to drive the updating of the unreliable nodes, so that the utilization rate of the iterative updating information is improved.

Description

LDPC code decoding method based on variable node dynamic block updating
Technical Field
The invention relates to the technical field of communication coding, in particular to an LDPC code decoding method aiming at MLC type NAND-Flash and based on variable node dynamic block updating.
Background
In 1962, Gallager proposed LDPC (Low Density parity check) codes for the first time in a paper, and the definition, construction method and decoding method of the LDPC codes are given in the paper. The two coding schemes mentioned in the paper are: hard decision decoding based on Bit Flipping (BF) and soft decision decoding based on posterior Probability (Posteriori Probability) lay a theoretical foundation for subsequent research, but because of the limitations of computer processing capability and storage capability at the time, LDPC codes have not attracted researchers' attention. Until 1996, MacKay and Neal study the LDPC code again on the basis of Gallager study, two people construct a plurality of code words with different code lengths and code rates in a randomized structure mode, and experimental simulation verifies that when the code length is enough, a Belief Propagation (BP) decoding mode is adopted for decoding, and the error correction performance of the LDPC code can be close to the Shannon limit. Meanwhile, with the rapid development of computer technology, the attention of many scholars is attracted, so that the LDPC code becomes the research focus in the technical field of channel coding and decoding. In recent years, LDPC codes have more excellent error correction performance than Turbo codes, and have a lower error level layer, and thus play an essential role in the fields of communications, storage, computers, and the like. For example, LDPC codes play an important role in optical fiber communications, network data transmission, deep space communications, and high speed wireless local area network communications. In 2017, LDPC codes were accepted by 3GPP as medium-and-long code coding schemes for 5G system eMBB service data information.
LDPC decoding algorithms can be mainly classified into hard-decision decoding algorithms and soft-decision decoding algorithms. Among them, the most basic hard decision decoding algorithm is BF decoding algorithm, which has the advantages of low decoding complexity and simple hardware implementation, but has the disadvantage of poor error correction performance, and cannot achieve the expected error correction performance in some practical applications. The most basic soft decision decoding algorithm is a BP decoding algorithm based on a probability domain, the BP decoding algorithm decodes according to the received posterior probability information, and due to the fact that channel soft information is utilized, the performance of the BP decoding algorithm is improved by about one time compared with the performance of a hard decision decoding algorithm, but the decoding complexity is increased. The parallel scheduling decoding algorithm is a soft decision decoding algorithm, and mainly takes a BP algorithm in a log domain, namely an LLR BP (log likelihood ratio) algorithm as a main algorithm. In the LLR BP decoding algorithm process, two processes are mainly included: firstly, messages from all check nodes to variable nodes are simultaneously updated in parallel; and secondly, messages from all variable nodes to check nodes are updated simultaneously in parallel, and the messages updated in the current iteration in the algorithm can be used only by the next iteration, so that the message utilization rate is low, and the convergence speed is low. Later, Sharon et al proposed an sbp (serial Belief propagation) decoding algorithm, which updates node information according to the sequence of rows or columns of the check matrix, and the serial scheduling decoding algorithm can use the information generated after updating in the current iteration, thereby improving the utilization rate of the information and improving the error correction performance to a certain extent. On the basis of a serial scheduling-based decoding algorithm, in order to further increase the convergence rate and improve the decoding performance, in recent years, researchers have proposed various dynamic scheduling algorithms successively, but at the cost of extremely high decoding complexity. And NAND-Flash is a device which requires low time delay and high reliability, so that the decoding algorithm of the dynamic scheduling LDPC code is not suitable for the NAND-Flash.
The NAND-Flash is a nonvolatile solid-state memory, and has the advantages of high access speed, low power consumption, light volume and the like compared with a magnetic disk memory, so that the NAND-Flash has wide application in the field of information storage, such as application to electronic devices such as mobile phones, wearable devices and computers. NAND-Flash can be classified into SLC (Single-Level Cell), MLC (Multi-Level Cell), TLC (Trinary-Level Cell), and QLC (Quad-Level Cell) types according to the number of bits that can store data bits in a memory Cell. SLC means that a memory cell can only store 1 bit of data, and data '0' and '1' are characterized by two voltage states; MLC means that a memory cell stores 2 bits of data, and four voltage states are used to represent 2 bits of information ('11', '10', '01', '00'); TLC means that one memory cell stores 3 bits of data, and 8 voltage states are used to represent 3 bits of information; QLC means that a memory cell stores 4 bits of data, and 16 voltage states are used to represent 4 bits of information. With the development of the technology, the chip of the NAND-Flash is smaller and smaller, the storage capacity is larger and larger, and the storage density is larger and larger, so that the overlapping condition between the voltage distribution states of the storage units is more serious, the interference between the storage units is greatly increased, the possibility of data errors is increased, and the reliability of the data errors is also continuously reduced. Meanwhile, the NAND-Flash mainly has interference noise, programming noise, random telegraph noise and data retention noise among units, the interference of the noise can also cause data to be easy to make mistakes, the error correction performance of a hard decision decoding algorithm of the LDPC code and a traditional LLR BP parallel decoding algorithm can not meet the requirement of the NAND-Flash on the reliability of the data under high storage density, and the requirements of a high-density Flash memory on low time delay and high throughput are completely not met because the complexity of a dynamic scheduling decoding algorithm is very high and the hardware realization difficulty is high. Therefore, it is necessary to apply an error correcting code having excellent performance to the NAND-Flash memory system.
With the improvement of unit storage density, the traditional error correcting codes such as Hamming code and BCH code are difficult to meet the error correcting performance requirement of NAND-Flash, and because the LDPC code can approach to the Shannon limit to the maximum extent, and can obtain good error correcting performance under the condition of high code rate without bringing too large time delay, the LDPC code is the mainstream error correcting code scheme aiming at the problem of data storage reliability of the Flash memory technology at present and is also a main research hotspot in the field of high-density storage coding and decoding at present.
The LDPC code is applied to NAND-Flash, and the specific application scene of NANDFlash is also met on the premise of ensuring good decoding performance. For example, the requirements of low latency, high throughput, and low cost of high density flash memory need to be met. Therefore, a reasonable trade-off between coding performance and coding efficiency needs to be made.
Disclosure of Invention
The invention aims to overcome at least one defect (deficiency) of the prior art, and provides an LDPC code decoding method aiming at MLC type NAND-Flash and based on variable node dynamic block update, which improves the decoding performance on the basis of being suitable for a NAND-Flash storage channel, enables an algorithm to concentrate computing resources at the initial decoding stage, preferentially updates reliable nodes, utilizes information generated by reliable node update to drive updating unreliable nodes, improves the utilization rate of the information updated by each iteration, and accelerates the convergence rate of the algorithm.
The technical scheme adopted by the invention is as follows:
an LDPC code decoding method aiming at MLC type NAND-Flash and based on variable node dynamic block update comprises the following steps:
s1, in a NAND-Flash storage channel, partitioning all variable nodes according to the probability that the voltage of the variable nodes falls into each area: dividing variable nodes in a non-overlapping region into Data blocks, and dividing variable nodes in an overlapping region into overlap sub-blocks;
s2, continuously subdividing each block into a plurality of sub-blocks according to the absolute value of the initial LLR value of the variable node in each block: continuously subdividing the Data block into a plurality of Data sub-blocks;
s3, skipping a plurality of data sub-blocks, sequentially updating the variable nodes in the remaining data sub-blocks and overlay sub-blocks in sequence, respectively searching low-value variable nodes in each data sub-block and overlay sub-block according to the judgment criterion of the low-value variable nodes, putting the low-value variable nodes in the set L, and sequentially updating the low-value variable nodes in the set L;
s4, judging whether the judgment condition is met, if so, updating the variable nodes of the data sub-blocks skipped in the step S3 in sequence, repeating the step S3 and executing the step S5, and if not, repeating the step S3;
s5, judging whether the decoding is successful, if not, continuing to the step S4, and if so, ending.
The decoding method firstly blocks all variable nodes according to a blocking principle, the number of the variable nodes in each sub-block is different under different programming and erasing periods (Program/Erase cycles and PE cycles), then different processing is carried out on each sub-block successively, low-value variable nodes in the sub-blocks are searched out simultaneously, and the low-value variable nodes are updated in time after all the sub-blocks are processed, so that the utilization rate of updated information each time is improved, the updated information of reliable nodes is utilized to update the low-value variable nodes, the negative influence of unreliable information is inhibited in time, and the decoding performance is improved.
After all variable nodes are partitioned according to a partitioning principle: firstly, the variable nodes in the Data block are subjected to related updating treatment: and skipping updating of the nodes in the data sub-blocks at the initial iteration, only searching out the low-value variable nodes and storing the low-value variable nodes into the set L, sequentially updating the variable nodes in the remaining data sub-blocks, and simultaneously searching out the low-value variable nodes in the sub-blocks and storing the low-value variable nodes into the set L. Therefore, reliable nodes are processed preferentially, information generated in the updating process of reliable variable nodes in the Data block can be transmitted into the overlap sub-block, and a positive promoting effect can be generated on the updating of the nodes in the overlap sub-block. And then, carrying out related serial updating processing on variable nodes in the overlap sub-blocks, sequentially updating the nodes in the overlap sub-blocks, and simultaneously searching out low-value variable nodes in each sub-block and storing the low-value variable nodes in the set L.
Further, the judgment criterion of the low-value variable node is specifically:
for the updated variable node, if the absolute value of the LLR value after the update of the variable node is less than or equal to the average value of the absolute values of the initial LLR values of the low-information variable nodes in the overlap sub-block, judging that the variable node is a low-value variable node;
and for the variable node which is not updated, if the absolute value of the initial LLR value of the variable node is less than or equal to the average value of the absolute values of the initial LLR values of the low-information variable nodes in the overlap sub-block, judging that the variable node is a low-value variable node.
Further, the determination condition specifically includes: iter > - γ · max _ iter, - γ -0.625, iter is the number of iterations, and max _ iter is the maximum number of iterations.
Further, updating the variable nodes in the sub-blocks specifically includes the following steps:
note that the variable node in the sub-block is vi；
For all check nodes cj∈N(vi) Update C2V message
Figure GDA0002614957800000051
According to the updated C2V message
Figure GDA0002614957800000052
Solving for variable node viUpdated LLR value and for all check nodes cj∈N(vi) Update V2C message
Figure GDA0002614957800000053
Wherein, N (v)i) Representation and variable node viA set of connected check nodes that are,
Figure GDA0002614957800000054
representing check nodescjTo variable node viThe message of (a) is received,
Figure GDA0002614957800000055
representing variable node viTo check node cjV2C message.
Further, updating the low-value variable nodes in the set L specifically includes the following steps:
note that the low-value variable node in the set L is vpi；
For all check nodes cj∈N(vpi) Update C2V message
Figure GDA0002614957800000056
According to the updated C2V message
Figure GDA0002614957800000057
Solving for variable node vpiUpdated LLR value and for all check nodes cj∈N(vpi) Update V2C message
Figure GDA0002614957800000058
Wherein, N (v)pi) Representation and variable node vpiA set of connected check nodes that are,
Figure GDA0002614957800000059
represents check node cjTo variable node vpiThe message of (a) is received,
Figure GDA00026149578000000510
representing variable node vpiTo check node cjV2C message.
Further, the pair of all check nodes cj∈N(vi) Update C2V message
Figure GDA00026149578000000511
The specific calculation formula of (A) is as follows:
Figure GDA00026149578000000512
wherein, N (c)j)\viIndicating node v except for variableiAll and check nodes c outsidejSet of connected variable nodes, N (c)j) Representing all and check nodes cjThe collection of connected variable nodes is connected to,
Figure GDA00026149578000000513
representing variable node vi'To check node cjV2C message of (a);
the message is according to the updated C2V
Figure GDA0002614957800000061
Solving for variable node viThe specific calculation formula of the updated LLR value is as follows:
Figure GDA0002614957800000062
wherein, L' (v)i) Representing variable node viUpdated LLR value, L (v)i) Representing variable node viThe initial LLR values of the received channel,
Figure GDA0002614957800000063
represents check node cjTo variable node viC2V message;
the pair of all check nodes cj∈N(vi) Update V2C message
Figure GDA0002614957800000064
The specific calculation formula of (A) is as follows:
Figure GDA0002614957800000065
wherein, N (v)i)\cjIndicating the exception of check node cjAll-out and variable node viConnected check jointSet of points, N (v)i) Representing all and variable nodes viA set of connected check nodes that are,
Figure GDA0002614957800000066
indicating the exception of check node cjOuter check node passing to variable node viThe information of (a);
further, for all check nodes cj∈N(vpi) Update C2V message
Figure GDA0002614957800000067
The specific calculation formula of (A) is as follows:
Figure GDA0002614957800000068
wherein, N (c)j)\vpiIndicating node v except for variablepiAll and check nodes c outsidejSet of connected variable nodes, N (c)j) Representing all and check nodes cjThe collection of connected variable nodes is connected to,
Figure GDA0002614957800000069
representing variable node vpi'To check node cjV2C message of (a);
the message is according to the updated C2V
Figure GDA00026149578000000610
Solving for variable node vpiThe specific calculation formula of the updated LLR value is as follows:
Figure GDA00026149578000000611
wherein, L' (v)pi) Representing variable node vpiUpdated LLR value, L (v)pi) Representing variable node vpiThe initial LLR values of the received channel,
Figure GDA00026149578000000612
represents check node cjTo variable node vpiC2V message;
the pair of all check nodes cj∈N(vpi) Update V2C message
Figure GDA00026149578000000613
The specific calculation formula of (A) is as follows:
Figure GDA0002614957800000071
wherein, N (v)pi)\cjIndicating the exception of check node cjAll-out and variable node vpiSet of connected check nodes, N (v)pi) Representing all and variable nodes vpiA set of connected check nodes that are,
Figure GDA0002614957800000072
check node cj'To variable node vpiThe information of (1).
Compared with the prior art, the invention has the beneficial effects that:
the method makes full use of the characteristics of MLC type NAND-Flash channels, dynamically blocks all variable nodes according to the probability of the variable nodes falling into each region and the absolute value of the initial LLR value, divides most of the variable nodes falling into the non-overlapping region into Data blocks, divides the Data blocks into a plurality of Data sub-blocks according to the absolute value of the initial LLR value of the variable nodes in the non-overlapping region, and simultaneously divides the remaining few variable nodes in the overlapping region into overlay sub-blocks. The variable nodes in the Data blocks have very low error probability, so the variable nodes can be regarded as variable nodes with high reliability, wherein the variable nodes in the previous Data sub-blocks are most reliable, the nodes in the Data sub-blocks are skipped over during the initial decoding stage, the nodes in the rest Data blocks are preferentially updated, the computing resources are saved, the updating of unreliable nodes is restrained, the utilization rate of reliable information is improved, and the updating of the subsequent nodes is promoted. After the block updating is finished, the low-value variable nodes in the set L are timely processed and updated, and the transfer of unreliable information in the updating process is restrained.
After iteration is carried out for a plurality of times, judging that iter > < gamma.max _ iter, if the judgment condition is met, starting updating operation on all variable nodes in the skipped Data blocks, and repeating the updating steps of the variable nodes in the rest Data sub-blocks and the overlap sub-blocks, so that the variable nodes with a small amount of low-reliability information in the skipped Data sub-blocks at the initial stage of iteration are fully considered, and the variable nodes can be updated to all nodes more comprehensively. After the processing, decoding judgment is carried out on all variable nodes after the updating is finished, and if the decoding is successful, the decoding is finished.
Drawings
FIG. 1 is a flowchart illustrating an embodiment of a decoding method.
FIG. 2 is a flow chart of dynamic blocking update of all variable nodes based on blocking criteria according to an embodiment of the present invention.
FIG. 3 is a graph of probability density of voltage distribution of each memory cell of MLC-type NAND-Flash according to the embodiment of the present invention.
FIG. 4 is a statistical result of the number of variable nodes in each sub-block according to an embodiment of the present invention.
Fig. 5 shows the absolute values of the initial LLRs of the variable nodes in each sub-block in the embodiment of the present invention.
Fig. 6(a) to (d) are schematic diagrams illustrating sequential update of variable nodes in a Data block according to an embodiment of the present invention.
Fig. 7(a) to (d) are schematic diagrams illustrating sequential updating of variable nodes in overlap sub-blocks according to an embodiment of the present invention.
FIG. 8 is a comparison of error correction performance of the LDPC code of embodiment 0.9- (3780,3402) of the present invention.
FIG. 9 is a comparison of error correction performance of the LDPC code of embodiment 0.92- (8000,7360) of the present invention.
FIG. 10 is a comparison of the convergence performance of the LDPC code of example 0.9- (3780,3402) of the present invention.
FIG. 11 is a comparison of the convergence performance of the LDPC code of example 0.92- (8000,7360) of the present invention.
Detailed Description
The drawings are only for purposes of illustration and are not to be construed as limiting the invention. For a better understanding of the following embodiments, certain features of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
Examples
As shown in fig. 1 and fig. 2, the present embodiment provides a variable node dynamic partitioning-based LDPC code decoding method for MLC-type NAND-Flash, including the following steps:
s1, in a NAND-Flash storage channel, partitioning all variable nodes according to the probability that the voltage of the variable nodes falls into each area: dividing variable nodes in a non-overlapping region into Data blocks, and dividing variable nodes in an overlapping region into overlap sub-blocks;
s2, continuously subdividing each block into a plurality of sub-blocks according to the absolute value of the initial LLR value of the variable node in each block: the Data block is continuously subdivided into a Data1 sub-block and a Data2 sub-block;
s3, skipping over the data1 sub-blocks, sequentially updating the variable nodes in the data2 sub-block and the overlap sub-block, respectively searching out the low-value variable nodes in the data1 sub-block, the data2 sub-block and the overlap sub-block according to the judgment criterion of the low-value variable nodes, putting the low-value variable nodes in the set L, and sequentially updating the low-value variable nodes in the set L;
s4, judging whether the judgment condition is met, if so, updating the variable nodes of the data sub-blocks skipped in the step S3 in sequence, repeating the step S3 and executing the step S5, and if not, repeating the step S3;
s5, judging whether the decoding is successful, if not, continuing to the step S4, and if so, ending.
Fig. 3 shows a channel model of the MLC NAND-Flash when the erase/write period PE is 15000 and the retention time coefficient T is 1, where the abscissa represents the threshold voltage and the ordinate represents the probability density, and each curve represents the probability density function in each storage state. In NAND-Flash of the MLC type, each timeEach memory cell stores 2 bits of data, and thus can represent four data storage states, which are, in order from low to high: 11 (erased state), 10 (programmed state), 00 (programmed state), and 01 (programmed state). To obtain the 2 bits of information stored in each cell, the present embodiment first sets a non-uniform set of quantized read voltages-R1,R2,R3,R4,R5And R6To obtain a higher accuracy LLR value for each quantization region. By combining the non-uniform read voltages and equations (1) and (2), the initial LLR value of the variable node corresponding to the high Bit (MSB) and low Bit (LSB) in each quantization region can be obtained, wherein,
Figure GDA0002614957800000091
Figure GDA0002614957800000092
and
Figure GDA0002614957800000093
the voltage distribution probability density functions representing states 11, 10, 00, and 01, respectively, are expressed by equations (3), (4), (5), and (6), respectively:
Figure GDA0002614957800000094
Figure GDA0002614957800000095
Figure GDA0002614957800000096
Figure GDA0002614957800000097
Figure GDA0002614957800000098
Figure GDA0002614957800000101
wherein L ismsbInitial LLR value, L, of variable node corresponding to high order bitlsbThe initial LLR value of the variable node corresponding to the low-order bit.
In addition, Vmin,V1,V2And VmaxThe threshold voltages respectively representing the four cell states in MLC-type NAND-Flash are shown in fig. 3.Δ VppWhich represents a stepped programming voltage when performing a programming operation on a memory cell. The data stored in the MLC NAND-Flash may be disturbed by various noises, so that the probability density curves of the voltage states also change under the influence of the noises. Wherein the content of the first and second substances,
Figure GDA0002614957800000102
and
Figure GDA0002614957800000103
respectively representing the standard deviation of probability density distribution obtained after the states of the four memory cells of 11, 10, 00 and 01 are interfered by noise,
Figure GDA0002614957800000104
and
Figure GDA0002614957800000105
the mean of the probability density distributions of the data retention noise representing the four memory cell states, respectively. In addition, erf (x) is a gaussian error function, and is expressed as follows:
Figure GDA0002614957800000106
as shown in fig. 3, in the present embodiment, all the memory cells are quantized into 7 regions by adding an additional read voltage, D1 to D4 correspond to the divided Data block, and O1 to O3 correspond to the divided overlap sub-block.
Each block is further subdivided into a plurality of sub-blocks according to the absolute value of the initial LLR value of the variable node in each block, and the statistical result of the number of the variable nodes in each sub-block is shown in fig. 4.
In this embodiment, the criterion for determining the low-value variable node is specifically:
for the updated variable node, if the initial LLR value absolute value of the variable node or the updated LLR value absolute value is smaller than a set value, judging the variable node as a low-value variable node;
and for the variable node which is not updated, if the absolute value of the initial LLR value of the variable node is smaller than a set value, judging that the variable node is a low-value variable node.
As shown in fig. 5, the relative magnitude of the initial LLR values of the variable nodes in each sub-block can be known, while the absolute values of the initial LLR values of the partial variable nodes in the overlap sub-block are very small and close to 0, which are called low-information variable nodes, and these variable nodes can be considered to be very unreliable, so that further processing is required on these variable nodes to prevent the transfer of unreliable information in the iterative process. Therefore, when the absolute value of the initial LLR value of the variable node or the absolute value of the updated LLR value is less than or equal to the average value of the absolute values of the initial LLR values of the low-information variable nodes in the overlap sub-block, the variable node is defined as a low-value variable node and stored in the set L. I.e. the low value variable node Vp,thr＝avg(abs(init-llr[i]) Init-llr [ i ]]Indicating the initial LLR values of the low information variable nodes.
In step S3, let v be the variable node in the data1 sub-block1iV is the variable node in the data2 sub-block2iV 'is the variable node in the overlap sub-block'i。
When the iteration starts, variable nodes in the data1 sub-block are skipped over and are not updated, and the variable nodes in the data2 sub-block and the overlap sub-block are sequentially updated respectively.
Updating the variable nodes in the data2 sub-block, which specifically comprises the following steps:
with variable node v in data2 sub-block21For example, asVariable node v as shown in FIGS. 6(a) and 6(b)21And variable node v21All check nodes connected are c1、c2、c5Where circles represent variable nodes and boxes represent check nodes.
First, the check node c is updated by equation (8)1、c2、c5To variable node v21C2V message
Figure GDA0002614957800000111
Figure GDA0002614957800000112
When j in formula (8) is 1, 2, 5, viCorresponds to v21：
Figure GDA0002614957800000113
Wherein, N (c)j)\viIndicating node v except for variableiAll and check nodes c outsidejSet of connected variable nodes, N (c)j) Representing all and check nodes cjThe collection of connected variable nodes is connected to,
Figure GDA0002614957800000114
representing variable node vi'To check node cjV2C message.
Then, the variable node v is obtained by equation (9)21Updated LLR value L' (v)21) When j in formula (9) is 1, 2, 5, viCorresponds to v21：
Figure GDA0002614957800000115
Wherein, L' (v)i) Representing variable node viUpdated LLR value, L (v)i) Representing variable node viThe initial LLR values of the received channel,
Figure GDA0002614957800000121
represents check node cjTo variable node viC2V message.
Finally, the variable node v is updated using equation (10)21To check node c1、c2、c5V2C message
Figure GDA0002614957800000122
When j in formula (10) is 1, 2, 5, viCorresponds to v21：
Figure GDA0002614957800000123
Wherein, N (v)i)\cjIndicating the exception of check node cjAll-out and variable node viSet of connected check nodes, N (v)i) Representing all and variable nodes viA set of connected check nodes that are,
Figure GDA0002614957800000124
indicating the exception of check node cjOuter check node passing to variable node viThe information of (1).
As shown in FIGS. 6(c) and 6(d), at variable node v21After updating, repeating the variable node updating step to continuously update the next variable node until all variable nodes in the data2 sub-block are updated.
After all the variable nodes in the data2 sub-block are updated, continuously updating the variable nodes in the overlap sub-block, and specifically comprising the following steps:
by variable node v 'in overlap sub-block'1For example, the variable node v 'is shown in FIG. 7(a) and FIG. 7 (b)'1And with variable node v'1Connected check node c2、c4、c5Where circles represent variable nodes and boxes represent check nodes.
Similar to the variable node update in the data2 sub-block, the check node c is first updated by equation (8)2、c4、c5To variable node v'1C2V message
Figure GDA0002614957800000125
And
Figure GDA0002614957800000126
when j in formula (8) is 2, 4, 5, viIs v'1(ii) a Then, the variable node v 'is obtained from the formula (9)'1Updated LLR value L '(v'1) When j in formula (9) is 2, 4, 5, viIs v'1(ii) a Finally, updating variable node v 'by formula (10)'1To check node c2、c4、c5V2C message
Figure GDA0002614957800000127
Figure GDA0002614957800000128
When j in formula (10) is 2, 4, 5, viIs v'1。
At variable node v'1After updating, repeating the updating steps of the variable nodes to continuously update the next variable node until all the variable nodes in the overlap sub-block are updated.
In the specific implementation process of this embodiment, after variable node update is performed on all subblocks requiring variable node update, low-value variable nodes in all subblocks are searched and placed in the set L; or after each subblock needing variable node updating is subjected to variable node updating, searching low-value variable nodes in the subblock and putting the low-value variable nodes into the set L, and then continuously performing variable node updating on the next subblock.
Updating the low-value variable nodes in the set L, wherein the specific updating method is the same as the node updating method in fig. 5 and 6, and the method specifically includes the following steps:
first, all check nodes c are updated using equation (11)j∈N(vpi) C2V message passed to Low value variable node
Figure GDA0002614957800000131
Figure GDA0002614957800000132
Wherein, N (c)j)\vpiIndicating node v except for variablepiAll and check nodes c outsidejSet of connected variable nodes, N (c)j) Representing all and check nodes cjThe collection of connected variable nodes is connected to,
Figure GDA0002614957800000133
representing variable node vpi'To check node cjV2C message.
Then, the LLR value L' (v) after updating the low-value variable node is obtained by the expression (9)pi)：
Figure GDA0002614957800000134
Wherein, L' (v)pi) Representing variable node vpiUpdated LLR value, L (v)pi) Representing variable node vpiThe initial LLR values of the received channel,
Figure GDA0002614957800000135
represents check node cjTo variable node vpiC2V message.
Finally, the updated low-value variable node of the formula (10) is transmitted to all check nodes cj∈N(vpi) V2C message
Figure GDA0002614957800000136
Figure GDA0002614957800000137
Wherein, N (v)pi)\cjIndicating the exception of check node cjAll-out and variable node vpiConnected checkSet of nodes, N (v)pi) Representing all and variable nodes vpiA set of connected check nodes that are,
Figure GDA0002614957800000138
check node cj'To variable node vpiThe information of (1).
In step S4, the determination condition specifically includes: iter > - γ · max _ iter, - γ -0.625, iter is the number of iterations, and max _ iter is the maximum number of iterations.
By a large number of experimental simulations, γ is set to 0.625, which enables a high error correction performance and a maximum throughput to be achieved, thereby reducing complexity.
In step S5, after the update processing of all the subblocks and the low-value variable nodes is completed, decoding decision is performed on all the variable nodes, and if the decoding end condition is satisfied, decoding is completed, and if the decoding end condition is not satisfied, step S4 is repeated until decoding is completed.
The decoding method provided by this embodiment firstly blocks all variable nodes according to a blocking principle, the variable nodes in each sub-block are different under different PEs, then different processing is performed on each sub-block in sequence and low-value variable nodes in each sub-block are searched, and the low-value variable nodes are updated in time after all sub-blocks are processed, so that the utilization rate of updated information each time is improved, the negative influence of unreliable information is suppressed, and the decoding performance is improved.
In order to verify the excellent performance of the decoding method proposed by the present patent, the present embodiment needs to perform computer simulation. The specific method is to construct two regular LDPC code words with high code rate by using the PEG method, wherein the code lengths are (3780,3402) and (8000,7360), respectively. The information bits of each codeword are grouped, and adjacent 2 information bits are stored in one cell of MLC NAND-Flash without repetition. Since the data stored in the cell is disturbed by various noises, the voltage values represented by the states are not an exact value but exhibit a distribution, as shown in fig. 3. The writing, erasing and reading process of the LDPC codeword in the MLC NAND-Flash can be considered as passing a noisy channel. In this embodiment, Visual Studio 2015 is used as a simulation platform, and first, the LLR BP parallel decoding method, VSBP serial decoding method, QABP decoding method proposed by Aslam, etc., and the blockabp decoding method proposed by the present invention are compared in decoding performance. The programming language uses C + +, setting the retention time coefficient T to 1. The error correction performance and convergence performance of two different codewords are simulated respectively, as shown in fig. 8, 9, 10, and 11, when the number of error frames reaches 100 frames, the iterative simulation is stopped, the corresponding frame error rate FER is counted, and a corresponding decoding performance graph is drawn.
FIG. 8 is a comparison graph of the error correction performance obtained by using different decoding algorithms on a NAND-Flash channel of MLC type for a 0.9- (3780,3402) codeword, the maximum number of iterations ImaxWith 5, the abscissa is the erase-write period PE and the ordinate is the frame error rate FER. It can be seen from the figure that, under any PE, the blockabp decoding algorithm proposed by the present invention has the best error correction performance. The LLRBP decoding algorithm is updated in a parallel scheduling mode, and a new message obtained by the iteration can only be used for the next iteration, so that the error correction performance of the LLRBP decoding algorithm is far inferior to that of other three serial decoding algorithms. In addition, compared with the VSBP decoding algorithm, the decoding performance of the blockabp decoding algorithm is greatly improved, wherein when PE is 18000, the FER of the blockabp decoding algorithm is reduced by about 45% compared with that of the VSBP decoding algorithm. And at a FER of 10-3In this case, the BlockBP algorithm has nearly 1500 more PEs than the VSBP algorithm, which indicates that: the BlockBP algorithm can still achieve the same error correction performance as the VSBP algorithm under worse channel conditions. Although the effect of improving the error correction performance is not significant when the PE is 16000, 15000, compared to the QABP algorithm proposed by Aslam et al, the effect is not significant at large erasure times (PE)>16000), the FER is reduced significantly, and the average reduction is 34%, which shows that compared with the QABP algorithm, the error correction performance of the decoding algorithm is greatly improved by performing block processing and updating on the variable nodes.
FIG. 9 shows the use of different decoding calculations for 0.92- (8000,7360) codewords on a NAND-Flash channel of MLC typeError correction performance comparison graph obtained by the method, maximum iteration number ImaxWith 5, the abscissa is the erase-write period PE and the ordinate is the frame error rate FER. It can be seen that when PE is less than 20000, the decoding performance of the blockabp decoding algorithm is better than that of the other three decoding algorithms. At PE 15000, the FER of the blockabp algorithm is reduced by about 60% compared to the FER of the QABP algorithm. At PE 16000, the FER of the BlockBP algorithm is an order of magnitude lower than that of the VSBP algorithm. As can be seen from fig. 8 and 9, as the codeword grows, the error correction performance of the blockabp algorithm becomes more and more excellent.
Fig. 10 and 11 are graphs comparing convergence performance obtained by using different decoding algorithms on a channel of MLC type NAND-Flash for a 0.9 code rate- (3780,3402) codeword and a 0.92 code rate- (8000,7360) codeword, respectively, where the ordinate is a frame error rate FER, and the abscissa is a maximum iteration number MaxIter. Setting the erasure period PE to 16000 and the retention time coefficient T to 1, it can be seen from the figure that after 20 iterations, the FER curves of the algorithms are gradually smoothed, and the decoding algorithm enters the convergence state. Compared with other algorithms in the graph, the Block BP algorithm has the fastest decoding convergence speed under two code lengths, namely, the excellent error correction performance can be obtained only by a small number of iteration times. Under the same iteration times, the BlockBP algorithm has the best error correction performance, under the BlockBP algorithm, the FER when MaxIter is 5 is similar to the FER when MaxIter is 15 under the VSBP algorithm, which shows that the algorithm provided by the invention greatly improves the decoding convergence rate by carrying out block processing and updating on all variable nodes before the iteration starts. Meanwhile, as can be seen from fig. 10 and 11, along with the increase of the code word, the convergence performance superiority of the blockabp algorithm is more and more obvious.
It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the technical solutions of the present invention, and are not intended to limit the specific embodiments of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention claims should be included in the protection scope of the present invention claims.

Claims (5)

1. An LDPC code decoding method aiming at MLC type NAND-Flash and based on variable node dynamic block update is characterized by comprising the following steps:
s1, in a NAND-Flash storage channel, partitioning all variable nodes according to the probability that the voltage of the variable nodes falls into each area: dividing variable nodes in a non-overlapping region into Data blocks, and dividing variable nodes in an overlapping region into overlap sub-blocks;
s2, continuously subdividing each block into a plurality of sub-blocks according to the absolute value of the initial LLR value of the variable node in each block: continuously subdividing the Data block into a plurality of Data sub-blocks;
s3, skipping a plurality of data sub-blocks, sequentially updating the variable nodes in the remaining data sub-blocks and overlay sub-blocks in sequence, respectively searching low-value variable nodes in each data sub-block and overlay sub-block according to the judgment criterion of the low-value variable nodes, putting the low-value variable nodes in the set L, and sequentially updating the low-value variable nodes in the set L;
s4, judging whether the judgment condition is met, if so, updating the variable nodes of the data sub-blocks skipped in the step S3 in sequence, repeating the step S3 and executing the step S5, and if not, repeating the step S3;
s5, judging whether the decoding is successful, if not, continuing to the step S4, and if so, ending;
the judgment criterion of the low-value variable node is specifically as follows:
for the updated variable node, if the absolute value of the LLR value after the update of the variable node is less than or equal to the average value of the absolute values of the initial LLR values of the low-information variable nodes in the overlap sub-block, judging that the variable node is a low-value variable node;
for the variable nodes which are not updated, if the absolute value of the initial LLR value of the variable node is less than or equal to the average value of the absolute values of the initial LLR values of the low-information variable nodes in the overlap sub-block, judging that the variable node is a low-value variable node;
the determination condition specifically includes: iter > - γ · max _ iter, - γ -0.625, iter is the number of iterations, and max _ iter is the maximum number of iterations.
2. The LDPC code decoding method for MLC-type NAND-Flash based on variable node dynamic block update according to claim 1, wherein the method for updating the variable nodes in the sub-blocks comprises the following steps:
note that the variable node in the sub-block is vi；
For all check nodes cj∈N(vi) Update C2V message
Figure FDA0002614957790000011
According to the updated C2V message
Figure FDA0002614957790000021
Solving for variable node viUpdated LLR value and for all check nodes cj∈N(vi) Update V2C message
Figure FDA0002614957790000022
Wherein, N (v)i) Representation and variable node viA set of connected check nodes that are,
Figure FDA0002614957790000023
represents check node cjTo variable node viThe message of (a) is received,
Figure FDA0002614957790000024
representing variable node viTo check node cjV2C message.
3. The LDPC code decoding method for MLC-type NAND-Flash based on variable node dynamic block update according to claim 1, wherein updating low-value variable nodes in the set L specifically comprises the following steps:
note that the low-value variable node in the set L is vpi；
For all check nodes cj∈N(vpi) Update C2V message
Figure FDA0002614957790000025
According to the updated C2V message
Figure FDA0002614957790000026
Solving for variable node vpiUpdated LLR value and for all check nodes cj∈N(vpi) Update V2C message
Figure FDA0002614957790000027
Wherein, N (v)pi) Representation and variable node vpiA set of connected check nodes that are,
Figure FDA0002614957790000028
represents check node cjTo variable node vpiThe message of (a) is received,
Figure FDA0002614957790000029
representing variable node vpiTo check node cjV2C message.
4. LDPC-code decoding method based on variable node dynamic block update for MLC-type NAND-Flash according to claim 2 wherein the said pair of all check nodes cj∈N(vi) Update C2V message
Figure FDA00026149577900000210
The specific calculation formula of (A) is as follows:
Figure FDA00026149577900000211
wherein, N (c)j)\viIndicating node v except for variableiAll and check nodes c outsidejSet of connected variable nodes, N (c)j) Representing all and check nodes cjThe collection of connected variable nodes is connected to,
Figure FDA00026149577900000212
representing variable node vi'To check node cjV2C message of (a);
the message is according to the updated C2V
Figure FDA00026149577900000213
Solving for variable node viThe specific calculation formula of the updated LLR value is as follows:
Figure FDA00026149577900000214
wherein, L' (v)i) Representing variable node viUpdated LLR value, L (v)i) Representing variable node viThe initial LLR values of the received channel,
Figure FDA0002614957790000031
represents check node cjTo variable node viC2V message;
the pair of all check nodes cj∈N(vi) Update V2C message
Figure FDA0002614957790000032
The specific calculation formula of (A) is as follows:
Figure FDA0002614957790000033
wherein, N (v)i)\cjIndicating the exception of check node cjAll-out and variable node viSet of connected check nodes, N (v)i) Representing all and variable nodes viA set of connected check nodes that are,
Figure FDA0002614957790000034
indicating the exception of check node cjOuter check node passing to variable node viThe information of (1).
5. LDPC-code decoding method based on variable node dynamic block update for MLC-type NAND-Flash according to claim 3 wherein c is the check node for allj∈N(vpi) Update C2V message
Figure FDA0002614957790000035
The specific calculation formula of (A) is as follows:
Figure FDA0002614957790000036
wherein, N (c)j)\vpiIndicating node v except for variablepiAll and check nodes c outsidejSet of connected variable nodes, N (c)j) Representing all and check nodes cjThe collection of connected variable nodes is connected to,
Figure FDA0002614957790000037
representing variable node vpi'To check node cjV2C message of (a);
the message is according to the updated C2V
Figure FDA0002614957790000038
Solving for variable node vpiThe specific calculation formula of the updated LLR value is as follows:
Figure FDA0002614957790000039
wherein, L' (v)pi) Representing variable node vpiUpdated LLR value, L (v)pi) Representing variable node vpiThe initial LLR values of the received channel,
Figure FDA00026149577900000310
represents check node cjTo variable node vpiC2V message;
the pair of all check nodes cj∈N(vpi) Update V2C message
Figure FDA00026149577900000311
The specific calculation formula of (A) is as follows:
Figure FDA00026149577900000312
wherein, N (v)pi)\cjIndicating the exception of check node cjAll-out and variable node vpiSet of connected check nodes, N (v)pi) Representing all and variable nodes vpiA set of connected check nodes that are,
Figure FDA00026149577900000313
check node cj'To variable node vpiThe information of (1).
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