CN110085643B - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
- Publication number
- CN110085643B CN110085643B CN201910357685.8A CN201910357685A CN110085643B CN 110085643 B CN110085643 B CN 110085643B CN 201910357685 A CN201910357685 A CN 201910357685A CN 110085643 B CN110085643 B CN 110085643B
- Authority
- CN
- China
- Prior art keywords
- power supply
- power
- display area
- supply lead
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
- H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
The embodiment of the invention discloses an array substrate and a display device. Wherein, the array substrate includes: a substrate base including a display region and a non-display region surrounding the display region; the first power supply leads and the gate drive circuit leads are arranged in the non-display area on the substrate, extend along a first direction and are distributed along a second direction; the plurality of first power supply leads are divided into at least two groups of first power supply lead groups, each group of first power supply lead groups comprises at least one first power supply lead, and a plurality of grid driving circuit leads are arranged between two adjacent groups of first power supply lead groups. According to the embodiment of the invention, the concentration of the arrangement of the first power supply lead is reduced, and the heat generated by the first power supply lead can be effectively diffused to the region where the grid drive circuit lead is located, so that the problem of heating of the first power supply lead is solved.
Description
Technical Field
The embodiment of the invention relates to a display technology, in particular to an array substrate and a display device.
Background
With the development of Active-matrix organic light emitting diode (AMOLED) display technology, the foldable display screen is receiving more and more attention from the market.
However, the technical development of the foldable display screen itself has many difficulties, for example, because the size of the foldable display screen is larger than that of a common mobile phone screen, the required screen body current is higher. In design, a single IC scheme is often used for cost consideration, which causes large current to be concentrated on power traces (especially ELVSS power traces) on the array substrate, which easily causes the power traces to generate heat, and may burn out the screen body especially in the highlight mode.
Disclosure of Invention
The invention provides an array substrate and a display device, which aim to solve the problem of heat generation of power supply wires.
In a first aspect, an embodiment of the present invention provides an array substrate, including:
a substrate base including a display area and a non-display area surrounding the display area;
the first power supply leads are used for transmitting first power supply voltage to the display area, the grid drive circuit leads are used for transmitting circuit control signals to the grid drive circuit positioned in the non-display area, and the first direction is intersected with the second direction;
the plurality of first power supply leads are divided into at least two groups of first power supply lead groups, each group of first power supply lead groups comprises at least one first power supply lead, and a plurality of grid driving circuit leads are arranged between two adjacent groups of first power supply lead groups.
Optionally, the non-display area includes a bending area, the first power supply lead, the gate driving circuit lead and the gate driving circuit lead all penetrate through the bending area in the first direction, and a plurality of holes are formed in portions of the first power supply lead, the gate driving circuit lead and the gate driving circuit lead, which are located in the bending area.
Optionally, the array substrate further includes a first power signal receiving bus and a first power signal output bus, where the first power signal receiving bus and the first power signal output bus are disposed in the non-display area on the substrate, the first power signal receiving bus is configured to receive the first power voltage signal, and the first power signal output bus is configured to output the first power voltage signal to the display area;
a first end of each of the first power supply leads is electrically connected with the first power supply signal receiving bus, a second end of each of the first power supply leads is electrically connected with the first power supply signal output bus,
preferably, the first power signal receiving bus is disposed on a side of the bending region away from the display region, and the first power signal outputting bus is disposed on a side of the bending region close to the display region.
Optionally, in the at least two first power supply lead groups and the gate driving circuit lead, one of the first power supply lead groups is closest to one side of the substrate base plate.
Optionally, the first direction is parallel to a side of the substrate base plate, and an extension line of a part of the first power supply lead in the first direction intersects with the display area.
Optionally, the array substrate further includes a plurality of control signal receiving traces and a plurality of control signal output traces, and the control signal receiving traces and the control signal output traces are disposed in the non-display area on the substrate;
the first end of the control signal output wire is electrically connected with the gate drive circuit, and the second end of the control signal output wire is electrically connected with the control signal receiving wire in a one-to-one correspondence manner through the leads of the gate drive circuit;
the control signal receiving wire is electrically insulated from the first power signal receiving bus, and the control signal output wire is electrically insulated from the first power signal output bus;
each of the control signal output traces extends along the first direction.
Optionally, the array substrate further includes a plurality of second power supply leads, disposed in the non-display area on the substrate, extending along the first direction and arranged along the second direction, and penetrating through the bending area in the first direction, the second power supply leads are used for transmitting a second power supply voltage signal to the display area, the second power supply leads are located on one side of any one of the first power supply leads away from the side edge,
preferably, the array substrate further includes a second power signal receiving bus and a second power signal output bus, the second power signal receiving bus is disposed in the non-display area on the substrate, the second power signal receiving bus is configured to receive the second power voltage signal, and the second power signal output bus is configured to output the second power voltage signal to the display area;
a first end of each second power supply lead is electrically connected with the second power supply signal receiving bus, and a second end of each second power supply lead is electrically connected with the second power supply signal output bus;
preferably, the second power supply lead penetrates through the bending region in the first direction, and a plurality of holes are formed in a part of the second power supply lead, which is located in the bending region;
preferably, the second power signal receiving bus is disposed on a side of the bending region away from the display region, and the second power signal output bus is disposed on a side of the bending region close to the display region.
Optionally, the first power supply lead, the gate driving circuit lead and the second power supply lead are located in the same layer.
Optionally, the first power supply lead is an ELVSS power supply lead.
In a second aspect, an embodiment of the present invention further provides a display device, including the array substrate according to the first aspect.
In the embodiment of the invention, a plurality of first power supply leads and a plurality of grid drive circuit leads which extend along a first direction and are distributed along a second direction are arranged in a non-display area of a substrate; the plurality of first power supply leads are divided into at least two groups of first power supply lead groups, wherein each group of first power supply lead groups comprises at least one first power supply lead, and a plurality of grid driving circuit leads are arranged between two adjacent groups of first power supply lead groups. The first power supply leads are separated by the grid drive circuit leads, so that the first power supply leads are distributed in a dispersed manner, and the concentrated heating of the first power supply leads is avoided; and the heat that the first power lead wire in each group of first power lead wire group that distributes produces can more evenly spread to the region at grid drive circuit lead wire place, has improved the thermal diffusion effect on the first power lead wire, has effectively reduced the heat that gathers on the first power lead wire. Therefore, in the embodiment of the invention, from the angle of layout wiring, the plurality of first power supply leads and the plurality of grid drive circuit leads are reasonably wired, and the plurality of first power supply leads are distributed in a scattered manner, so that the quantity of the first power supply leads distributed in a concentrated manner is reduced, heat generated by the first power supply leads can be effectively diffused to the region where the grid drive circuit leads are located, and the problem of heat generation of the first power supply leads is solved.
Drawings
Fig. 1 is a schematic structural view of a partial area of a conventional array substrate;
FIG. 2 is a circuit diagram of a conventional pixel driving circuit;
fig. 3 is a schematic structural diagram of a partial region of an array substrate according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a partial region of an array substrate according to yet another embodiment of the present invention;
fig. 5 is a schematic structural view of a partial region of an array substrate according to yet another embodiment of the present invention;
fig. 6 is a schematic structural view of a partial region of an array substrate according to yet another embodiment of the present invention;
fig. 7 is a schematic structural view of a partial region of an array substrate according to yet another embodiment of the present invention;
fig. 8 is a schematic structural view of a partial region of an array substrate according to yet another embodiment of the present invention;
fig. 9 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Along with the demand of people to the narrow frame effect of lower frame, there can be the design of bending zone when the lower frame designs. Fig. 1 is a schematic structural diagram of a partial area of a conventional array substrate, and specifically, fig. 1 shows a wiring situation at a lower right corner of the array substrate. As shown in fig. 1, in the non-display area 120 disposed around the display area 110, the ELVDD power supply lead 10, the gate driving circuit lead 12, and the ELVSS power supply lead 11 are sequentially arranged. Among them, the ELVDD power supply lead 10 is used to transmit an ELVDD power supply voltage to the pixel driving circuits in the display area 110, the ELVSS power supply lead 11 is used to transmit an ELVSS power supply voltage to the cathodes of the organic light emitting diodes OLED in the display area 110, and the gate driving circuit lead 12 is used to transmit circuit control signals (including a clock signal, a trigger signal, a power supply signal, and the like) to the gate driving circuit 13 located in the non-display area 120.
And one circuit structure of the pixel driving circuit may be as shown in fig. 2, the pixel driving circuit including a switching transistor T1, a driving transistor T2, and a storage capacitor Cst, a gate electrode of the driving transistor T2 being connected to one end of the storage capacitor Cst, a first electrode of the driving transistor T2 being connected to the other terminal of the storage capacitor Cst and an ELVDD power supply; the second electrode of the driving transistor T2 is connected to the anode of the OLED; the driving transistor T2 controls the amount of current flowing from the ELVDD power source to the ELVSS power source through the OLED to correspond to the value of the voltage stored in the storage capacitor Cst. At this time, the OLED emits light corresponding to the amount of current supplied from the driving transistor T2.
Obviously, when the OLED is driven to emit light by the pixel driving circuit, a large current is concentrated on the ELVSS power supply lead 11, which causes the ELVSS power supply lead 11 to generate heat in a concentrated manner, and thus the screen body is easily burned out.
In view of the above technical problems, embodiments of the present invention provide an array substrate, in which a power supply lead and a gate driving circuit lead on the array substrate are wired, so as to effectively solve the problem of heat generation of the power supply lead. Specifically, fig. 3 is a schematic structural diagram of a partial region of an array substrate according to an embodiment of the present invention. As shown in fig. 3, an array substrate provided in an embodiment of the present invention includes:
a substrate base plate 101, the substrate base plate 101 including a display area 110 and a non-display area 120 surrounding the display area 110;
a plurality of first power supply leads 21 and a plurality of gate driving circuit leads 12, both disposed in the non-display region 120 on the substrate base plate 101, extending along a first direction X and arranged along a second direction Y, the first power supply leads 21 being configured to transmit a first power supply voltage to the display region 110, the gate driving circuit leads 12 being configured to transmit a circuit control signal to the gate driving circuit 13 located in the non-display region 120, the first direction X intersecting the second direction Y;
the plurality of first power supply leads 21 are divided into at least two first power supply lead groups 20, each first power supply lead group 20 includes at least one first power supply lead 21, and a plurality of gate driving circuit leads 12 are disposed between two adjacent first power supply lead groups 20 (in the figure, the plurality of gate driving circuit leads 12 are illustrated by one gate driving circuit lead 12). Optionally, the Gate driving circuit 13 may be a Gate driving IC, or may also be a Gate In Panel (GIP) circuit, that is, a Gate driving chip is integrated on the Panel, so as to save the Gate driving chip, reduce the material cost, reduce the number of processes, and shorten the process time, thereby reducing the Panel cost and realizing a narrower frame.
In the embodiment of the present invention, the substrate base plate 101 may be a flexible base plate; the first power supply lead 21 and the gate driving circuit lead 12 are connected in a transition manner, and generally need to be arranged in different layers from the signal lines at the two ends thereof through a jumper wire. The first power supply lead 21 may be an ELVDD power supply lead or an ELVSS power supply lead, and considering that the current on the ELVSS power supply lead 11 is large, the generated heat may burn out the screen body, so that, optionally, the first power supply lead 21 in the embodiment of the present invention is an ELVSS power supply lead.
The circuit control signal may include a clock signal, a trigger signal, and a power signal, and correspondingly, the gate driving circuit lead 12 includes leads corresponding to the circuit control signal one by one to respectively transmit different signals.
It should be noted that fig. 3 only exemplarily shows that the plurality of first power supply leads 21 are divided into three first power supply lead groups 20, but the plurality of first power supply leads 21 may be divided into more first power supply lead groups 20 or two first power supply lead groups 20. Illustratively, as shown in fig. 4, the plurality of first power supply leads 21 are divided into two first power supply lead groups 20, and in this case, the gate driving circuit leads 12 are all disposed between the two first power supply lead groups 20. In addition, when the plurality of first power supply leads 21 are divided into two first power supply lead groups 20, a part of the gate driving circuit leads 12 may be disposed between the two first power supply lead groups 20, and another part of the gate driving circuit leads 12 may be disposed on the other side of one of the first power supply lead groups 20. The present invention does not limit the number of the first power supply leads 21 and the specific arrangement of the first power supply leads 21 and the gate driving circuit leads 12, and the first power supply leads 21 are arranged in a dispersed manner and a heat dissipation space is provided through the region where the gate driving circuit leads 12 are located, so that the concentrated heat generation of the first power supply leads 21 can be avoided, and the heat generation problem of the first power supply leads 21 can be improved.
In the embodiment of the invention, a plurality of first power supply leads and a plurality of grid drive circuit leads which extend along a first direction and are distributed along a second direction are arranged in a non-display area of a substrate; the plurality of first power supply leads are divided into at least two groups of first power supply lead groups, wherein each group of first power supply lead groups comprises at least one first power supply lead, and a plurality of grid driving circuit leads are arranged between two adjacent groups of first power supply lead groups. The first power supply leads are separated by the grid drive circuit leads, so that the first power supply leads are distributed in a dispersed manner, and the concentrated heating of the first power supply leads is avoided; and the heat that the first power lead wire in each group of first power lead wire group that distributes produces can more evenly spread to the region at grid drive circuit lead wire place, has improved the thermal diffusion effect on the first power lead wire, has effectively reduced the heat that gathers on the first power lead wire. Therefore, in the embodiment of the invention, from the angle of layout wiring, the plurality of first power supply leads and the plurality of grid drive circuit leads are reasonably wired, and the plurality of first power supply leads are distributed, so that the distribution concentration of the first power supply leads is reduced, heat generated by the first power supply leads can be effectively diffused to the region where the grid drive circuit leads are located, and the problem of heat generation of the first power supply leads is solved.
Optionally, fig. 6 is a schematic structural diagram of a partial region of an array substrate according to another embodiment of the present invention. As shown in fig. 6, the non-display area 120 includes a bending area 121, the first power supply lead 21 and the gate driving circuit lead 12 both penetrate through the bending area 121 in the first direction X, a plurality of holes 19 are formed in portions of the first power supply lead 21 and the gate driving circuit lead 12 located in the bending area 121, and a plurality of holes 19 are also formed in portions of the gate driving circuit lead 12 located in the bending area 121. Therefore, the bending performance of the first power supply lead 21 and the gate driving circuit lead 12 can be improved, the first power supply lead 21 and the gate driving circuit lead 12 are prevented from being broken, and abnormal display of the display device is prevented.
Optionally, fig. 5 is a schematic structural diagram of a partial region of an array substrate according to another embodiment of the present invention. As shown in fig. 5, based on the above embodiments, the array substrate of this embodiment may further include a first power signal receiving bus 14 and a first power signal output bus 15, which are disposed in the non-display area 120 on the substrate 101, wherein the first power signal receiving bus 14 is configured to receive a first power voltage signal, and the first power signal output bus 15 is configured to output the first power voltage signal to the display area 110;
the first end of each first power lead 21 is electrically connected to the first power signal receiving bus 14, and the second end of each first power lead 21 is electrically connected to the first power signal output bus 15, wherein the first power signal output bus 15 is located at a side of the bending region close to the display region, and the first power signal receiving bus 14 is located at a side of the bending region far from the display region.
At this time, the first power supply lead 21, the first power supply signal receiving bus 14 and the first power supply signal output bus 15 may be disposed around the gate driving circuit lead 12, and heat generated by the first power supply lead 21, the first power supply signal receiving bus 14 and the first power supply signal output bus 15 may be diffused to an area where the gate driving circuit lead 12 is located, so that heat on the first power supply lead 21 is effectively reduced, and the heat is uniformly distributed.
In this embodiment, since the ELVSS power supply voltages provided to the OLEDs in the display area are the same, the wiring around the display area in the non-display area can be performed in a bus manner, and thus, the wiring in the non-display area can also be simplified.
Optionally, the first power signal receiving bus 14 and the first power signal output bus 15 are located on the same layer, that is, the first power signal receiving bus 14 and the first power signal output bus 15 may be formed in the same process, so that the process flow is reduced, and the process cost is reduced. Meanwhile, a plurality of IC output pads 18 arranged along the second direction Y are disposed on the non-display area 120 of the array substrate, and the IC output pads 18 are used for binding the driving IC and are correspondingly electrically connected with pins of the driving IC; and the first power signal receiving bus 14 is electrically connected to the corresponding IC output pad 18 to obtain the first power voltage from the driving IC.
In addition, with reference to fig. 5, the array substrate may further include a plurality of control signal receiving traces 16 and a plurality of control signal output traces 17, which are disposed in the non-display area 120 on the substrate base plate 101; the first end of the control signal output wire 17 is electrically connected with the gate drive circuit 13, and the second end of the control signal output wire 17 is electrically connected with the control signal receiving wire 16 in a one-to-one correspondence manner through the lead 12 of the gate drive circuit; the control signal receiving trace 16 is electrically connected with the corresponding IC output pad 18 to acquire a circuit control signal from the driving IC; the control signal receiving trace 16 is electrically insulated from the first power signal receiving bus 14, and the control signal output trace 17 is electrically insulated from the first power signal output bus 15. For example, the control signal receiving trace 16 and the control signal output trace 17 may be located on the same layer, the control signal receiving trace 16 may be disposed across the first power signal receiving bus 14 to be electrically insulated from the first power signal receiving bus 14, or the control signal receiving trace 16 and the first power signal receiving bus 14 may be located on different layers.
Optionally, in the at least two first power supply lead groups and the gate driving circuit leads, at least one of the first power supply lead groups is closest to one side edge of the substrate base plate. For example, referring to fig. 3 to fig. 5, at least one first power lead group always exists on the substrate 101, and is disposed at the outermost side of the substrate 101, at this time, because the signal (current) in the first power lead 21 is stronger, the antistatic capability of the first power lead 21 is stronger, and the static electricity generated at the side end of the screen body can be resisted better, so that the antistatic capability of the screen body is improved; in addition, since each of the first power supply leads 21 is electrically connected to the first power supply signal receiving bus 14 and the first power supply signal output bus 15, even if the outermost first power supply lead 21 disposed on the substrate board 101 is damaged by static electricity, the transmission of the first power supply voltage by the other first power supply leads 21 is not affected, and the reliability of the panel is improved.
Optionally, fig. 6 is a schematic structural diagram of a partial region of an array substrate according to another embodiment of the present invention. As shown in fig. 6, the non-display area 120 includes a bending area 121, the first power supply lead 21 and the gate driving circuit lead 12 both penetrate through the bending area 121 in the first direction X, and a plurality of holes 19 are formed in portions of the first power supply lead 21 and the gate driving circuit lead 12 located in the bending area 121, so that the bending performance of the first power supply lead 21 and the gate driving circuit lead 12 can be improved, the first power supply lead 21 and the gate driving circuit lead 12 are prevented from being broken, and the display device is prevented from displaying abnormally.
However, it is considered that the opening of the first power supply lead 21 reduces the width of the first power supply lead 21, which increases the impedance of the first power supply lead 21 and thus increases the heat generation of the first power supply lead 21. Therefore, the embodiment of the invention improves the heating problem of the first power supply lead 21 by expanding the whole heat dissipation area of the first power supply lead 21 while ensuring the bending performance of the first power supply lead 21.
Fig. 7 is a schematic structural diagram of a partial region of an array substrate according to yet another embodiment of the present invention. As shown in fig. 7, the first direction X is parallel to one side (right side in the figure) of the base substrate 101, and an extension line 30 (shown by a dashed line frame in the figure) of a part of the first power supply lead 21 in the first direction X intersects with the display area 110. Compared with the existing wiring (the wiring shown in fig. 1), the lead area of the first power supply lead 21 in the embodiment is expanded toward the middle of the substrate base plate 101, so that a larger number of first power supply leads 21 can be arranged or the width of the first power supply lead 21 can be increased, thereby, on one hand, more space is provided for increasing the width of the first power supply lead 21, further the impedance of the first power supply lead 21 is reduced, on the other hand, the heat dissipation area of the first power supply lead 21 is further increased, the heat dissipation of the first power supply lead 21 is facilitated, and the heat generation problem of the first power supply lead 21 is improved.
Specifically, as shown in fig. 8, the array substrate may further include a plurality of second power supply leads 31 disposed in the non-display area 120 on the substrate base plate 101, extending along the first direction X and arranged along the second direction Y, the second power supply leads 31 are configured to transmit a second power supply voltage signal to the display area 110, and the second power supply leads 31 are located on one side of any one of the first power supply leads 21, which is far away from the side (the right side in the figure) of the substrate base plate 101. Illustratively, the first power supply lead 21 is an ELVSS power supply lead, the second power supply lead 31 is an ELVDD power supply lead, and the first power supply lead 21 and the second power supply lead 31 are adjacently disposed. Currently, referring to fig. 1, the ELVDD power supply leads are all located on the extension lines of the display area 110 corresponding to the ELVDD power supply signal transmission traces, so that the wiring area of the ELVSS power supply leads is small. Considering that the ELVDD power supply voltages required by the pixel driving circuits in the display area 110 are the same, fewer ELVDD power supply leads may be arranged to electrically connect the ELVDD power supply leads to more ELVDD power supply signal transmission traces in the display area, and further, in this embodiment, the lead area of the second power supply lead 31 may be compressed (the number of the second power supply leads 31 is reduced), and the vacant area is used for disposing the first power supply lead 21, so as to increase the heat dissipation area of the first power supply lead 21.
Similarly, the present embodiment may also transmit the second power voltage signal (ELVDD power voltage signal) to the display area 110 by routing a bus at the periphery of the display area 110. Optionally, referring to fig. 8, the array substrate further includes a second power signal receiving bus 32 and a second power signal output bus 33, which are disposed in the non-display area 120 on the substrate 101, wherein the second power signal receiving bus 32 is configured to receive a second power voltage signal, and the second power signal output bus 33 is configured to output the second power voltage signal to the display area 110;
a first end of each second power supply lead 31 is electrically connected with the second power supply signal receiving bus 32, and a second end of each second power supply lead 31 is electrically connected with the second power supply signal output bus 33; the second power signal receiving bus 32 is electrically connected to the corresponding IC output pad 18 to acquire a second power voltage signal from the driver IC.
In addition, the second power supply lead 31 penetrates through the bending region 121 in the first direction X and is connected to the display region 110, and a plurality of holes are formed in a portion of the second power supply lead 31 located in the bending region 121, so that the bending performance of the second power supply lead 31 can be improved, the second power supply lead 31 is prevented from being broken, and abnormal display of the display device is prevented.
Optionally, the first power supply lead 21, the gate driving circuit lead 12, and the second power supply lead 31 are located in the same layer, that is, the first power supply lead 21, the gate driving circuit lead 12, and the second power supply lead 31 may be formed in the same process, so that the process flow is reduced, and the process cost is reduced.
Optionally, in this embodiment, each control signal output trace 17 extends along the first direction X, that is, each control signal output trace 17 is linearly arranged, so that the process difficulty caused by bending and wiring is avoided.
In addition, an embodiment of the present invention further provides a display device, and fig. 9 is a schematic structural diagram of the display device provided in the embodiment of the present invention. Referring to fig. 9, the display device 200 may be a display panel including the array substrate 100 according to the embodiment of the present invention. The display device 200 may be a mobile phone, a computer, an intelligent wearable device, and the like.
It is to be understood that the foregoing is only illustrative of the preferred embodiments of the present invention and that the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (12)
1. An array substrate, comprising:
a substrate base including a display area and a non-display area surrounding the display area;
the first power supply leads are used for transmitting first power supply voltage to the display area, the grid drive circuit leads are used for transmitting circuit control signals to the grid drive circuit positioned in the non-display area, and the first direction is intersected with the second direction;
the plurality of first power supply leads are divided into at least two groups of first power supply lead groups, each group of first power supply lead groups comprises at least one first power supply lead, and a plurality of grid drive circuit leads are arranged between two adjacent groups of first power supply lead groups
The first direction is parallel to one side edge of the substrate base plate, and an extension line of part of the first power supply lead in the first direction is intersected with the display area;
the non-display area comprises a bending area; the array substrate further comprises a plurality of second power supply leads, the second power supply leads are arranged in the non-display area on the substrate, extend along the first direction and are arranged along the second direction, the first direction penetrates through the bending area, the second power supply leads are used for transmitting second power supply voltage signals to the display area, and the second power supply leads are located on any side, away from the side edges, of the first power supply leads.
2. The array substrate of claim 1, wherein the first power supply lead and the gate driving circuit lead both penetrate through the bending region in the first direction, and a plurality of holes are formed in portions of the first power supply lead and the gate driving circuit lead located in the bending region.
3. The array substrate of claim 2, further comprising a first power signal receiving bus and a first power signal output bus, the first power signal receiving bus and the first power signal output bus being disposed in the non-display area on the substrate, the first power signal receiving bus being configured to receive a first power voltage signal, the first power signal output bus being configured to output the first power voltage signal to the display area;
the first end of each first power supply lead is electrically connected with the first power supply signal receiving bus, and the second end of each first power supply lead is electrically connected with the first power supply signal output bus.
4. The array substrate of claim 3,
the first power signal receiving bus is arranged on one side, far away from the display area, of the bending area, and the first power signal output bus is arranged on one side, close to the display area, of the bending area.
5. The array substrate of claim 1, wherein one of the at least two first power supply lead groups and the gate driving circuit leads is closest to one side of the substrate.
6. The array substrate according to claim 3, wherein the array substrate further comprises a plurality of control signal receiving traces and a plurality of control signal output traces disposed in the non-display area on the substrate;
the first end of the control signal output wire is electrically connected with the gate drive circuit, and the second end of the control signal output wire is electrically connected with the control signal receiving wire in a one-to-one correspondence manner through the leads of the gate drive circuit;
the control signal receiving wire is electrically insulated from the first power signal receiving bus, and the control signal output wire is electrically insulated from the first power signal output bus;
each of the control signal output traces extends along the first direction.
7. The array substrate of claim 1,
the array substrate further comprises a second power signal receiving bus and a second power signal output bus, the second power signal receiving bus and the second power signal output bus are arranged in the non-display area on the substrate, the second power signal receiving bus is used for receiving the second power voltage signal, and the second power signal output bus is used for outputting the second power voltage signal to the display area;
the first end of each second power supply lead is electrically connected with the second power supply signal receiving bus, and the second end of each second power supply lead is electrically connected with the second power supply signal output bus.
8. The array substrate of claim 1,
the second power supply lead penetrates through the bending area in the first direction, and a plurality of holes are formed in the part, located in the bending area, of the second power supply lead.
9. The array substrate of claim 7,
the second power signal receiving bus is arranged on one side, far away from the display area, of the bending area, and the second power signal output bus is arranged on one side, close to the display area, of the bending area.
10. The array substrate of claim 1, wherein the first power supply lead, the gate driving circuit lead and the second power supply lead are located at a same layer.
11. The array substrate of claim 1, wherein the first power supply lead is an ELVSS power supply lead for transmitting a voltage to a cathode of the organic light emitting diode in the display area.
12. A display device comprising the array substrate according to any one of claims 1 to 11.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910357685.8A CN110085643B (en) | 2019-04-29 | 2019-04-29 | Array substrate and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910357685.8A CN110085643B (en) | 2019-04-29 | 2019-04-29 | Array substrate and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110085643A CN110085643A (en) | 2019-08-02 |
| CN110085643B true CN110085643B (en) | 2021-08-03 |
Family
ID=67417818
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910357685.8A Active CN110085643B (en) | 2019-04-29 | 2019-04-29 | Array substrate and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110085643B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20230165080A1 (en) * | 2021-01-29 | 2023-05-25 | Boe Technology Group Co., Ltd. | Display substrate and display device |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8610645B2 (en) * | 2000-05-12 | 2013-12-17 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
| KR100552963B1 (en) * | 2003-08-28 | 2006-02-15 | 삼성에스디아이 주식회사 | FPD with improved non-nuiform brightness |
| JP4886540B2 (en) * | 2006-03-01 | 2012-02-29 | キヤノン株式会社 | Organic EL element panel |
| JP5068067B2 (en) * | 2006-11-22 | 2012-11-07 | 株式会社ジャパンディスプレイイースト | Display device and flat display device |
| KR101174882B1 (en) * | 2010-06-15 | 2012-08-17 | 주식회사 엔씰텍 | Flat panel display apparatus, mother substrate for flat panel display apparatus, method of manufacturing flat panel display apparatus and method of manufacturing mother substrate for flat panel display apparatus |
| GB2510480B (en) * | 2012-12-21 | 2016-02-03 | Lg Display Co Ltd | Display device |
| KR102195166B1 (en) * | 2013-12-26 | 2020-12-24 | 엘지디스플레이 주식회사 | Top emission organic light emitting display device and method of manufacturing the same |
| CN104157233B (en) * | 2014-08-06 | 2017-04-12 | 京东方科技集团股份有限公司 | Flexible display panel |
| KR102305920B1 (en) * | 2015-04-30 | 2021-09-28 | 삼성디스플레이 주식회사 | Organic light emitting diode display |
| CN106816459B (en) * | 2017-02-28 | 2019-08-13 | 上海天马微电子有限公司 | A kind of flexible display substrates and flexible display apparatus |
| KR102409200B1 (en) * | 2017-06-01 | 2022-06-15 | 엘지디스플레이 주식회사 | Display apparatus including touch electrode and maunufacturing method for the same |
| JP2018205583A (en) * | 2017-06-07 | 2018-12-27 | 株式会社ジャパンディスプレイ | Display |
| CN207925468U (en) * | 2018-01-19 | 2018-09-28 | 昆山国显光电有限公司 | A kind of conducting wire and display device |
| CN109285962B (en) * | 2018-09-25 | 2020-12-01 | 合肥鑫晟光电科技有限公司 | Display substrate, manufacturing method and display device |
| CN109920836B (en) * | 2019-03-29 | 2022-04-01 | 云谷（固安）科技有限公司 | Display panel and display device |
-
2019
- 2019-04-29 CN CN201910357685.8A patent/CN110085643B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN110085643A (en) | 2019-08-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8432334B2 (en) | Organic light emitting display device | |
| CN112151696B (en) | Display panel and display device | |
| CN108154842B (en) | Organic light-emitting display panel and electronic equipment | |
| US20150243679A1 (en) | Display Device | |
| CN111128048B (en) | Display panel and display device | |
| CN113805378B (en) | Light-emitting substrate and display device | |
| CN110931541A (en) | Display panel and display device | |
| CN112711349A (en) | Touch display screen and touch display device | |
| CN110930941A (en) | Display module and display device | |
| CN109216425B (en) | Display panel and display device | |
| KR20220039795A (en) | Pixel driving circuit and display panel | |
| CN111312765B (en) | Display device and manufacturing method thereof | |
| CN114342368A (en) | Display substrate and display device | |
| CN210575959U (en) | Display panel and display device | |
| CN100452421C (en) | Display device, organic luminous display device and its producing method | |
| CN110085643B (en) | Array substrate and display device | |
| CN113823671B (en) | Display panel and display device | |
| CN115294936A (en) | Display panel and display device | |
| CN109273490B (en) | Display panel and preparation method thereof | |
| CN110931537B (en) | Display panel and display device | |
| CN111403468A (en) | Display panel and display device | |
| WO2022095549A1 (en) | Driving back plate, and display panel and preparation method therefor | |
| CN214481454U (en) | Flexible circuit board, lamp strip, backlight module and liquid crystal display device | |
| CN115020428A (en) | Array substrate, display panel and display device | |
| CN114649394A (en) | Display panel and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |