CN110085172B

CN110085172B - Gate driving device

Info

Publication number: CN110085172B
Application number: CN201910436566.1A
Authority: CN
Inventors: 林志隆; 李家伦; 陈福星; 郑贸薰; 吴柏融
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2018-06-14
Filing date: 2019-05-23
Publication date: 2020-10-09
Anticipated expiration: 2039-05-23
Also published as: CN110085172A

Abstract

The gate driving device includes a plurality of shift register circuits. The shift register circuit of the Nth stage comprises an output stage circuit, a first voltage regulator, a second voltage regulator, a third voltage regulator and a fourth voltage regulator. The output stage circuit provides a clock pulse signal or a first mode selection signal to generate an Nth stage gate driving signal according to the first control signal and the second control signal. The first voltage regulator regulates the first control signal according to the second mode selection signal. The second voltage regulator regulates the first control signal according to the switching signal and the reverse clock pulse signal. The third voltage regulator regulates the second control signal according to the first control signal. The fourth voltage regulator regulates the second control signal according to the reverse clock pulse signal.

Description

Gate driving device

Technical Field

The present invention relates to a gate driving device, and more particularly, to a gate driving device for driving a display panel.

Background

In the active light emitting diode pixel circuit with synchronous light emission, all pixels need to be turned on simultaneously in the compensation stage so as to compensate the variation of the on-voltage of the thin film transistors in the pixels simultaneously. In the next data writing stage, the pixel circuits are turned on column by column to write data into the pixel circuits column by column.

In the prior art, the pixel circuits emitting light synchronously have several problems. Firstly, special signals are required to be set in the pixel circuits which synchronously emit light to indicate the progress of a compensation stage and a data writing stage; second, when applied to a high-resolution display panel, a sufficiently long data writing time is required; third, when the thin film transistor is manufactured by applying the low temperature poly-silicon process in the gate driving circuit, the thin film transistor still has a relatively high electron mobility when it is turned off, and the leakage phenomenon is easily generated at the circuit node.

Disclosure of Invention

The invention provides a gate driving device which can be applied to a display panel with high resolution.

The gate driving device of the invention comprises a plurality of shift register circuits. The shift register circuits are coupled in series and respectively generate a plurality of gate driving signals, wherein the shift register circuit of the Nth stage comprises an output stage circuit, a first voltage regulator, a second voltage regulator, a third voltage regulator and a fourth voltage regulator. The output stage circuit has a first control terminal and a second control terminal for receiving the first control signal and the second control signal respectively. The output stage circuit provides a clock pulse signal or a first mode selection signal to charge the output end according to the first control signal and the second control signal so as to generate an Nth stage grid driving signal. The first voltage regulator is coupled to the first control terminal and provides a gate high voltage to regulate the first control signal according to the second mode selection signal. The second voltage regulator is coupled to the first control end and provides a front-stage grid driving signal or a starting pulse signal according to the switching signal and the reverse clock pulse signal so as to regulate the first control signal. The third voltage regulator is coupled to the second control terminal and provides a gate high voltage to regulate the second control signal according to the first control signal. The fourth voltage regulator is coupled to the first control terminal and regulates the second control signal according to the inverted clock pulse signal.

Based on the above, the gate driving apparatus of the present invention adjusts the control signal on the control terminal through the plurality of voltage regulators, and controls the output stage circuit to generate the gate driving signal according to the control signal. Therefore, the grid driver can generate a plurality of grid driving signals with consistent waveforms in the compensation stage and generate a plurality of grid driving signals which are respectively enabled in sequence in the later writing stage.

The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.

Drawings

Fig. 1 is a schematic diagram of a gate driving device according to an embodiment of the invention.

Fig. 2 is a waveform diagram illustrating the operation of the gate driving device according to the embodiment of the invention.

Fig. 3A to 3F are equivalent circuit diagrams of shift register circuits according to embodiments of the invention.

Wherein, the reference numbers:

100: shift register circuit

110: output stage circuit

120-150: voltage regulator

CE1, CE 2: control terminal

Q [ N ], P [ N ]: control signal

OE: output end

SS1, SS 2: mode selection signal

CK: clock pulse signal

CHA: switching signal

XCK: reverse clock pulse signal

G [ N ]: nth stage gate drive signal

T1-T10: transistor with a metal gate electrode

C1, C2: capacitor with a capacitor element

VGH: high voltage of gate

VGL: very low voltage of gate

G [ N-1 ]: preceding stage gate drive signal

ST: initial pulse signal

G_[N+1]: back stage gate drive signal

TA 0-TA 5: time interval

Detailed Description

The invention will be described in detail with reference to the following drawings, which are provided for illustration purposes and the like:

referring to fig. 1, fig. 1 is a schematic diagram illustrating a gate driving device according to an embodiment of the invention. The gate driving device comprises a plurality of shift register circuits coupled in series, and generates a plurality of gate driving signals respectively. Taking the shift register circuit 100 of the nth stage as an example, the shift register circuit 100 includes an output stage circuit 110 and a plurality of voltage regulators 120-150. The output stage circuit 110 has a first control terminal CE1 and a second control terminal CE 2. The first control end CE1 and the second control end CE2 respectively receive the first control signal Q_[N]And a second control signal P_[N]. The output stage circuit 110 is based on the first control signal Q_[N]And a second control signal P_[N]To provide the clock signal CK or the mode selection signal SS2 to charge the output OE and thereby generate the Nth stage gate driving signal G_[N]。

In the present embodiment, the output stage circuit 110 includes transistors T5, T10, capacitors C1, and C2. The first terminal of the transistor T5 receives the clock signal CK, the second terminal of the transistor T5 is coupled to the output terminal OE, and the control terminal of the transistor T5 is coupled to the first control terminal CE 1. The first terminal of the transistor T10 is coupled to the output terminal OE, the second terminal of the transistor T10 receives the mode selection signal SS2, and the control terminal of the transistor T10 is coupled to the second control terminal CE 2. In addition, the capacitor C1 is connected in series between the control terminal of the transistor T5 and the output terminal OE, and the capacitor C2 is connected in series between the control terminal of the transistor T10 and the output terminal OE.

The voltage regulator 120 is coupled to the first control terminal CE 1. The voltage regulator 120 provides the gate high voltage V according to the mode selection signal SS1_GHTo adjust the first control signal Q_[N]Wherein the voltage regulator 120 provides the gate high voltage V when the mode selection signal SS1 is at the low voltage level_GHTo pull up the first controlSignal Q_[N]The voltage value of (2). In the present embodiment, the mode selection signals SS1 and SS2 are used to indicate whether the shift register circuit 100 is in the compensation phase or the write phase.

In the present embodiment, the voltage regulator 120 includes transistors T3 and T4, the transistors T3 and T4 are sequentially connected in series to the first control terminal CE1 for connecting with the gate high voltage V_GHAnd (3) removing the solvent. The control terminals of the transistors T3 and T4 commonly receive the mode selection signal SS 1.

In other embodiments of the present invention, the voltage regulator 120 may include only a single transistor. In fact, the number of the transistors in the voltage regulator 120 may be limited by one or more transistors connected in series. The leakage phenomenon between the nodes can be reduced by the circuit structure of a plurality of transistors connected in series.

The voltage regulator 130 is coupled to the first control terminal CE 1. The voltage regulator 130 provides a front-stage gate driving signal G according to the switching signal CHA and the reverse clock signal XCK_[N-1]Or the start pulse signal ST to adjust the first control signal Q_[N]. Wherein, when the reverse clock signal XCK and the switching signal CHA are both at a low voltage level, the voltage regulator 130 can be driven according to the previous stage gate driving signal G_[N-1]Or the start pulse signal ST to adjust the first control signal Q_[N]The voltage value of (2).

Incidentally, when the shift register circuit 100 is a first stage shift register circuit, the voltage regulator 130 provides the start pulse signal ST to regulate the first control signal Q according to the switching signal CHA and the inverted clock signal XCK_[N]On the other hand, when the shift register circuit 100 is not the first stage, the voltage regulator 130 provides the front-stage gate driving signal G according to the switching signal CHA and the reverse clock signal XCK_[N-1]To adjust the first control signal Q_[N]The voltage value of (2).

In the present embodiment, the voltage regulator 130 includes transistors T1 and T2. The transistors T1 and T2 are connected in series, wherein the transistor T1 receives a previous stage gate driving signal G_[N-1]Or start pulse signal ST and controlled by the inverseTo the clock pulse signal XCK. The transistor T2 is coupled to the first control terminal CE1 and controlled by a switching signal CHA. It should be noted that the arrangement of the transistors T1 and T2 in fig. 1 can be interchanged, and the illustration in fig. 1 is merely an example and is not intended to limit the scope of the present invention.

The voltage regulator 140 is coupled to the second control terminal CE 2. The voltage regulator 140 is based on the first control signal Q_[N]To provide a gate high voltage V_GHTo adjust the second control signal P_[N]. Wherein, when the first control signal Q_[N]The voltage regulator 140 provides a high gate voltage V for low voltage potentials_GHTo pull up the second control signal P_[N]The voltage value of (2).

In the present embodiment, the voltage regulator 140 includes transistors T8 and T9. Transistors T8 and T9 are connected in series to the second control terminal CE2 for connecting with the gate high voltage V_GHAnd (3) removing the solvent. It should be noted that the number of transistors included in the voltage regulator 140 may be one or more than two. Fig. 1 is merely an illustrative example, and is not intended to limit the scope of the present invention.

The voltage regulator 150 is coupled to the second control terminal CE 2. The voltage regulator 150 regulates the second control signal P according to the inverse clock signal XCK_[N]. The voltage regulator 150 includes transistors T6 and T7, and the control terminals of the transistors T6 and T7 are commonly coupled to the first terminal of the transistor T6, forming a diode configuration. In the present embodiment, the cathodes of the diodes constructed by the transistors T6 and T7 receive the reverse clock signal XCK, and the anodes thereof are coupled to the second control terminal CE 2.

In other embodiments of the present invention, the number of transistors included in the voltage regulator 150 may be one or more than two, and fig. 1 is only an illustrative example, and is not intended to limit the scope of the present invention.

Referring to fig. 2 and fig. 3A to 3F together, the operation details of the shift register circuit 100 are shown, in which fig. 2 is a waveform diagram of the operation of the gate driving device according to the embodiment of the invention, and fig. 3A to 3F are equivalent circuit diagrams of the shift register circuit according to the embodiment of the invention.

Referring to fig. 2 and 3A, in the initial time interval TA0, when the inverted clock signal XCK is at a low voltage level (equal to the gate low voltage V)_GL) At this time, the transistors T6 and T7 are turned on in reverse, and the second control signal P is asserted_[N]Voltage value of equal to V_GL+|V_{TH_T6}L, wherein V_{TH_T6}Is the turn-on voltage of the transistor T6. Then, the reverse clock signal XCK is converted to high voltage alignment (equal to the gate high voltage V)_GH) The transistors T1 and T2 are turned off, and the transistors T3 and T4 in the voltage adjusting circuit 120 are turned on based on the mode selection signal SS1 transitioning to the low voltage level, and the voltage adjusting circuit 120 provides the gate high voltage V_GHTo pull up the first control signal Q_[N]. At this time, the transistor T10 in the output stage circuit 110 is controlled by the second control signal P_[N]Is turned on, and the transistor T5 in the output stage circuit 110 is turned on according to the first control signal Q_[N]Is turned off, the output stage circuit 110 generates the Nth stage gate driving signal G with a high voltage level_[N]. At the same time, the latter stage gate drive signal G generated by the latter stage shift register_[N+1]Also at a high voltage potential (equal to the gate high voltage V)_GH)。

Incidentally, in the initial time interval TA0, the transistors T8 and T9 of the voltage regulator 140 are based on being equal to the high voltage potential (equal to the gate high voltage V)_GH) First control signal Q_[N]And is disconnected.

Please refer to fig. 2 and fig. 3B. In time interval TA1, the gate driving device enters the compensation phase. At the same time, the switching signal CHA changes state to a high voltage level (equal to the gate high voltage V)_GH) The mode selection signal SS2 is transited to a low voltage level (equal to the gate low voltage V)_GL). Based on the mode selection signal SS2 changing to a low voltage level, the output stage circuit 110 is driven by the second control signal P_[N]To provide the mode selection signal SS2 to charge the output OE and enable the Nth stage of the gate driving signal G_[N]Is pulled down to be equal to the gate low voltage V_GL。

Corresponding to the Nth stage gate drive signal G_[N]By the coupling effect of the capacitor C2, the second control signal P_[N]Is correspondingly pulled down to be equal to V_GL+|V_{TH_T6}L- Δ V. The magnitude of Δ V is determined according to the ratio of the capacitance of the capacitor C2 to the equivalent capacitance of the second control terminal CE 2.

It is noted that the gate driving signal G is at this time and before_[N-1]Or the transistors T1, T2 of the voltage regulator 130 associated with the start pulse signal ST are turned off, so that all the shift register circuits in the gate driving device can synchronously generate the voltage V equal to the gate low voltage_GLThat is, the subsequent gate driving signal G at this time_[N+1]Is equal to the gate low voltage V_GL。

Please refer to fig. 2 and fig. 3C. At time interval TA2, the gate driving apparatus ends the compensation phase and is ready to enter the writing phase. During time interval TA2, the mode select signal SS2 transitions to a high voltage level (equal to the gate high voltage V)_GH). The Nth stage gate driving signal G is driven by the transistor T10 maintained to be turned on in the output stage circuit 110_[N]Is pulled up to the gate high voltage V according to the mode selection signal SS2_GH. And, the second control signal P is generated by the coupling effect of the capacitor C2_[N]Is pulled up to a voltage value equal to V_GL+|V_{TH_T6}And based on the condition that the transistors T3, T4 in the voltage regulator 120 are continuously turned on, the first control signal Q_[N]Is maintained to be equal to the gate high voltage V_GH。

On the other hand, the mode selection signal SS2 received based on all the shift register circuits is the same, so that the (N + 1) th stage gate driving signal G is generated during the time interval TA2_[N+1]Is synchronously pulled up to the gate high voltage V according to the mode selection signal SS2_GH. In this way, the gate driving device can enable (pull down) all the gate driving signals at the same time, and can perform the compensation operation of the thin film transistors of all the pixel circuits.

Please refer to fig. 2 and fig. 3D. In time interval TA3, the gate driving device enters the writingThe first sub-phase of the phase. During time interval TA3, the mode select signal SS1 transitions to a high voltage level (equal to the gate high voltage V)_GH) And the switching signal CHA is transited to a low voltage level (equal to the gate low voltage V)_GL). At the same time, the voltage regulator 130 is turned on according to the switching signal CHA and the reverse clock signal XCK, and receives a low voltage level (equal to the gate low voltage V)_GL) The start pulse signal ST. The first control signal Q is supplied via the turned-on transistors T1, T2_[N]Is pulled low according to the start pulse signal ST, at which time the first control signal Q is pulled low_[N]Voltage value of equal to V_GL+|V_{TH_T1}L, wherein V_{TH_T1}Is the turn-on voltage of the transistor T1.

Following the first control signal Q_[N]Is pulled low, the transistors T8, T9 in the voltage regulator 140 are turned on. Thus, the second control signal P_[N]According to the high voltage V of the grid_GHIs pulled high. In the present embodiment, the second control signal P_[N]Can be pulled up to be slightly lower than the gate high voltage V during the time interval TA3_GHVoltage V of_GM. Wherein, V_GH＞V_GM＞V_GL+|V_{TH_T6}L. At the same time, the transistor T5 is kept turned on, the transistor T10 is kept turned off, and the nth stage gate driving signal G_[N]Is maintained to be equal to the gate high voltage V_GH。

It should be noted that the voltage regulator 130 may receive the start pulse signal ST, or may also receive the previous stage gate driving signal G_[N-1]. The voltage regulator 130 can determine to receive the start pulse signal ST or the previous stage gate driving signal G according to the position of the shift register circuit_[N-1]. Briefly, when the voltage regulator 130 belongs to the shift register circuit of the first stage, the voltage regulator 130 can receive the start pulse signal ST, and when the voltage regulator 130 does not belong to the shift register circuit of the first stage, the voltage regulator 130 can receive the gate driving signal G of the previous stage_[N-1]。

Please refer to fig. 2 and fig. 3E. In time interval TA4, the gateThe drive means enters the second sub-phase of the write phase. In the time interval TA4, the voltage value of the start pulse signal ST is pulled up to the gate high voltage V_GH. The reverse clock signal XCK and the switching signal CHA transition to high voltage levels, turning off the transistors T1, T2 in the voltage regulator 130. On the other hand, the clock signal CK is driven by the gate high voltage V_GHSwitching state to gate low voltage V_GL. The Nth stage gate driving signal G is driven by the transistor T5 which is maintained to be turned on_[N]Is pulled down to a gate low voltage V_GL。

Please note that the Nth level gate driving signal G is used_[N]Is pulled down, the first control signal Q is coupled through the coupling effect of the capacitor C1_[N]Can be further pulled down to V_GL+|V_{TH_T1}I-AV. And in the first control signal Q2_N]May be further pulled low, the transistors T8, T9 of the voltage regulator 140 may be turned on, and the second control signal P is enabled_[N]Is pulled up to a gate high voltage V_GH。

Please refer to fig. 2 and fig. 3F. During time interval TA5, the gate driving device enters a voltage holding phase. In time interval TA5, the Nth stage of the gate driving signal G_[N]Is transmitted to the shift register circuit of the next stage to become the front stage gate drive signal of the shift register circuit of the next stage and drive the (N + 1) th stage gate drive signal G generated by the shift register circuit of the next stage_[N+1]Is pulled down to a gate low voltage V_GL. In addition, the transistor T1 is turned on periodically according to the clock signal CK with periodic transition state for the first control signal Q_[N]Periodically charged to maintain the first control signal Q_[N]Is equal to the gate low voltage V_GL. The transistor T5 is pulled down according to the first control signal Q_[N]Is disconnected. On the other hand, the voltage regulator 150 is controlled by the second control signal P according to the inverted clock signal XCK_[N]And (4) periodic charging. To drive the second control signal P_[N]Is lowered and maintained at V_GL+|V_{TH_T6}And causes transistor T10 to be turned on. Nth stage gate driving signal G_[N]Then transits according to the mode selection signal SS2 and maintains at the gate high voltage V_GH。

As can be readily understood from the above description, in the writing stage, the gate driving device can generate sequentially enabled (pulled down) gate driving signals and sequentially perform data writing operations on a plurality of pixel rows by sequentially transmitting the pulled down gate driving signals.

In summary, the present invention provides a shift register circuit, and a gate driving signal is formed by a plurality of shift register circuits connected in series. The gate driving signals provided by the invention can provide a plurality of commonly enabled gate driving signals in the compensation stage and generate sequentially enabled gate driving signals in the writing stage so as to provide enough time to perform data writing action. The display panel can be effectively matched with a synchronous active organic light-emitting diode and is applied to a display panel with high resolution. In addition, in the embodiment of the invention, the voltage regulator is constructed by a plurality of transistors connected in series, so that the leakage phenomenon of internal nodes can be reduced, and the power consumption is saved.

The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A gate driving apparatus, comprising:

a plurality of shift register circuits coupled in series to each other for generating a plurality of gate driving signals, wherein the shift register circuit of the nth stage includes:

an output stage circuit having a first control terminal and a second control terminal for receiving a first control signal and a second control signal respectively, and providing a clock signal or a first mode selection signal to an output terminal according to the first control signal and the second control signal to generate an nth stage gate driving signal;

a first voltage regulator coupled to the first control terminal for providing a gate high voltage according to a second mode selection signal to regulate the first control signal;

a second voltage regulator coupled to the first control terminal for providing a pre-stage gate driving signal or a start pulse signal according to a switching signal and a reverse clock signal to regulate the first control signal;

a third voltage regulator coupled to the second control terminal for providing the gate high voltage to regulate the second control signal according to the first control signal; and

a fourth voltage regulator coupled to the second control terminal for regulating the second control signal according to the inverted clock signal.

2. The gate driving apparatus of claim 1, wherein during a compensation phase, the second voltage regulator is turned off according to the switching signal, the first voltage regulator is turned on according to the second mode selection signal, and the gate high voltage is provided to pull up the first control signal.

3. The apparatus of claim 2, wherein the third voltage regulator is turned off according to the first control signal, the fourth voltage regulator is turned off, and the second control signal is pulled down during the compensation phase.

4. The gate driving device as claimed in claim 3, wherein the output stage circuit provides the first mode selection signal to the output terminal according to the second control signal and generates the Nth stage gate driving signal during the compensation stage.

5. The gate driving apparatus as claimed in claim 2, wherein the first voltage regulator is turned off according to the second mode selection signal, and the second voltage regulator is turned on according to the switching signal and the pulled-down backward clock signal to transmit the previous gate driving signal or the start pulse signal to pull down the first control signal during a first sub-phase of a writing phase.

6. The gate driving apparatus as claimed in claim 5, wherein the third voltage regulator is turned on according to the first control signal and provides the gate high voltage to pull up the second control signal, and the fourth voltage regulator is turned on during the first sub-phase of the writing phase.

7. The apparatus of claim 5, wherein the second voltage regulator is turned off according to the inverted clock signal being pulled up during a second sub-phase of the write phase, and the first control signal is pulled down by an offset value according to the clock signal being pulled down.

8. The gate driving device as claimed in claim 7, wherein the output stage circuit provides the clock signal to the output terminal according to the first control signal and generates the nth stage gate driving signal.

9. The gate driving device as claimed in claim 2, wherein during a voltage holding period, the second voltage regulator is turned on periodically according to the clock signal and charges the first control signal periodically, the first voltage regulator and the third voltage regulator remain turned off, and the fourth voltage regulator is turned on periodically according to the inverted clock signal and charges the second control signal periodically.

10. The gate driving device as claimed in claim 9, wherein the output stage circuit provides the first mode selection signal to generate the nth stage gate driving signal according to the second control signal during the voltage holding stage.

11. A gate driver according to claim 1, wherein the output stage circuit comprises:

a first transistor, a first terminal of which receives the clock signal, a second terminal of which is coupled to the output terminal, and a control terminal of which receives the first control signal;

a first capacitor coupled between the control terminal of the first transistor and the output terminal;

a second transistor, a first terminal of which is coupled to the output terminal, a second terminal of which receives the first mode selection signal, and a control terminal of which receives the second control signal; and

a second capacitor coupled between the control terminal of the second transistor and the output terminal.

12. The gate driving apparatus of claim 1, wherein the first voltage regulator comprises:

at least one transistor coupled between the first control terminal and the gate high voltage, the control terminal of the at least one transistor receiving the second mode selection signal.

13. The gate driving apparatus of claim 1, wherein the second voltage regulator comprises:

a first transistor, a first end of which receives the preceding stage gate driving signal or the start pulse signal, and a control end of which receives the reverse clock pulse signal; and

a second transistor, wherein a first terminal of the second transistor is coupled to the second terminal of the first transistor, a second terminal of the second transistor is coupled to the first control terminal, and a control terminal of the second transistor receives the switching signal.

14. A gate driver according to claim 1, wherein the third voltage regulator comprises:

at least one transistor coupled between the second control terminal and the gate high voltage, the control terminal of the at least one transistor receiving the first control signal.

15. A gate driver according to claim 1, wherein the fourth voltage regulator comprises:

a diode having a cathode receiving the inverted clock signal and an anode coupled to the second control terminal.

16. A gate driver according to claim 15, wherein the diode comprises:

a first transistor, the first end and the control end of which receive the reverse clock pulse signal; and

a second transistor, wherein a first terminal of the second transistor is coupled to a second terminal of the first transistor, a control terminal of the second transistor receives the inverted clock signal, and a second terminal of the second transistor is coupled to the second control terminal.

17. The gate driving device as claimed in claim 1, wherein the gate driving signals are enabled simultaneously during a compensation phase, the gate driving signals are enabled sequentially during a write phase, and the gate driving signals are maintained at a disabled voltage value during a voltage holding phase, wherein the compensation phase, the write phase and the voltage holding phase occur sequentially.