CN110085157A - Clock generating circuit, driving chip, display device and clock signal generating method - Google Patents
Clock generating circuit, driving chip, display device and clock signal generating method Download PDFInfo
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- CN110085157A CN110085157A CN201910330893.9A CN201910330893A CN110085157A CN 110085157 A CN110085157 A CN 110085157A CN 201910330893 A CN201910330893 A CN 201910330893A CN 110085157 A CN110085157 A CN 110085157A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
Abstract
The invention discloses a kind of clock signal generating methods, comprising: carries out content comparison to the image data of successive frame, and judges described image data for still image or dynamic image；When described image data are dynamic image, the first clock signal is generated；When described image data are still image, second clock signal is generated, the refreshing frequency shown according to the first clock signal or second clock signal control image；Wherein, the frequency of first clock signal is higher than the frequency of the second clock signal.The invention also discloses a kind of clock generating circuit, driving chip and display devices.Clock generating circuit, display device and clock signal generating method disclosed in this invention reduce the driving chip number of image frames per second that can refresh, reduce frame per second, reduce unnecessary energy loss.
Description
Technical field
The present invention relates to image display technology fields, and in particular to a kind of clock generating circuit, driving chip, display
Device and clock signal generating method.
Background technique
Frame per second (Frame rate, referred to as: FR) is the measurement for measuring display frame number, and measurement unit is display frame per second
Number (Frames per Second, referred to as: FPS) or " hertz (Hz) ".Frequency can be used for frame number (FPS) per second in other words
Indicate the number that each second can update when graphics processor Treatment stations.High frequency is available more smooth, more true to nature to be moved
It draws.In general, the frame per second of 30Hz or so is exactly user's acceptable, but if by performance boost to 60Hz, can be with
Significantly promote interaction sense and realism.
The frame per second of driving chip mainly passes through chip OSC (Oscillator, oscillator) clock frequency and chip interior the
One counter is realized；Under normal circumstances, the resolution ratio of the refreshing frame per second and display panel that are required according to display panel, can push away
The time that driving chip scanning display panel one-row pixels need is calculated, obtains the first meter further according to this time and OSC clock value
The count value of number device.The OSC clock value and after OTP (One Time Programmable, One Time Programmable) burning
The count value of one counter is fixed, therefore the frame per second of driving chip is also fixed.
Therefore, at present some electronic equipments (such as mobile phone, computer or TV) when displaying an image, the driving chip frame
The size and picture quality of rate have very big relationship, and the in general frame per second the big, show that image is more clear, but simultaneously, improve
Frame per second also means that the more energy of consumption, especially in some unnecessary situations, for example shows within a certain period of time
When identical image.
Summary of the invention
In order to solve the above-mentioned technical problems, the present invention provides a kind of clock generating circuit, driving chip, display dresses
It sets and clock signal generating method, the refresh frame of driving chip is adjusted when image data is dynamic image or still image
Rate reduces energy loss while guaranteeing display effect.
A kind of clock generating circuit provided according to the present invention, comprising: data comparison module, for successive frame
Image data carries out content and compares to judge whether it is still image or dynamic image；Oscillator, for generating reference pulse letter
Number；First counter, for counting the reference pulse to generate the first clock when described image data are dynamic image
Signal；Second counter is used for when described image data are still image, when counting the reference pulse to generate second
Clock signal, wherein the frequency of first clock signal is higher than described and second clock signal frequency, the clock signal hair
Raw circuit provides one of first clock signal and the second clock signal to control the frame per second that image is shown.
Preferably, when the picture data content of adjacent two frame is identical and maintains N frame, described image data are static map
Picture, wherein N is the integer greater than 2.
Preferably, when the picture data content of adjacent two frame is different or adjacent two field pictures data content is identical but maintains not
When to N frame, described image data are dynamic image, wherein N is the integer greater than 2.
Preferably, first counter and second counter do not work at the same time.
Preferably, when second counter starts counting, the first counter pause is counted；When second meter
When number device stops counting, first counter continues to count from the counting position of pause.
Preferably, the clock generating circuit further include: third counter, for when described image data are in dynamic
When image and still image switch, the reference pulse is counted to generate third clock signal, wherein third clock signal
Frequency is located between the frequency of first clock signal and the frequency of second clock signal.
A kind of driving chip provided according to the present invention, the driving chip include any one of the claims 1-6
The clock generating circuit, the clock generating circuit provide the clock signal.
A kind of display device provided according to the present invention, comprising: display panel, the display panel include multiple grids
Line, multiple data lines and multiple pixels, the multiple pixel are respectively connected to the multiple grid line and are respectively connected to institute
State multiple data lines；Gate driving circuit, the gate driving circuit have an input terminal, the input terminal receive clock signal with
And the driving voltage of the multiple grid line of driving；And data drive circuit, the data drive circuit are configured to driving institute
State multiple data lines, wherein the display device further includes driving chip according to claim 7, the driving chip
For receiving picture signal and driving signal from external source, with to the gate driving circuit provide the clock signal with
And the driving voltage is provided to the data drive circuit.
Preferably, when second counter counts, the clock generating circuit is sent to the driving chip
Signal is controlled, the gate driving circuit and data drive circuit works state are controlled.
Preferably, when second counter counts, the gate driving circuit drives according to preset scanning mode
The display panel.
Preferably, the display panel include: liquid crystal display panel, organic light emitting display panel, field emission display panel,
Electric slurry display panel, electrophoretic display panel or Electrowetting display panel.
A kind of clock signal generating method provided according to the present invention characterized by comprising to the picture number of successive frame
According to progress content comparison, and judge described image data for still image or dynamic image；When described image data are Dynamic Graph
When picture, the first clock signal is generated；When described image data are still image, second clock signal is generated, when according to first
The refreshing frequency that clock signal or second clock signal control image are shown；Wherein, the frequency of first clock signal is higher than institute
State the frequency of second clock signal.
Preferably, when the picture data content of adjacent two frame is identical and maintains N frame, described image data are static map
Picture, wherein N is the integer greater than 2.
Preferably, when the picture data content of adjacent two frame is different or adjacent two field pictures data content is identical but maintains not
When to N frame, described image data are dynamic image, wherein N is the integer greater than 2.
Preferably, the reference pulse is counted by the first counter to generate the first clock signal；Pass through
Two counters count the reference pulse to generate second clock signal.
Preferably, when second counter starts counting, the first counter pause is counted；When second meter
When number device stops counting, first counter continues to count from the counting position of pause.
Preferably, further includes: when described image data are when dynamic image and still image switch, generation third clock is believed
Number, wherein the frequency of third clock signal is located between the frequency of first clock signal and the frequency of second clock signal.
The beneficial effects of the present invention are: judging image data for dynamic image or still image according to picture data content
When, when image data is dynamic image, the display of image is controlled using the first clock signal of upper frequency；Work as picture number
When according to for still image, the display of image is controlled using the second clock signal of lower frequency.Different image datas uses
Different frame per second are shown, reduce energy loss.
Further, when dynamic image and still image switch, the frequency for being gradually lowered or increasing clock signal is real
Switching between existing first clock signal and second clock signal, the display of image caused by preventing frame per second to be mutated is abnormal, improves figure
As display quality.
Further, when image data is still image, gate driving circuit and the source drive electricity of display device
Road does not work, and further reduced energy consumption.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from.
Fig. 1 shows the structural schematic diagram of clock generating circuit provided in an embodiment of the present invention；
Fig. 2 shows the structural schematic diagrams of display device provided in an embodiment of the present invention；
Fig. 3 shows the working principle diagram of display device provided in an embodiment of the present invention；
Fig. 4 shows the working signal waveform diagram of display device provided in an embodiment of the present invention；
Fig. 5 shows the flow chart of clock signal generating method provided in an embodiment of the present invention.
Specific embodiment
To facilitate the understanding of the present invention, a more comprehensive description of the invention is given in the following sections with reference to the relevant attached drawings.In attached drawing
Give presently preferred embodiments of the present invention.But the present invention can be realized by different forms, however it is not limited to be retouched herein
The embodiment stated.Opposite, purpose of providing these embodiments is keeps the understanding to the disclosure more thorough complete
Face.
Unless otherwise defined, all technical and scientific terms used herein and belong to technical field of the invention
The normally understood meaning of technical staff is identical.Used term is intended merely to description specifically in the description of the invention herein
Embodiment purpose, it is not intended that in limitation the present invention.
In the following, referring to attached drawing, the present invention is described in detail.
Fig. 1 shows the structural schematic diagram of clock generating circuit provided in an embodiment of the present invention.As shown in Figure 1, described
Clock generating circuit 110 includes: oscillator 111, the first counter 113, the second counter 114 and data comparison module
112。
Wherein, oscillator 111 is to generate reference pulse signal (such as OSC pulse signal).
Data comparison module 112 carries out content to the image data to successive frame and compares to judge whether it is still image
Or dynamic image.
In the present embodiment, data comparison module 112 to successive frame image data carry out content compare when, if adjacent two
The picture data content of frame is identical and maintains N frame still identical, then the image data is still image；If the figure of adjacent two frame
As data content difference or adjacent two field pictures data content is identical but maintenance is still identical less than N frame, then the image data is
Dynamic image.Wherein, N is the integer greater than 2.
It when being read out display to the identical image data of consecutive numbers frame, does not need to maintain original refreshing frame per second, only
It is above just to need for refreshing frame per second to be at this time maintained at the minimum frame per second requirement of human eye acceptable, can not influence in this way
The loss appropriate for reducing energy under the premise of display effect.
Specifically, if the picture data content of adjacent two frame is identical, then compare whether this identical image data of two frames is tieed up
It is still identical to hold N frame, if maintaining N frame identical, for still image.Such as data comparison module 112 detects the figure of a certain frame
Picture data are image A, and the image data of next frame is also image A, and since the frame, to be shown in continuous N frame
The image data shown is image A, then can determine whether that the image data is still image.Suspend the first counter at this time and starts the
Two counters reduce the refreshing frame per second that image is shown, such as frame per second are reduced to 30Hz from 60Hz.
If received adjacent two field pictures data content it is not identical or adjacent two field pictures data content is identical but does not have
Have and maintain N frame still identical, is then dynamic image.Such as data comparison module 112 detects the image data of a certain frame for figure
As A, the image data of next frame is image B or the image data of a certain frame is image A, the image data of next frame
Also be image A, but since the frame, image B occur in continuous N frame, then judge this image for dynamic image, at this time
Start the first counter, do not start the second counter, maintains original image refreshing frame per second (such as 60Hz) constant.
First counter 113 is used to count reference pulse signal, and generate first when image data is dynamic image
Clock signal.
Second counter 114 is used to count reference pulse signal, and generate second when image data is still image
Clock signal.
In the present embodiment, the first counter 113 counts the failing edge or rising edge of reference pulse signal and generates first
Clock signal；Second counter 114 counts the failing edge or rising edge of reference pulse signal and generates second clock signal.Its
In, the frequency of the first clock signal is higher than the frequency of second clock signal.First counter 113 and the second counter 114 will not
It is counted in the reference pulse signal that synchronization generates oscillator 111.Specifically, when the second counter 114 starts to count
When number, the first counter 113 can suspend counting；When the second counter 114 stops counting, the first counter 113 can be from pause
Counting position continue to count.
First clock signal and second clock signal can be supplied to the gate driving circuit and data-driven of display panel
Circuit controls the display panel complete primary charging refreshing to each pixel on display panel with different refreshing frequencys respectively,
And then realize the display of image.
In a preferred embodiment, the first clock signal and second clock signal are STV (Start
Vortical, frame unbalanced pulse) signal.Display panel shows that the time of one-row pixels is a vibration by oscillator reference clock
The period is swung multiplied by the sum of the first counter and the count value of the second counter, or to be counted by the reference pulse period multiplied by first
The integral multiple of the sum of the count value of device and the second counter.
In a preferred embodiment, the clock generating circuit further includes third counter 115, the third
Counter 115 can be when image data carries out the switching of dynamic image and still image, to the benchmark arteries and veins of the generation of oscillator 111
It rushes signal to be counted, and generates third clock signal.
Wherein, the frequency of third clock signal be located at the first clock signal frequency and second clock signal frequency it
Between, display can be made to have one when first refreshes between frame per second (such as 60Hz) and the second refreshing frame per second (such as 30Hz) and jump
The buffering course (such as first become 45Hz from 60Hz, then become 30Hz) of frame per second adjustment avoids the shadow due to jump of frame per second difference is excessive
Ring the display effect of image.
The third counter 115 can wrap containing multiple, realize smaller frame per second stepping section to facilitate, and guarantee to reduce
Better display effect is realized while energy consumption.
Clock generating circuit disclosed in the present embodiment can be still image in the image data of required display
When, display frame rate is reduced automatically, meanwhile, when image data is dynamic image, it is increased to original display frame rate, Jin Er automatically
While ensure that the display effect of image data, the power consumption of chip is reduced.
Fig. 2 shows the structural schematic diagrams of display device provided in an embodiment of the present invention.Fig. 3 shows offer of the embodiment of the present invention
Display device working principle diagram.As shown in Figures 2 and 3, the display device includes: driving chip 100, gate driving electricity
Road 200, data drive circuit 300 and display panel 400.
Wherein, include multiple gate lines G L1 to GLn in display panel 400, and intersect with gate lines G L1 to GLn more
A data line DL1 to DLm and multiple pixel PX11 to PXnm, each of pixel PX11 to PXnm with gate lines G L1
Into GLn, the corresponding data line into DLm is connected corresponding grid line with data line DL1.
The structure of display panel 400 can be such as liquid crystal display panel, organic light emitting display panel, field emission display face
Plate, electric slurry display panel, electrophoretic display panel or Electrowetting display panel, but the present invention and its appended claims are not limited to
This.
Driving chip 100, driving chip 100 is for receiving picture signal and driving signal from external source, with to grid
Pole driving circuit 200 provides clock signal and provides the driving voltage to data drive circuit 300.
In the present embodiment, driving chip 100 can (Display Driver Integrated Circuit be shown for DDIC
Show drive integrated circult), it receives and MIPI is passed through by application processor (Application Processor, referred to as: AP)
The image data of (Mobile Industry Processor Interface, mobile communications industry processor) interface transmission, should
Image data includes still image and dynamic image.
Driving chip 100 includes clock generating circuit 110 described in Fig. 1, for by image data
Content relatively judges that image data for dynamic image or still image, and exports the first clock signal and the according to judging result
One of two clock signals, control gate drive circuit 200 and data drive circuit 300 are driven with different refreshing frame per second
400 display image data of display panel.The structure of clock generating circuit is as shown in Figure 1, details are not described herein.
Driving signal includes vertical synchronizing signal Vsync, horizontal synchronizing signal Hsync and data enable signal, wherein is hung down
Straight synchronization signal Vsync is used as the signal that the frame period is distinguished from each other out, horizontal synchronizing signal Hsync as by horizontal cycle that
This signal distinguished, data enable signal are maintained at high level during the period that data are exported and input week with designation date
Phase.
Gate driving circuit 200 has input terminal, and input terminal receives clock signal and the multiple grid line of driving
Driving voltage.
In the present embodiment, gate driving circuit 200 is connected with gate lines G L1 to GLn, is connected with driving chip 100, in work
Driving signal and clock signal that driving chip 100 is sent are received when making, and grid line scanning is exported by gate lines G L1 to GLn
Signal drives corresponding pixel in display panel 400 to light.
Gate driving circuit 200 sequentially exports high level square wave to each row grid line, by these grid within the time of a frame
The corresponding pixel thin film transistor of polar curve is opened line by line, so that grid line completes primary charging to sub-pixel all in pixel region
Refresh.Meanwhile the unlatching of gate driving circuit at least needs one group of STV trigger signal.
300 data drive circuit of data drive circuit is configured to drive multiple data lines.
In the present embodiment, data drive circuit 300 is connected with data line DL1 to DLn, is connected with driving chip 100, in work
The data-signal and clock signal that driving chip 100 is sent are received when making, and through data line DL1 to DLn into display panel
Respective pixel provide grayscale signal.
Data drive circuit is used for when gate driving circuit opens the thin film transistor (TFT) of liquid crystal display panel lastrow,
By the gray scale voltage of capacitor charge and discharge thereon to pre-display.
In a preferred embodiment, clock generating circuit 110 be may also set up in outside driving chip 100.
In a preferred embodiment, during the counting of the second counter 114, i.e., image data is still image
When, at this time since the image data of required display is still image, so without to display panel convey new clock signal and
Data-signal, therefore, clock generating circuit 110 can be by sending control signal to driving chip, and then control grid
The working condition of driving circuit 200 and data drive circuit 300, such as control gate drive circuit 200 and data drive circuit 300
It does not work during the counting of the second counter 114, to reduce unnecessary energy loss.
In a preferred embodiment, during the counting of the second counter 114, gate driving circuit 200 and data
Driving circuit 300 can also drive display panel according to preset scanning mode.
Specifically, display panel 400 receives pixel data stream by the display command message of MIPI bus control unit.Display
Frame buffer is provided in panel 400 to store all pixel datas.When pixel data is stored in the frame buffer of display
In, timing controller can read data and be shown from frame buffer.MIPI bus control unit does not need that display is periodically flushed
Panel 400.
As shown in figure 4, within a frame period, display panel 400 only shows image information in low level, in high electricity
Image information is not shown usually.For example, when frame-synchronizing impulse TE low level is effective, under 2C/3C agreement, display panel 400
First frame image N is shown with the first refreshing frequency (such as 60Hz) within the first frame period, if the second frame image and first frame figure
As different, change (dynamic image), display panel 400 within the second frame period still with the first refreshing frequency (such as
60Hz) show the second frame image A.If third frame image is identical as the second frame image, the 4th frame image is identical as third frame image
(still image), then since third frame image, display panel third frame period and the 4th frame period are with the second refreshing frequency (example
Such as 30Hz) third frame image A, the 4th frame image A are shown respectively.If the 5th frame image is different from the 4th frame image, change,
Display panel 400 shows the 5th frame image B within the 5th frame period with the first refreshing frequency (such as 60Hz).
Display panel 400 first reads image data from random access memory ram, then between at regular intervals after according to institute
The image data information of reading carries out driving and shows, by being imaged on a display panel after a certain period of time.Therefore, RAM data is read
Extract operation, driving display operation DISPLAY, panel imaging operation PANEL successively postpone.
In the present embodiment, 2C/3C communication protocol includes: HDLC (High Level Data Link Control, high series
According to link control procedure) agreement, SDLC (Synchronous Data Link Control, synchronous data-link control) agreement
With RS-232-C agreement.
Display device disclosed in the present embodiment adjusts the refreshing frame per second of image data by clock generating circuit,
To reduce the power consumption of chip while the display effect that ensure that image data.
Fig. 5 shows the flow chart of clock signal generating method provided in an embodiment of the present invention.
As shown in figure 5, clock signal generating method disclosed in this invention includes:
In step s 110, content comparison is carried out to the image data of successive frame, and judges described image data for static state
Image or dynamic image.
When the content of the image data of progress successive frame compares, if judging result is still image, then follow the steps
S120；If judging result is dynamic image, S130 is thened follow the steps.Specific multilevel iudge method please refers to Fig. 2.
In the step s 120, when described image data are dynamic image, the first clock signal is generated.
In the present embodiment, when described image data are dynamic image, reference pulse signal is carried out by the first counter
It counts, and generates the first clock signal, the first clock signal control gate drive circuit and data drive circuit with the first brush
New frequency shows image.At this point, the second counter does not count reference pulse.
In step s 130, when described image data are still image, second clock signal is generated.
In the present embodiment, when described image data are still image, to reference pulse signal by the second counter
It is counted, and generates second clock signal, the second clock signal grid pole driving circuit and data drive circuit are with
Two refreshing frequencys show image.At this point, the first counter can suspend the counting to reference pulse, and when the second counter stops
When counting, the first counter continues to count from the counting position of pause.
Wherein, the frequency of the first clock signal is higher than the frequency of second clock signal and the first refreshing frequency is higher than second
Refreshing frequency.
In step S150, the refreshing frequency that image is shown is controlled according to the first clock signal or second clock signal.
It further include step S140 in a preferred embodiment.
In step S140, when described image data are when dynamic image and still image switch, generation third clock is believed
Number, wherein the frequency of third clock signal is located between the frequency of first clock signal and the frequency of second clock signal.
Clock signal generating method disclosed in the embodiment of the present invention still image and dynamic can occur in image data
When the switching of image, the refreshing frame per second of adjust automatically display panel is shown when still image with low frame per second driving display panel
Image shows image in dynamic image with original frame per second driving display panel, ensure that image display effect, reduce energy
Loss.
It should be noted that herein, contained the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
Finally, it should be noted that obviously, the above embodiment is merely an example for clearly illustrating the present invention, and simultaneously
The non-restriction to embodiment.For those of ordinary skill in the art, it can also do on the basis of the above description
Other various forms of variations or variation out.There is no necessity and possibility to exhaust all the enbodiments.And thus drawn
The obvious changes or variations that Shen goes out are still in the protection scope of this invention.
Claims (17)
1. a kind of clock generating circuit, comprising:
Data comparison module carries out content for the image data to successive frame and compares to judge whether it is still image or dynamic
Image；
Oscillator, for generating reference pulse signal；
First counter is used for when described image data are dynamic image, when counting the reference pulse to generate first
Clock signal；
Second counter is used for when described image data are still image, when counting the reference pulse to generate second
Clock signal,
Wherein, the frequency of first clock signal is higher than the frequency of the second clock signal, and electricity occurs for the clock signal
Road provides one of first clock signal and the second clock signal to control image display frame rate.
2. clock generating circuit according to claim 1, which is characterized in that when the picture data content of adjacent two frame
Identical and when maintaining N frame, described image data are still image, wherein N is the integer greater than 2.
3. clock generating circuit according to claim 1, which is characterized in that when the picture data content of adjacent two frame
Different or adjacent two field pictures data content is identical but when maintaining less than N frame, and described image data are dynamic image, wherein N is
Integer greater than 2.
4. clock generating circuit according to claim 1, which is characterized in that first counter and described second
Counter does not work at the same time.
5. clock generating circuit according to claim 4, which is characterized in that when second counter starts counting
When, the first counter pause counts；
When second counter stops counting, first counter continues to count from the counting position of pause.
6. clock generating circuit according to claim 1, which is characterized in that further include:
Third counter is used for when described image data are when dynamic image and still image switch, to the reference pulse meter
It counts to generate third clock signal,
Wherein, the frequency of third clock signal be located at first clock signal frequency and second clock signal frequency it
Between.
7. a kind of driving chip, which is characterized in that include clock of any of claims 1-6 on the driving chip
Signal generating circuit, the clock generating circuit provide the clock signal.
8. a kind of display device, comprising:
Display panel, the display panel include multiple grid lines, multiple data lines and multiple pixels, the multiple pixel difference
It is connected to the multiple grid line and is respectively connected to the multiple data line；
Gate driving circuit, the gate driving circuit have input terminal, and the input terminal receives clock signal and driving institute
State the driving voltage of multiple grid lines；And
Data drive circuit, the data drive circuit are configured to drive the multiple data line,
Wherein, the display device further includes driving chip according to claim 7, and the driving chip is for receiving figure
As signal and driving signal, Xiang Suoshu gate driving circuit provides the clock signal and provides to the data drive circuit
The driving voltage.
9. display device according to claim 8, which is characterized in that when second counter counts, the clock
Signal generating circuit sends control signal to the driving chip, controls the gate driving circuit and data drive circuit works
State.
10. display device according to claim 8, which is characterized in that when second counter counts, the grid
Driving circuit drives the display panel according to preset scanning mode.
11. display device according to claim 10, which is characterized in that the display panel include: liquid crystal display panel,
Organic light emitting display panel, field emission display panel, electric slurry display panel, electrophoretic display panel or Electrowetting display panel.
12. a kind of clock signal generating method characterized by comprising
Content comparison is carried out to the image data of successive frame, and judges described image data for still image or dynamic image；
When described image data are dynamic image, the first clock signal is generated；
When described image data are still image, second clock signal is generated,
The refreshing frequency shown according to the first clock signal or second clock signal control image；
Wherein, the frequency of first clock signal is higher than the frequency of the second clock signal.
13. clock signal generating method according to claim 12, which is characterized in that when in the image data of adjacent two frame
Hold identical and when maintaining N frame, described image data are still image, wherein N is the integer greater than 2.
14. clock signal generating method according to claim 12, which is characterized in that when in the image data of adjacent two frame
It is identical but when maintaining less than N frame to hold different or adjacent two field pictures data content, described image data are dynamic image, wherein N
For the integer greater than 2.
15. clock signal generating method according to claim 12, which is characterized in that by the first counter to the base
Quasi- pulse is counted to generate the first clock signal；
The reference pulse is counted by the second counter to generate second clock signal.
16. clock signal generating method according to claim 15, which is characterized in that when second counter starts to count
When number, the first counter pause is counted；
When second counter stops counting, first counter continues to count from the counting position of pause.
17. clock signal generating method according to claim 12, which is characterized in that further include:
When described image data are when dynamic image and still image switch, third clock signal is generated,
Wherein, the frequency of third clock signal be located at first clock signal frequency and second clock signal frequency it
Between.
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| CN201910330893.9A CN110085157A (en) | 2019-04-23 | 2019-04-23 | Clock generating circuit, driving chip, display device and clock signal generating method |
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| CN201910330893.9A CN110085157A (en) | 2019-04-23 | 2019-04-23 | Clock generating circuit, driving chip, display device and clock signal generating method |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111883038A (en) * | 2020-07-28 | 2020-11-03 | 惠科股份有限公司 | Method for determining gray-scale value of pixel, display panel and computer-readable storage medium |
| CN111883073A (en) * | 2020-07-22 | 2020-11-03 | 上海创功通讯技术有限公司 | Display method of electronic equipment and electronic equipment |
| CN113066430A (en) * | 2021-03-22 | 2021-07-02 | 硅谷数模(苏州)半导体有限公司 | Time schedule controller and display system |
| CN113299233A (en) * | 2020-02-21 | 2021-08-24 | 夏普株式会社 | Display control device, display control method, and recording medium |
| CN113870812A (en) * | 2021-10-15 | 2021-12-31 | Oppo广东移动通信有限公司 | Method and device for adjusting refresh frame rate of display screen, processor, chip and terminal |
| CN114420010A (en) * | 2021-12-30 | 2022-04-29 | 联想(北京)有限公司 | Control method and device and electronic equipment |
Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1155211A (en) * | 1995-12-12 | 1997-07-23 | 汤姆森消费电子有限公司 | Method for generating variable frequency synchronous signal, and apparatus thereof |
| CN1337669A (en) * | 2000-08-08 | 2002-02-27 | 株式会社半导体能源研究所 | Liquid crystal display apparatus and drive method thereof |
| US20070200843A1 (en) * | 2006-02-28 | 2007-08-30 | Jong-Kon Bae | Display driving integrated circuit and method of generating system clock signal using oscillator clock signal |
| US20080225062A1 (en) * | 2007-03-12 | 2008-09-18 | Au Optronics Corp. | Drive Circuit, Display Apparatus, and Method for Adjusting Screen Refresh Rate |
| CN101299316A (en) * | 2001-09-19 | 2008-11-05 | 日本电气株式会社 | Method for driving display, circuit board thereof and portable electronic apparatus |
| CN101908326A (en) * | 2010-02-09 | 2010-12-08 | 华映视讯（吴江）有限公司 | The driving method of display panel and display device |
| US20110205254A1 (en) * | 2010-02-19 | 2011-08-25 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device and electronic device |
| CN102542980A (en) * | 2010-12-22 | 2012-07-04 | 乐金显示有限公司 | Timing controller and organic light emitting diode display device using the same |
| CN102640207A (en) * | 2009-12-18 | 2012-08-15 | 株式会社半导体能源研究所 | Liquid crystal display device and driving method thereof |
| CN102930839A (en) * | 2011-08-08 | 2013-02-13 | 三星电子株式会社 | Display device and driving method thereof |
| US20130038639A1 (en) * | 2011-08-08 | 2013-02-14 | Young-su Han | Display device and a driving method thereof |
| CN104658495A (en) * | 2013-11-25 | 2015-05-27 | 乐金显示有限公司 | Display device and a method of driving the same |
| CN105047176A (en) * | 2015-09-21 | 2015-11-11 | 京东方科技集团股份有限公司 | Display panel, driving method thereof and display device |
| CN106504722A (en) * | 2017-01-12 | 2017-03-15 | 京东方科技集团股份有限公司 | A kind of GOA subregions driving method and device, GOA unit |
-
2019
- 2019-04-23 CN CN201910330893.9A patent/CN110085157A/en active Pending
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1155211A (en) * | 1995-12-12 | 1997-07-23 | 汤姆森消费电子有限公司 | Method for generating variable frequency synchronous signal, and apparatus thereof |
| CN1337669A (en) * | 2000-08-08 | 2002-02-27 | 株式会社半导体能源研究所 | Liquid crystal display apparatus and drive method thereof |
| CN101299316A (en) * | 2001-09-19 | 2008-11-05 | 日本电气株式会社 | Method for driving display, circuit board thereof and portable electronic apparatus |
| US20070200843A1 (en) * | 2006-02-28 | 2007-08-30 | Jong-Kon Bae | Display driving integrated circuit and method of generating system clock signal using oscillator clock signal |
| US20080225062A1 (en) * | 2007-03-12 | 2008-09-18 | Au Optronics Corp. | Drive Circuit, Display Apparatus, and Method for Adjusting Screen Refresh Rate |
| CN102640207A (en) * | 2009-12-18 | 2012-08-15 | 株式会社半导体能源研究所 | Liquid crystal display device and driving method thereof |
| CN101908326A (en) * | 2010-02-09 | 2010-12-08 | 华映视讯（吴江）有限公司 | The driving method of display panel and display device |
| US20110205254A1 (en) * | 2010-02-19 | 2011-08-25 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device and electronic device |
| CN102542980A (en) * | 2010-12-22 | 2012-07-04 | 乐金显示有限公司 | Timing controller and organic light emitting diode display device using the same |
| CN102930839A (en) * | 2011-08-08 | 2013-02-13 | 三星电子株式会社 | Display device and driving method thereof |
| US20130038639A1 (en) * | 2011-08-08 | 2013-02-14 | Young-su Han | Display device and a driving method thereof |
| CN104658495A (en) * | 2013-11-25 | 2015-05-27 | 乐金显示有限公司 | Display device and a method of driving the same |
| CN105047176A (en) * | 2015-09-21 | 2015-11-11 | 京东方科技集团股份有限公司 | Display panel, driving method thereof and display device |
| CN106504722A (en) * | 2017-01-12 | 2017-03-15 | 京东方科技集团股份有限公司 | A kind of GOA subregions driving method and device, GOA unit |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113299233A (en) * | 2020-02-21 | 2021-08-24 | 夏普株式会社 | Display control device, display control method, and recording medium |
| CN111883073A (en) * | 2020-07-22 | 2020-11-03 | 上海创功通讯技术有限公司 | Display method of electronic equipment and electronic equipment |
| CN111883073B (en) * | 2020-07-22 | 2022-02-25 | 上海创功通讯技术有限公司 | Display method of electronic equipment and electronic equipment |
| CN111883038A (en) * | 2020-07-28 | 2020-11-03 | 惠科股份有限公司 | Method for determining gray-scale value of pixel, display panel and computer-readable storage medium |
| US11380238B2 (en) | 2020-07-28 | 2022-07-05 | HKC Corporation Limited | Method for determining gray scale values of pixels, display panel and computer readable storage medium |
| CN113066430A (en) * | 2021-03-22 | 2021-07-02 | 硅谷数模(苏州)半导体有限公司 | Time schedule controller and display system |
| CN113870812A (en) * | 2021-10-15 | 2021-12-31 | Oppo广东移动通信有限公司 | Method and device for adjusting refresh frame rate of display screen, processor, chip and terminal |
| CN114420010A (en) * | 2021-12-30 | 2022-04-29 | 联想(北京)有限公司 | Control method and device and electronic equipment |
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