CN110069892B - FPGA pin allocation design method and device - Google Patents

FPGA pin allocation design method and device Download PDF

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CN110069892B
CN110069892B CN201910379084.7A CN201910379084A CN110069892B CN 110069892 B CN110069892 B CN 110069892B CN 201910379084 A CN201910379084 A CN 201910379084A CN 110069892 B CN110069892 B CN 110069892B
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pin
fpga
port
data structure
file
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CN110069892A (en
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赵鑫鑫
姜凯
李朋
于治楼
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Shandong Inspur Scientific Research Institute Co Ltd
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Shandong Inspur Scientific Research Institute Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
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  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

The invention provides a method and a device for designing FPGA pin allocation, wherein the method comprises the following steps: determining a top-level input/output port information file and a device available pin information file corresponding to the type of the FPGA; operating an FPGA pin graphic template database to generate a script to read the two files, so as to generate an FPGA pin graphic template database for distributing FPGA pins to a graphical interface; running FPGA pin allocation software with a graphical interface to design the FPGA pin allocation condition of a top-level input/output port in a file of the database and display the FPGA pin allocation condition with the graphical interface; and modifying the distribution condition according to the operation based on the external graphical interface and updating the distribution condition into the file of the database so as to complete the FPGA pin distribution design. The pin pre-allocation is automatically performed firstly, and then pin allocation adjustment is performed manually as required, so that the manual investment is greatly reduced, and the FPGA design efficiency can be improved by the scheme.

Description

FPGA pin allocation design method and device
Technical Field
The invention relates to the technical field of computers, in particular to a method and a device for designing FPGA pin allocation.
Background
At present, the electronic information technology industry develops rapidly, the performance requirement on a special chip is higher and higher, the complexity of an integrated circuit is exponentially increased while the integrated circuit technology advances rapidly, the research and development production period is greatly prolonged, and the method cannot well adapt to changeable market demands. FPGA (Field-Programmable Gate Array, field programmable gate array) provides a method that can flexibly implement circuits, balancing the contradiction between product development cycle and product performance. However, since many functions are integrated into one FPGA, the number of pins of the FPGA is huge.
At present, in the design process of the FPGA engineering codes, as the placement positions of the input and output ports are related to each other, different ports have different level requirements, and the FPGA pins have various types to meet the different port requirements, the port pin allocation files need to be written manually and fully, so when modifying the front-end design codes, laying out and wiring, adjusting the input and output ports and the like, workers need to modify the FPGA pin allocation files for a plurality of times.
Therefore, the FPGA pin allocation design process is tedious, repeated and frequent, a large amount of time is wasted, and the FPGA design efficiency is low.
Disclosure of Invention
The invention provides a method and a device for distributing and designing FPGA pins, which can improve the design efficiency of the FPGA.
In order to achieve the above purpose, the invention is realized by the following technical scheme:
in one aspect, the present invention provides a method for designing pin assignment of an FPGA, including:
s1: determining a top-level input/output port information file and a device available pin information file corresponding to the type of the FPGA;
s2: operating a pre-written FPGA pin graphic template database to generate a script so as to read the information file of the input/output port of the top layer of the design and the information file of the available pins of the device, thereby generating an FPGA pin graphic template database for distributing FPGA pins to a graphical interface;
s3: running pre-written FPGA pin allocation software with a graphical interface to design the pin allocation condition of a top-level input/output port FPGA in a file of an FPGA pin graphical template database and display the pin allocation condition with the graphical interface;
s4: modifying the pin allocation condition of the FPGA of the input/output port of the top layer according to the operation based on the graphical interface;
s5: updating the modified FPGA pin allocation condition of the top-level input/output port of the design into a file of the FPGA pin graphic template database to complete the FPGA pin allocation design.
Further, the designing the file content of the top-level input/output port information file includes: any one or more of port group name, port group type, port group level, whether port group allows separation, port name, port additional level;
the file content of the pin information file available for the device comprises: pin BANK number, BANK inner pin type, pin description information, pin number.
Further, the step S2 includes: running a pre-written FPGA pin graphic template database to generate a script so as to execute the following operations:
searching the file content of the information file of the input/output port of the design top layer, thereby establishing a primary data structure by taking the port group as a unit, and establishing a secondary data structure by taking the port as a unit, wherein any primary data structure comprises at least one secondary data structure, any primary data structure stores the information of the port group, and any secondary data structure stores the information of the port;
searching file content of the device available pin information file, thereby establishing a primary data structure by taking a BANK as a unit, and establishing a secondary data structure by taking a device available pin as a unit, wherein any one of the primary data structures comprises at least one secondary data structure, any one of the primary data structures stores information of the BANK, and any one of the secondary data structures stores information of a device available pin;
Sorting the port groups by searching the established data structure;
according to the port group sequencing result, sequentially searching pins meeting the demands of each port, pre-distributing the pins of each port in each port group, and correspondingly storing the pin distribution condition of each port in a secondary data structure of each port;
and printing and outputting the data in the obtained data structure according to the format requirement of the FPGA pin allocation software on the graphic template database so as to generate an FPGA pin graphic template database for allocating the FPGA pins to the graphic interface.
Further, the retrieving the file content of the pin information file available to the device includes: and retrieving file contents of the pin information file available for the device by using the regular expression.
Further, the sorting the port group by searching the established data structure includes: according to a preset port group ordering rule, ordering the port groups by searching the established data structure so that the priority of the port group ordered in front is not less than that of the port group ordered in back;
correspondingly, the sequentially retrieving pins meeting the requirements of each port comprises the following steps: pins meeting the requirements of all ports are sequentially searched according to the sequence of priority from high to low and BANK numbers from low to high.
Further, the printing output of the data in the data structure to be obtained comprises: and printing out the data in the obtained data structure by using the printf function.
Further, after the completing the FPGA pin assignment design, further includes: and generating a constraint file of XDC for VIVADO or UCF for ISE according to the file of the FPGA pin graphic template database.
In another aspect, the present invention provides an FPGA pin assignment design apparatus, including:
the determining unit is used for determining a top-level input/output port information file and a device available pin information file corresponding to the model of the used FPGA;
the running unit is used for running a pre-written FPGA pin graphic template database to generate a script so as to read the information file of the input/output port of the top design layer and the information file of the available pins of the device, thereby generating an FPGA pin graphic template database for distributing FPGA pins to a graphic interface;
the processing unit is used for running pre-written FPGA pin allocation software with a graphical interface so as to design the FPGA pin allocation situation of the top-level input/output port in the file of the FPGA pin graphical template database and display the FPGA pin allocation situation by the graphical interface; modifying the pin allocation condition of the FPGA of the input/output port of the top layer according to the operation based on the graphical interface; updating the modified FPGA pin allocation condition of the top-level input/output port of the design into a file of the FPGA pin graphic template database to complete the FPGA pin allocation design.
Further, the designing the file content of the top-level input/output port information file includes: any one or more of port group name, port group type, port group level, whether port group allows separation, port name, port additional level;
the file content of the pin information file available for the device comprises: pin BANK number, BANK inner pin type, pin description information, pin number.
Further, the operation unit is configured to operate a pre-written FPGA pin graphic template database to generate a script, so as to perform the following operations: searching the file content of the information file of the input/output port of the design top layer, thereby establishing a primary data structure by taking the port group as a unit, and establishing a secondary data structure by taking the port as a unit, wherein any primary data structure comprises at least one secondary data structure, any primary data structure stores the information of the port group, and any secondary data structure stores the information of the port; searching file content of the device available pin information file, thereby establishing a primary data structure by taking a BANK as a unit, and establishing a secondary data structure by taking a device available pin as a unit, wherein any one of the primary data structures comprises at least one secondary data structure, any one of the primary data structures stores information of the BANK, and any one of the secondary data structures stores information of a device available pin; sorting the port groups by searching the established data structure; according to the port group sequencing result, sequentially searching pins meeting the demands of each port, pre-distributing the pins of each port in each port group, and correspondingly storing the pin distribution condition of each port in a secondary data structure of each port; and printing and outputting the data in the obtained data structure according to the format requirement of the FPGA pin allocation software on the graphic template database so as to generate an FPGA pin graphic template database for allocating the FPGA pins to the graphic interface.
Further, the running unit is used for retrieving file contents of the pin information file available for the device by using the regular expression.
Further, the operation unit is configured to sort the port groups by searching the established data structure according to a preset port group sorting rule, so that the priority of the port group sorted in front is not less than the priority of the port group sorted in back; pins meeting the requirements of all ports are sequentially searched according to the sequence of priority from high to low and BANK numbers from low to high.
Further, the running unit is configured to print out the data in the obtained data structure by using a printf function.
Further, the FPGA pin assignment design apparatus further includes: and the generating unit is used for generating a constraint file of XDC (XDC) for VIVADO or UCF (UCF) for ISE (open channel language) according to the file of the FPGA pin graphic template database.
The invention provides a method and a device for designing FPGA pin allocation, wherein the method comprises the following steps: determining a top-level input/output port information file and a device available pin information file corresponding to the type of the FPGA; operating an FPGA pin graphic template database to generate a script to read the two files, so as to generate an FPGA pin graphic template database for distributing FPGA pins to a graphical interface; running FPGA pin allocation software with a graphical interface to design the FPGA pin allocation condition of a top-level input/output port in a file of the database and display the FPGA pin allocation condition with the graphical interface; and modifying the distribution condition according to the operation based on the external graphical interface and updating the distribution condition into the file of the database so as to complete the FPGA pin distribution design. The pin pre-allocation is automatically performed firstly, and then the pin allocation adjustment is performed manually as required, so that the manual investment is greatly reduced, and the FPGA design efficiency can be improved.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for designing FPGA pin assignment according to an embodiment of the present invention;
FIG. 2 is a flow chart of another design method for FPGA pin assignment according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a graphical interface provided by an embodiment of the present invention;
FIG. 4 is a schematic diagram of another graphical interface provided by an embodiment of the present invention;
FIG. 5 is a schematic diagram of an FPGA pin assignment design apparatus according to an embodiment of the present invention;
fig. 6 is a schematic diagram of another FPGA pin assignment design apparatus according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments, and all other embodiments obtained by those skilled in the art without making any inventive effort based on the embodiments of the present invention are within the scope of protection of the present invention.
As shown in fig. 1, the embodiment of the invention provides a method for designing pin allocation of an FPGA, which may include the following steps:
step 101: determining a design top-level input-output port information file and determining a device available pin information file corresponding to a model of the FPGA used.
Step 102: and running a pre-written FPGA pin graphic template database to generate a script so as to read the information file of the input/output port of the top layer of the design and the information file of the available pins of the device, thereby generating the FPGA pin graphic template database for distributing the FPGA pins to the graphical interface.
Step 103: and running pre-written FPGA pin allocation software with a graphical interface to design the pin allocation condition of the top-level input/output port FPGA in the file of the FPGA pin graphical template database and display the pin allocation condition with the graphical interface.
Step 104: and modifying the pin allocation condition of the FPGA of the input/output port of the top layer of the design according to the operation based on the graphical interface.
Step 105: updating the modified FPGA pin allocation condition of the top-level input/output port of the design into a file of the FPGA pin graphic template database to complete the FPGA pin allocation design.
The embodiment of the invention provides a design method for FPGA pin allocation, which comprises the following steps: determining a top-level input/output port information file and a device available pin information file corresponding to the type of the FPGA; operating an FPGA pin graphic template database to generate a script to read the two files, so as to generate an FPGA pin graphic template database for distributing FPGA pins to a graphical interface; running FPGA pin allocation software with a graphical interface to design the FPGA pin allocation condition of a top-level input/output port in a file of the database and display the FPGA pin allocation condition with the graphical interface; and modifying the distribution condition according to the operation based on the external graphical interface and updating the distribution condition into the file of the database so as to complete the FPGA pin distribution design. The pin pre-allocation is automatically performed firstly, and then the pin allocation adjustment is performed manually according to the requirement, so that the manual investment is greatly reduced, and the FPGA design efficiency can be improved.
In detail, the pin assignment, i.e. the assignment between a plurality of input/output ports and a plurality of FPGA pins, is performed, and thus, referring to step 101, the port information and the pin information need to be predetermined.
For example, in one embodiment of the present invention, the file content of the top-level input/output port information file includes: any one or more of port group name, port group type, port group level, whether port group allows separation, port name, port attachment level.
For example, in one embodiment of the present invention, the file content of the device available pin information file includes: pin BANK number, BANK inner pin type, pin description information, pin number.
In detail, xilinx is a vendor of programmable logic complete solutions. In one embodiment of the present invention, when this pin assignment design method is applied to the project using the Xilinx FPGA design, in order to illustrate a possible implementation manner of determining the device available pin information file, the determining the device available pin information file corresponding to the model of the FPGA used in step 101 includes: according to the model of the FPGA, acquiring package and pin (Packaging and Pinouts) information corresponding to the model from an Xilinx device use document, and establishing a device usable pin information file according to the acquired package and pin information.
Referring to step 102, a script is generated by pre-writing the FPGA pin graphic template database, and the FPGA pin graphic template database for distributing FPGA pins to the graphical interface can be generated by using the script.
In detail, the script file may be implemented using tcl (Tool Command Language ), python, etc. In detail, python is a computer programming language.
In one embodiment of the present invention, to illustrate one possible implementation of running a script to generate a database, the step 102 includes: running a pre-written FPGA pin graphic template database to generate a script so as to execute the following operations:
searching the file content of the information file of the input/output port of the design top layer, thereby establishing a primary data structure by taking the port group as a unit, and establishing a secondary data structure by taking the port as a unit, wherein any primary data structure comprises at least one secondary data structure, any primary data structure stores the information of the port group, and any secondary data structure stores the information of the port;
searching file content of the device available pin information file, thereby establishing a primary data structure by taking a BANK as a unit, and establishing a secondary data structure by taking a device available pin as a unit, wherein any one of the primary data structures comprises at least one secondary data structure, any one of the primary data structures stores information of the BANK, and any one of the secondary data structures stores information of a device available pin;
sorting the port groups by searching the established data structure;
According to the port group sequencing result, sequentially searching pins meeting the demands of each port, pre-distributing the pins of each port in each port group, and correspondingly storing the pin distribution condition of each port in a secondary data structure of each port;
and printing and outputting the data in the obtained data structure according to the format requirement of the FPGA pin allocation software on the graphic template database so as to generate an FPGA pin graphic template database for allocating the FPGA pins to the graphic interface.
In detail, the information of the port group may include a name of the port group, a port group type, a port group level, whether the port group allows separation, and the like.
In detail, the information of the port may include a name of the port, an additional level of the port, and the like.
In detail, the information of the BANK may include a pin BANK number, a BANK in-pin type, and the like. Such as the BANK inner pin type, whether the HP type, HR type, or GTH type.
In detail, the information of the device available pins may include pin description information, pin numbers, and the like.
In detail, by generating this FPGA pin graphic template database, automated pin pre-allocation is equivalent to completion. In the embodiment of the invention, automatic pin pre-allocation is firstly performed according to the preset allocation rule, and then the pre-allocation result can be displayed to a user through a graphical interface, so that the user can manually adjust the pin allocation according to the requirement. Please refer to fig. 2, which is an example of a graphical interface. This instance may be either a pre-assigned instance or an instance that has been adjusted by the user at any time.
Referring to fig. 2, the interface example shown in fig. 2 shows the current pin assignment from the top layer. In fig. 2, several button blocks for BANK are shown, and each button block displays the type of BANK, for example, HP, HR, GTH; the numbers at the back of the type are the numbers of BANK; in the first bracket at the back, the number before "/" is the pin number used by BANK, and the number after "/" is the total pin number of BANK; the number in the second bracket at the back is the number of pins the user expects to place in the remaining outstanding assignments of the BANK.
For example, a total pin count of a BANK is 30, but a user expects 40 pins to be placed in the BANK, so that when 30 of them are successfully placed in the BANK and another 10 are not successfully placed in the BANK, the number in the second bracket of the button block is 10.
When any button block for the BANK is clicked, the next graphical interface can be accessed to display each pin under the BANK, for example, the content shown in fig. 3 can be the next graphical interface. .
In fig. 2, there are a remaining button block and a completion allocation button block at the lowermost side. The numbers displayed on the rest button blocks are the number of all unassigned pins, and clicking on the button blocks can display the detailed name information of all unassigned pins in the next graphical interface. After the allocation is completed, the user may click on the complete allocation button block, thereby automatically producing the constraint file.
Referring to FIG. 3, the numbers after bytes can be the numbers of the bytes in the BANK. The numbers in the circles are the numbers of the pins within the bytes, and the numbers in the rectangular boxes after the circles are the pin names. Each circle corresponds to a port, so if the port is not currently allocated with a pin, the following rectangular frame is empty.
At the middle area of fig. 3 is shown pin information of remaining unassigned pins that the user desires to put in the BANK. The pin count shown here is consistent with the number in brackets of the second of the button blocks of the BANK.
The remaining IO number, i.e., the total remaining pin count, is shown in the lower region of FIG. 3, and may be the sum of the remaining unassigned pin counts in all other BANK's. Clicking on the button may also display all unassigned pin information in the upper region.
Referring to fig. 3, when a user needs to manually adjust pin assignment, a button block of an IO pin assigned above may be clicked and dragged to a lower unassigned region, or a button block of any IO pin in the lower unassigned region may be clicked and dragged to a rectangular frame above to complete pin assignment.
Based on the foregoing, in the embodiment of the present invention, further, when pin pre-allocation is performed, if there is an input/output port for which pin allocation cannot be completed according to a predetermined policy, pin allocation may be abandoned for the input/output port. For example, referring to fig. 3, if an input/output port does not perform pin assignment, the rectangular frame on the right side of the circle corresponding to the port is empty. Therefore, the user can manually allocate pins to the port as required, for example, a button block of a pin in the middle area of fig. 3 can be dragged into a rectangular frame on the right side of the circle corresponding to the port, so as to manually establish a matching relationship between the two.
In detail, when the script is run, information retrieval can be performed by using a regular expression, pin pre-allocation can be performed by using priority ordering, and result printing can be performed by using a printf function.
Thus, based on the foregoing, in one embodiment of the present invention, the retrieving file content of the pin information file available to the device includes: and retrieving file contents of the pin information file available for the device by using the regular expression.
Based on the foregoing, in one embodiment of the present invention, the sorting the port group by searching the established data structure includes: according to a preset port group ordering rule, ordering the port groups by searching the established data structure so that the priority of the port group ordered in front is not less than that of the port group ordered in back;
correspondingly, the sequentially retrieving pins meeting the requirements of each port comprises the following steps: pins meeting the requirements of all ports are sequentially searched according to the sequence of priority from high to low and BANK numbers from low to high.
For example, the priority may be required that the port group does not allow separation to be highest, and the remaining port groups may be ordered according to the desired pin BANK type, e.g., the HP type pin has a higher priority than the HR type pin.
Based on the foregoing, in one embodiment of the present invention, the printing out of the data in the data structure to be obtained includes: and printing out the data in the obtained data structure by using the printf function.
Referring to step 103, FPGA pin assignment software needs to be pre-written. The software can be used for displaying the distribution condition of the FPGA pins of the input/output port on the top layer in the FPGA pin graphic template database file in a graphic interface. In this manner, the user may operate the image interface to modify pin assignments as desired.
In detail, the software may be written using Visual Basic language.
Referring to step 104, after displaying the pin assignment in the graphical interface, the user performs assignment adjustment by observing the pre-assignment condition of the existing pins and using the graphical interface as required to complete the design of the pin assignment of the top-level input/output port. Of course, referring to step 105 above, the modified pin assignment information may be automatically updated to the FPGA pin graphic template database file.
In detail, before the final file generation, the user can freely adjust the position of each FPGA pin to realize optimal FPGA pin allocation.
After pin assignment is completed, XDC for VIVADO software or UCF constraint files for ISE can be generated as needed. Thus, in one embodiment of the present invention, after said step 105, further comprising: and generating a constraint file of XDC for VIVADO or UCF for ISE according to the file of the FPGA pin graphic template database.
Based on the generated constraint file, the actual operation of FPGA pin allocation can be performed in the corresponding integrated environment.
In detail, the VIVADO software is an integrated design environment issued by an FPGA vendor, for which XDC (Xilinx Design Constraints) is a constraint file.
In detail, ISE (Integrated Software Environment ) is a hardware design tool of Xilinx corporation, for which UCF is a constraint file.
Based on the foregoing, an embodiment of the present invention may automatically generate an XDC for the VIVADO software or a UCF constraint file for the ISE by using an automation script and a graphical interface software according to a design top-level input-output port information file and a device available pin information file. When the design modification front-end design codes, port level standards, port names, port numbers and the like are designed, so that the port pin allocation file needs to be modified, the automation script is only required to be called again, FPGA pin allocation is performed by using the graphical interface software, and a new port pin allocation file is generated. Therefore, the efficiency of FPGA design is greatly improved, and project progress is quickened.
In summary, the design of the FPGA pin allocation based on the graphical interface provided by the embodiment of the invention can be suitable for projects using the Xilinx FPGA design, can realize automatic pre-allocation of pins, adjusts pin allocation based on the graphical interface, automatically completes pin allocation constraint file generation, improves the automation level of the FPGA design, reduces errors caused by manual operation, and accelerates project development progress.
As shown in fig. 4, an embodiment of the present invention provides another design method for pin assignment of FPGA, taking an example of an item applied to design using Xilinx FPGA, specifically including the following steps:
step 401: and writing an FPGA pin graphic template database to generate a script by using a Python language.
Step 402: and (3) compiling FPGA pin allocation software with a graphical interface by using Visual Basic language.
Step 403: and determining a top-level input/output port information file.
In the embodiment of the invention, the file content of the file comprises: port group name, port group type, port group level, whether port groups allow separation, port name, port attachment level.
Step 404: according to the model of the FPGA, acquiring package and pin information corresponding to the model from an Xilinx device use document, and establishing a device usable pin information file according to the acquired package and pin information.
In the embodiment of the invention, the file content of the file comprises: pin BANK number, BANK inner pin type, pin description information, pin number.
Step 405: the FPGA pin graphics template database generation script is run to perform steps 406 through 410.
Step 406: and searching the file content of the information file of the input/output port of the design top layer, thereby establishing a primary data structure by taking the port group as a unit, and establishing a secondary data structure by taking the port as a unit, wherein any one of the primary data structures comprises at least one secondary data structure, any one of the primary data structures stores the information of the port group, and any one of the secondary data structures stores the information of the port.
Step 407: and searching file contents of the device available pin information file by using a regular expression, thereby establishing a primary data structure by taking the BANK as a unit, and establishing a secondary data structure by taking the device available pin as a unit, wherein any one of the primary data structures comprises at least one secondary data structure, any one of the primary data structures stores information of a BANK, and any one of the secondary data structures stores information of a device available pin.
Step 408: and according to a preset port group ordering rule, ordering the port groups by searching the established data structure, so that the priority of the port group ordered in front is not less than that of the port group ordered in back.
Step 409: according to the port group sequencing result, sequentially retrieving pins meeting the requirements of each port according to the order of priority from high to low and BANK numbers from low to high, performing pin pre-allocation on each port in each port group, and correspondingly storing the pin allocation condition of each port in a secondary data structure of each port.
Step 410: and printing and outputting the data in the obtained data structure by using a printf function according to the format requirement of FPGA pin allocation software on the graphic template database so as to generate an FPGA pin graphic template database for allocating FPGA pins to the graphic interface.
Step 411: and running FPGA pin distribution software with a graphical interface to design the FPGA pin distribution condition of the top-level input/output port in a file of an FPGA pin graphical template database and display the FPGA pin distribution condition with the graphical interface.
Step 412: and modifying and designing the pin allocation condition of the top-level input/output port FPGA according to the operation based on the graphical interface.
Step 413: and updating the modified FPGA pin allocation condition of the input/output port of the top layer of the design into a file of an FPGA pin graphic template database to finish the FPGA pin allocation design.
Step 414: and generating the constraint file of the XDC for the VIVADO according to the file of the FPGA pin graphic template database.
The FPGA pin allocation design method provided by the embodiment of the invention is convenient to implement, simple in flow, efficient and stable, and can greatly shorten the time of manually writing port pin allocation files and improve the FPGA design efficiency. Of course, because the manual operation is greatly reduced, the error easily caused by the manual operation is correspondingly reduced.
As shown in fig. 5, an embodiment of the present invention provides an FPGA pin assignment design apparatus, which may include:
a determining unit 501, configured to determine a top-level input/output port information file, and determine a device available pin information file corresponding to a model of the FPGA used;
the operation unit 502 is configured to operate a pre-written FPGA pin graphic template database to generate a script, so as to read the information file of the input/output port of the design top layer and the information file of the available pins of the device, thereby generating an FPGA pin graphic template database for distributing FPGA pins to a graphical interface;
the processing unit 503 is configured to run pre-written FPGA pin allocation software with a graphical interface, so as to display the pin allocation situation of the top-level input/output port FPGA in the file of the FPGA pin graphic template database with the graphical interface; modifying the pin allocation condition of the FPGA of the input/output port of the top layer according to the operation based on the graphical interface; updating the modified FPGA pin allocation condition of the top-level input/output port of the design into a file of the FPGA pin graphic template database to complete the FPGA pin allocation design.
In one embodiment of the present invention, the designing the file content of the top-level input/output port information file includes: any one or more of port group name, port group type, port group level, whether port group allows separation, port name, port additional level;
the file content of the pin information file available for the device comprises: pin BANK number, BANK inner pin type, pin description information, pin number.
In one embodiment of the present invention, the running unit 502 is configured to run a pre-written FPGA pin graphic template database to generate a script, so as to perform the following operations: searching the file content of the information file of the input/output port of the design top layer, thereby establishing a primary data structure by taking the port group as a unit, and establishing a secondary data structure by taking the port as a unit, wherein any primary data structure comprises at least one secondary data structure, any primary data structure stores the information of the port group, and any secondary data structure stores the information of the port; searching file content of the device available pin information file, thereby establishing a primary data structure by taking a BANK as a unit, and establishing a secondary data structure by taking a device available pin as a unit, wherein any one of the primary data structures comprises at least one secondary data structure, any one of the primary data structures stores information of the BANK, and any one of the secondary data structures stores information of a device available pin; sorting the port groups by searching the established data structure; according to the port group sequencing result, sequentially searching pins meeting the demands of each port, pre-distributing the pins of each port in each port group, and correspondingly storing the pin distribution condition of each port in a secondary data structure of each port; and printing and outputting the data in the obtained data structure according to the format requirement of the FPGA pin allocation software on the graphic template database so as to generate an FPGA pin graphic template database for allocating the FPGA pins to the graphic interface.
In one embodiment of the present invention, the running unit 502 is configured to use a regular expression to retrieve file contents of the pin information file available for the device.
In one embodiment of the present invention, the operation unit 502 is configured to sort the port groups by searching the established data structure according to a preset port group sorting rule, so that the priority of the port group sorted before is not less than the priority of the port group sorted after; pins meeting the requirements of all ports are sequentially searched according to the sequence of priority from high to low and BANK numbers from low to high.
In one embodiment of the present invention, the running unit 502 is configured to print out the data in the obtained data structure using a printf function.
In one embodiment of the present invention, referring to fig. 6, the FPGA pin assignment design apparatus may further include: and the generating unit 601 is configured to generate a constraint file, such as XDC for VIVADO or UCF for ISE, according to the file of the FPGA pin graphic template database.
The content of information interaction and execution process between the units in the device is based on the same conception as the embodiment of the method of the present invention, and specific content can be referred to the description in the embodiment of the method of the present invention, which is not repeated here.
In summary, the embodiments of the present invention have at least the following advantages:
1. in the embodiment of the invention, a top-layer input/output port information file and a device available pin information file corresponding to the model of the used FPGA are determined; operating an FPGA pin graphic template database to generate a script to read the two files, so as to generate an FPGA pin graphic template database for distributing FPGA pins to a graphical interface; running FPGA pin allocation software with a graphical interface to design the FPGA pin allocation condition of a top-level input/output port in a file of the database and display the FPGA pin allocation condition with the graphical interface; and modifying the distribution condition according to the operation based on the external graphical interface and updating the distribution condition into the file of the database so as to complete the FPGA pin distribution design. The pin pre-allocation is automatically performed firstly, and then the pin allocation adjustment is performed manually according to the requirement, so that the manual investment is greatly reduced, and the FPGA design efficiency can be improved.
2. An embodiment of the present invention may automatically generate an XDC for VIVADO software or a UCF constraint file for ISE by using an automation script and graphical interface software according to a design top-level input-output port information file and a device available pin information file. When the design modification front-end design codes, port level standards, port names, port numbers and the like are designed, so that the port pin allocation file needs to be modified, the automation script is only required to be called again, FPGA pin allocation is performed by using the graphical interface software, and a new port pin allocation file is generated. Therefore, the efficiency of FPGA design is greatly improved, and project progress is quickened.
3. The FPGA pin allocation design based on the graphical interface provided by the embodiment of the invention can be suitable for projects using the Xilinx FPGA design, can realize automatic pre-allocation of pins, adjusts pin allocation based on the graphical interface, automatically completes pin allocation constraint file generation, improves the automation level of the FPGA design, reduces errors caused by manual operation, and accelerates project development progress.
4. The FPGA pin allocation design method provided by the embodiment of the invention is convenient to implement, simple in flow, efficient and stable, and can greatly shorten the time of manually writing port pin allocation files and improve the FPGA design efficiency. Of course, because the manual operation is greatly reduced, the error easily caused by the manual operation is correspondingly reduced.
It is noted that relational terms such as first and second, and the like, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the statement "comprises one" does not exclude that an additional identical element is present in a process, method, article or apparatus that comprises the element.
Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the above method embodiments may be implemented by hardware related to program instructions, and the foregoing program may be stored in a computer readable storage medium, where the program, when executed, performs steps including the above method embodiments; and the aforementioned storage medium includes: various media in which program code may be stored, such as ROM, RAM, magnetic or optical disks.
Finally, it should be noted that: the foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims (2)

1. The FPGA pin allocation design method for the field programmable gate array is characterized by comprising the following steps of:
s1: determining a top-level input/output port information file and a device available pin information file corresponding to the type of the FPGA;
s2: operating a pre-written FPGA pin graphic template database to generate a script so as to read the information file of the input/output port of the top layer of the design and the information file of the available pins of the device, thereby generating an FPGA pin graphic template database for distributing FPGA pins to a graphical interface;
S3: running pre-written FPGA pin allocation software with a graphical interface to design the pin allocation condition of a top-level input/output port FPGA in a file of an FPGA pin graphical template database and display the pin allocation condition with the graphical interface;
s4: modifying the pin allocation condition of the FPGA of the input/output port of the top layer according to the operation based on the graphical interface;
s5: updating the modified FPGA pin allocation condition of the top-level input/output port of the design into a file of the FPGA pin graphic template database to complete the FPGA pin allocation design;
the file content of the information file of the top-level input/output port is designed, which comprises the following steps: any one or more of port group name, port group type, port group level, whether port group allows separation, port name, port additional level;
the file content of the pin information file available for the device comprises: any one or more of pin BANK number, BANK inner pin type, pin description information and pin number;
the step S2 comprises the following steps: running a pre-written FPGA pin graphic template database to generate a script so as to execute the following operations:
Searching the file content of the information file of the input/output port of the design top layer, thereby establishing a primary data structure by taking the port group as a unit, and establishing a secondary data structure by taking the port as a unit, wherein any primary data structure comprises at least one secondary data structure, any primary data structure stores the information of the port group, and any secondary data structure stores the information of the port;
searching file content of the device available pin information file, thereby establishing a primary data structure by taking a BANK as a unit, and establishing a secondary data structure by taking a device available pin as a unit, wherein any one of the primary data structures comprises at least one secondary data structure, any one of the primary data structures stores information of the BANK, and any one of the secondary data structures stores information of a device available pin;
sorting the port groups by searching the established data structure;
according to the port group sequencing result, sequentially searching pins meeting the demands of each port, pre-distributing the pins of each port in each port group, and correspondingly storing the pin distribution condition of each port in a secondary data structure of each port;
Printing and outputting the data in the obtained data structure according to the format requirement of the FPGA pin allocation software on the graphic template database so as to generate an FPGA pin graphic template database for allocating the FPGA pins to the graphic interface;
the retrieving file content of the pin information file available for the device includes: retrieving file contents of the pin information file available for the device by using a regular expression;
and/or the number of the groups of groups,
the sorting the port group by searching the established data structure includes: according to a preset port group ordering rule, ordering the port groups by searching the established data structure so that the priority of the port group ordered in front is not less than that of the port group ordered in back;
correspondingly, the sequentially retrieving pins meeting the requirements of each port comprises the following steps: sequentially retrieving pins meeting the requirements of all ports according to the sequence of priority from high to low and BANK numbers from low to high;
and/or the number of the groups of groups,
the printing and outputting of the data in the obtained data structure comprises the following steps: printing and outputting the data in the obtained data structure by using a printf function;
after the FPGA pin assignment design is completed, further comprising:
And generating a constraint file of XDC for VIVADO or UCF for ISE according to the file of the FPGA pin graphic template database.
2. A field programmable gate array FPGA pin assignment design apparatus, comprising:
the determining unit is used for determining a top-level input/output port information file and a device available pin information file corresponding to the model of the used FPGA;
the running unit is used for running a pre-written FPGA pin graphic template database to generate a script so as to read the information file of the input/output port of the top design layer and the information file of the available pins of the device, thereby generating an FPGA pin graphic template database for distributing FPGA pins to a graphic interface;
the processing unit is used for running pre-written FPGA pin allocation software with a graphical interface so as to design the FPGA pin allocation situation of the top-level input/output port in the file of the FPGA pin graphical template database and display the FPGA pin allocation situation by the graphical interface; modifying the pin allocation condition of the FPGA of the input/output port of the top layer according to the operation based on the graphical interface; updating the modified FPGA pin allocation condition of the top-level input/output port of the design into a file of the FPGA pin graphic template database to complete the FPGA pin allocation design;
The file content of the information file of the top-level input/output port is designed, which comprises the following steps: any one or more of port group name, port group type, port group level, whether port group allows separation, port name, port additional level;
the file content of the pin information file available for the device comprises: any one or more of pin BANK number, BANK inner pin type, pin description information and pin number;
the operation unit is used for operating a pre-written FPGA pin graphic template database to generate a script so as to execute the following operations: searching the file content of the information file of the input/output port of the design top layer, thereby establishing a primary data structure by taking the port group as a unit, and establishing a secondary data structure by taking the port as a unit, wherein any primary data structure comprises at least one secondary data structure, any primary data structure stores the information of the port group, and any secondary data structure stores the information of the port; searching file content of the device available pin information file, thereby establishing a primary data structure by taking a BANK as a unit, and establishing a secondary data structure by taking a device available pin as a unit, wherein any one of the primary data structures comprises at least one secondary data structure, any one of the primary data structures stores information of the BANK, and any one of the secondary data structures stores information of a device available pin; sorting the port groups by searching the established data structure; according to the port group sequencing result, sequentially searching pins meeting the demands of each port, pre-distributing the pins of each port in each port group, and correspondingly storing the pin distribution condition of each port in a secondary data structure of each port; printing and outputting the data in the obtained data structure according to the format requirement of the FPGA pin allocation software on the graphic template database so as to generate an FPGA pin graphic template database for allocating the FPGA pins to the graphic interface;
The operation unit is used for searching file contents of the pin information files available for the device by using the regular expression;
and/or the number of the groups of groups,
the operation unit is used for sorting the port groups by searching the established data structure according to a preset port group sorting rule so that the priority of the port group sorted in front is not less than that of the port group sorted in back; sequentially retrieving pins meeting the requirements of all ports according to the sequence of priority from high to low and BANK numbers from low to high;
and/or the number of the groups of groups,
the operation unit is used for printing and outputting the data in the obtained data structure by using the printf function;
further comprises: and the generating unit is used for generating a constraint file of XDC (XDC) for VIVADO or UCF (UCF) for ISE (open channel language) according to the file of the FPGA pin graphic template database.
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