CN110046695A - A kind of configurable high degree of parallelism spiking neuron array - Google Patents
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Abstract
The invention discloses a kind of configurable high degree of parallelism spiking neuron arrays, comprising: the array and multiple alternative selectors that multiple row is constituted by can configure base unit；Wherein: each column is sequentially connected by can configure the configurable base unit in the array that base unit is constituted；Configurable base unit between adjacent two column staggers successively one and is connected by the alternative selector.The present invention can support to be adapted to a variety of input port number neurons, while can be improved the degree of parallelism of pulse convolutional neural networks processing.
Description
Technical field
The present invention relates to Design of Digital Circuit technical field more particularly to a kind of configurable high degree of parallelism spiking neurons
Array.
Background technique
With the development of artificial intelligence, more and more applications start to introduce artificial intelligence to further improve performance.Mind
Through the important branch that network is in artificial intelligence, there is important application in image recognition and feature extraction.In image recognition
In, neural network is there are two important branch, another then be more to meet biologically nerve net one is convolutional neural networks
The impulsive neural networks of network.The it is proposed of convolutional neural networks is in eighties of last century, but since calculation power at that time is insufficient, and could not
Developed well, but since the 21th century, the development of computer science makes calculation power have huge promotion, convolution mind
It is also attracted much attention again through network and starts to play the part of important role in various applications.Due to sending out for a long time
Exhibition, convolutional neural networks have mature Fundamentals of Mathematics and theories integration.But compared to human brain, the efficiency of convolutional neural networks is also
Have very big gap, so in order to be able to achieve the neural network of high energy efficiency, impulsive neural networks become people research object it
One.Impulsive neural networks are different from traditional biological neural network, are not bionical in complete progress structure, but carry out
Bionical on behaviour, that is, the mode for taking pulse input and pulse to export carries out information transmitting.
In impulsive neural networks, the neuron due to not receiving pulse not will do it operation, so operand is compared
It is reduced much in convolutional neural networks, and the core operation of spiking neuron is that film potential is added, and can save convolutional Neural
Multiplication operation in network, this also reduces the consumption of energy and the expense of hardware resource to a certain extent.But pulse is refreshing
One through network the disadvantage is that currently without mature theoretical basis and Fundamentals of Mathematics, ununified efficient training algorithm.One
The common solution of kind is that the function of convolutional neural networks is realized using impulsive neural networks, and this network is referred to as pulse
Convolutional neural networks, which has the theoretical basis of convolutional neural networks simultaneously, while having the high energy of impulsive neural networks again
Characteristic is imitated, in the case where little with convolutional neural networks performance gap, efficiency has apparent raising.
The topological structure of impulsive neural networks and convolutional neural networks is essentially identical, but the basic place of impulsive neural networks
Reason unit has been replaced by spiking neuron, and spiking neuron is only in the pulse letter for receiving upper level neuron and launching
Number ability and the variation of retrograde film potential, after the value of film potential is more than threshold value, neuron will be to all neurons transmittings of next stage
Pulse, and the film potential of itself is resetted.Constantly pulse is transmitted to last output stage so, is generated in last output end
Pulse train will to input carry out Classification and Identification.
Common issue is that the input port number between neuron is not fixation, i.e., in pulse convolutional neural networks
Make in the same network, input port number between layers may also be different, so design it is a kind of it is general can
The neuron of configuration input port number is one and important studies a question.
There are a large amount of data to transmit in convolutional neural networks, equally, after being converted into pulse convolutional neural networks, in network
In there is also a large amount of pulse trains, although ' 1 ' number is seldom in the sequence, i.e., next layer of operation number is seldom, arteries and veins
The sequencing for rushing sequence determines the classification of final output, so although pulse convolutional neural networks greatly reduce operation
Amount, but the data volume transmitted is but still considerable, therefore in hardware design, for large batch of in pulse convolutional neural networks
How pulse train, which carries out high degree of parallelism processing, is also one and important studies a question.
Summary of the invention
In view of this, can support the present invention provides a kind of configurable high degree of parallelism spiking neuron array to more
Kind input port number neuron is adapted to, while can be improved the degree of parallelism of pulse convolutional neural networks processing.
The present invention provides a kind of configurable high degree of parallelism spiking neuron arrays, comprising: multiple row is by configurable basis
The array and multiple alternative selectors that unit is constituted；Wherein:
Each column is sequentially connected by can configure the configurable base unit in the array that base unit is constituted；
Configurable base unit between adjacent two column staggers successively one and is connected by the alternative selector.
Preferably, the configurable base unit includes: the on piece memory module for storing weight and the logic for calculating
Computing module.
Preferably, the logic calculation module for calculating includes: cell space unit, reset unit, path selection unit
And pulse emitting units；Wherein:
The cell space unit is connected with the reset unit and the path selection unit respectively, tired for carrying out to weight
Add；
The reset unit is connected with the cell space unit and the pulse emitting units respectively, for control film potential into
Row resets；
The pulse emitting units are connected with the path selection unit and the reset unit respectively；
The present unit in path is connected with the cell space unit and the pulse emitting units respectively.
Preferably, the cell space unit includes: the register for storing weight accumulation.
Preferably, the pulse emitting units include: the register and comparator for storing threshold value.
In conclusion the invention discloses a kind of configurable high degree of parallelism spiking neuron arrays, comprising: multiple row is by can
Configure array and multiple alternative selectors that base unit is constituted；Wherein: the array that each column is constituted by can configure base unit
In configurable base unit be sequentially connected；Configurable base unit between adjacent two column staggers successively one by described two
A selector is selected to be connected.The present invention can support to be adapted to a variety of input port number neurons, while can be improved pulse
The degree of parallelism of convolutional neural networks processing.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is a kind of structural representation of configurable high degree of parallelism spiking neuron array embodiment disclosed by the invention
Figure；
Fig. 2 is a kind of structural schematic diagram of configurable base unit disclosed by the invention；
Fig. 3 is a kind of structural schematic diagram of configurable base unit disclosed by the invention；
Fig. 4 is a kind of circuit topology figure of configurable base unit disclosed by the invention；
Fig. 5 is a kind of multi input neuron working timing figure disclosed by the invention；
Fig. 6 is configurable high degree of parallelism spiking neuron array parallel data processing schematic diagram disclosed by the invention；
Fig. 7 is that configurable high degree of parallelism spiking neuron array disclosed by the invention illustrates the processing of pulse train
Figure.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
As shown in Figure 1, being a kind of knot of configurable high degree of parallelism spiking neuron array embodiment disclosed by the invention
Structure schematic diagram, configurable high degree of parallelism spiking neuron array may include: multiple row by can configure base unit
The array and multiple alternative selectors 10 that (Configurable Basic Unit, CBU) is constituted；Wherein:
Each column is sequentially connected by can configure the configurable base unit in the array that base unit CBU is constituted；
Configurable base unit CBU between adjacent two column staggers successively one and is connected by alternative selector 10.
Wherein, it each can configure the function of base unit are as follows:
1, the film potential that adds up simultaneously transmits film potential to adjacent configurable base unit, sets itself film potential after transmission
Zero.
2, the film potential that adds up simultaneously stores film potential, and only own transmission pulse is just by film potential zero setting.
Wherein function 2 can embody the basic function of a spiking neuron, but when the multiple neurons of needs are matched
When closing the neuron to realize a multi input, it is necessary to which a configurable base unit uses function 2, and other configurable
Base unit then uses function 1, realizes a complete multi input neuron by the cooperation of multiple configurable base units.It is logical
It crosses and the control signal of the configurable base unit of composition neuron is handled, different degrees of loop unrolling may be implemented,
Spiking neuron of the less hardware resource realization compared with multi input can be used.
The configurable base unit of one column has connection relationship between each other, while by configuring built-in function, can cut off
Or the connection relationship connected with next configurable base unit then connects with next configurable base unit if function 1
It connects, if function 2, then cuts off the connection with next configurable base unit.It is each arrange between configurable base unit according to
Diagonal line has connection, this is to be multiplexed to the greatest extent in order to parallel processing input pulse sequence to input, reduces number
According to repetition read, have an alternative selector on each diagonal line, this is because when the data of input be not according to
When step-length is 1 variation, mistake can be generated by passing data using diagonal line, and connection between the column and the column will be cut off at this time, Mei Yilie
It will be from external input pulse train.
In conclusion the invention discloses a kind of configurable high degree of parallelism spiking neuron arrays, comprising: multiple row is by can
Configure array and multiple alternative selectors that base unit is constituted；Wherein: the array that each column is constituted by can configure base unit
In configurable base unit be sequentially connected；Configurable base unit between adjacent two column staggers successively one by described two
A selector is selected to be connected.The present invention can support to be adapted to a variety of input port number neurons, while can be improved pulse
The degree of parallelism of convolutional neural networks processing.
If Fig. 2~Fig. 4 is the schematic diagram of configurable base unit disclosed by the invention, as shown in Fig. 2, configurable basis is single
Member may include: the on piece memory module for storing weight and the logic calculation module for calculating.
Specifically, as shown in figure 3, the logic calculation module for calculating may include: cell space unit, reset unit, road
Diameter selecting unit and pulse emitting units；Wherein:
Cell space unit is connected with reset unit and path selection unit respectively, for adding up to weight；
Reset unit is connected with cell space unit and pulse emitting units respectively, is resetted for controlling film potential；
Pulse emitting units are connected with path selection unit and the reset unit respectively；
The present unit in path is connected with cell space unit and the pulse emitting units respectively.
Specifically, entire configurable basis is single as shown in figure 4, giving the internal structure of a configurable base unit
Member is segmented into two parts, first is that the logic calculation module portion of the on piece memory module Memory of storage weight and responsible operation
Point.Wherein, the main input signal of Memory includes clock clk, address signal Addr and input pulse signal inspike.
Neuron connection weight is stored in Memory, judges whether to read data in rising edge clock, when the value of input pulse signal is
When ' 1 ', the weight that address is " Addr " is read out, and be input to logic computing unit.If input pulse signal is ' 0 ',
The weight 0 of Memory output.
Wherein, logic calculation module includes the circuit of three major parts, and one is to carry out the cumulative cell space unit of weight
Soma, the major function of this part be it is cumulative for being carried out to weight, for weight there are two source, one is read from Memory
Weight out, the other is can configure the upper configurable base unit that base unit is connected from this.Pass through one two
A selector is selected to be controlled, alternative selector is controlled by sum_en signal, and the configurable basis on a column is single
The sum_en signal that member receives successively delays a cycle, realizes the pipeline design by control sum_en.Cumulative weight
There are in a register in cell space unit, when thering is new weight or film potential to add up every time, by the film potential of itself and defeated
Enter to be added, if reset signal is effective, the value of next register will become (0+weight), i.e., realization warm reset is same
When do not influence next pulse input reception.
Another part of logic calculation module is the pulse emitting units Fire Part for carrying out impulse ejection in Fig. 4, should
The register and a comparator that part stores threshold value by one form, if the value of film potential is more than threshold value, can emit pulse,
Pulse signal will continue a clock cycle, while the value of cell space part can be carried out a warm reset by pulse signal.
The third component part of logic calculation module is reset unit Reset Part in Fig. 4, this part is believed by ctl
It number is configured, resets entire circuit either by sum_en signal control film potential, or controlled by outspike
Molding current potential is resetted.
A remaining circuit module is path selection unit in Fig. 4, and shape is that rectangle inside has one ' × ', main
Function is the Path selection for carrying out data, and the function of path selection unit is 2 inputs 2 output, if ctl signal is ' 1 ',
It is exported after input is swapped, if ctl signal is ' 0 ', by the directly corresponding output of input signal.The two of path selection unit
A input is film potential and ' 0 ' respectively, output be respectively then entire configurable base unit part and output psum_out and
The film of pulse emitting units inputs Vt, and when ctl signal is 0, film potential will be transferred directly to the next and configurable basis
The connected configurable base unit of unit, reset portion is also controlled the synchronous reset that is configured as by sum_en at this time, works as ctl
When signal is 1, which will transmit signal ' 0 ' to next configurable base unit, i.e. connection is cut off, and
And the reset of the configurable base unit will be exported outspike by pulse and be controlled, and just will do it film when only generating pulse
The reset of current potential.
Specifically, being accomplished that a 3*3 as shown in figure 5, describe the timing that configurable base unit cooperates
Spiking neuron, using 3 configurable base units, and by control sum_en signal come carry out in time 3 times multiplexing,
It is equivalent to and a 9 input pulse neurons has been carried out one cycle expansion, need 4 clock cycle that could export one at this time
As a result, CBU (1) is first begin to operation, CBU (2) and CBU (3) successively prolong the latter clock cycle, will have one after every three periods
A period, CBU (1) transmit film potential to CBU (2), and next clock cycle, CBU (1) will will do it warm reset and receive next
A pulse, while CBU (2) is accumulated the sum of CBU (1) and CBU (2) film potential to CBU (3) transmission.The operation time sequence of CBU by
Sum_en control, when sum_en is ' 1 ', cumulative film potential is passed from 0x01 to 0x03 from external input, weight storage address
Increase, when itself film potential is saved a clock cycle for ' 0 ', CBU so that next stage inputs by sum_en.Due to working sequence
A clock cycle is staggered successively, with the mode treatment input data of assembly line between multiple configurable base units.
Fig. 6 describes the high concurrency of array.Although in order to further enhance the degree of parallelism of array, Ke Yitong in Fig. 5
Multiple row neuron is crossed to promote degree of parallelism, while the extent for multiplexing of data can be improved again.In Fig. 6, come with the array of a 6*6
Be configured to 12 neurons, by configurable base unit it is recognised that the data connection between the third line and fourth line be by
Cutting, while the alternative selector between the third line and fourth line will from outside read in data rather than can from upper one
It configures base unit and reads data.By with postponing, the neuron of top half and the neuron of lower half portion are two kinds of neurons,
It is completely separate on the topology, by taking top half as an example, top half is configured to the neuron of 6 3*3, and this 6
The weight of neuron is identical, it is therefore an objective to the degree of parallelism of processing is improved, first neuron receives the input of 3 row data,
Second neuron and first neuron are multiplexed two row data, and handle a line new data, third to sixth nerve
First principle is identical, i.e. 6 3*3 neurons of top can handle 8 row data simultaneously.
Fig. 7 gives a more intuitive example then to explain high concurrency, while pulse train is also described in detail
Transmission and treatment process.Input is multiple pulse trains, a series of figures is formed in the pulse in same time period, then by pulse
Figure is input in CBU array and is handled, and is the diagram of the CBU ARRAY PROCESSING pulse train of a 3*3 in figure, by the 3*3 gusts
Column are configured to the spiking neuron of 3*3, i.e., every four periods can generate an output, can handle five-element's data simultaneously, export
Three pulse trains.The output pulse sequence of generation is split according to the time cycle, is generated new pulse sequence diagram and is passed to
Next stage, to the last level-one is identified, generate output at first over a period of time is classification results.
In conclusion configurable base unit provided by the invention can by signal control realize median transmission or
Impulse ejection function；And array can then be reduced by reasonably configuring the multiplexing for realizing data and the treatment effeciency for improving data
High degree of parallelism calculating is able to achieve while data exchange number between memory again.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.For device disclosed in embodiment
For, since it is corresponded to the methods disclosed in the examples, so being described relatively simple, related place is said referring to method part
It is bright.
Professional further appreciates that, unit described in conjunction with the examples disclosed in the embodiments of the present disclosure
And algorithm steps, can be realized with electronic hardware, computer software, or a combination of the two, in order to clearly demonstrate hardware and
The interchangeability of software generally describes each exemplary composition and step according to function in the above description.These
Function is implemented in hardware or software actually, the specific application and design constraint depending on technical solution.Profession
Technical staff can use different methods to achieve the described function each specific application, but this realization is not answered
Think beyond the scope of this invention.
The step of method described in conjunction with the examples disclosed in this document or algorithm, can directly be held with hardware, processor
The combination of capable software module or the two is implemented.Software module can be placed in random access memory (RAM), memory, read-only deposit
Reservoir (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technology
In any other form of storage medium well known in field.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (5)
1. a kind of configurable high degree of parallelism spiking neuron array characterized by comprising multiple row is by can configure base unit
The array of composition and multiple alternative selectors；Wherein:
Each column is sequentially connected by can configure the configurable base unit in the array that base unit is constituted；
Configurable base unit between adjacent two column staggers successively one and is connected by the alternative selector.
2. configurable high degree of parallelism spiking neuron array according to claim 1, which is characterized in that described configurable
Base unit includes: the on piece memory module for storing weight and the logic calculation module for calculating.
3. configurable high degree of parallelism spiking neuron array according to claim 2, which is characterized in that described based on
The logic calculation module of calculation includes: cell space unit, reset unit, path selection unit and pulse emitting units；Wherein:
The cell space unit is connected with the reset unit and the path selection unit respectively, for adding up to weight；
The reset unit is connected with the cell space unit and the pulse emitting units respectively, is answered for controlling film potential
Position；
The pulse emitting units are connected with the path selection unit and the reset unit respectively；
The present unit in path is connected with the cell space unit and the pulse emitting units respectively.
4. configurable high degree of parallelism spiking neuron array according to claim 3, which is characterized in that the cell space list
Member includes: the register for storing weight accumulation.
5. configurable high degree of parallelism spiking neuron array according to claim 4, which is characterized in that the pulse hair
Penetrating unit includes: the register and comparator for storing threshold value.
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| CN113269317B (en) * | 2021-04-14 | 2024-05-31 | 南京大学 | Pulse neural network computing array |
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| CN113269317B (en) * | 2021-04-14 | 2024-05-31 | 南京大学 | Pulse neural network computing array |
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