CN110007853B - Nandflash command processing method, Nandflash command processing device, terminal and storage medium - Google Patents
Nandflash command processing method, Nandflash command processing device, terminal and storage medium Download PDFInfo
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- CN110007853B CN110007853B CN201910089576.2A CN201910089576A CN110007853B CN 110007853 B CN110007853 B CN 110007853B CN 201910089576 A CN201910089576 A CN 201910089576A CN 110007853 B CN110007853 B CN 110007853B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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Abstract
The invention discloses a Nandflash command processing method, a Nandflash command processing device, a Nandflash command processing terminal and a computer readable storage medium.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a Nandflash command processing method, a Nandflash command processing device, a Nandflash command processing terminal and a computer readable storage medium.
Background
With the continuous progress of communication calculation, people put forward higher requirements on the transmission rate of the flash memory, the operation of the existing flash memory is basically serial, if data in the flash memory is to be read, an Lc command needs to be sent out first, then the data is read out from the flash memory after the data in the flash memory is ready, and the operation causes a lot of unnecessary waiting time, so that the performance of reading operation is limited, and the improvement of the transmission rate of the flash memory is limited finally.
Disclosure of Invention
The invention provides a Nandflash command processing method, a Nandflash command processing device, a Nandflash command processing terminal and a computer readable storage medium, which aim to solve the problem of low flash memory transmission rate in the prior art.
In a first aspect, the present invention provides a Nandflash command processing method, including:
receiving a read or write command to the Nandflash flash memory;
splitting the read or write command into a plurality of micro commands so that the Nandflash flashes on a multi-logic unit number LUN to realize parallel processing of each micro command;
the micro command is a basic command processed by the Nandflash flash memory operation.
Preferably, the micro-commands include one or more of:
c, finally writing the data into the micro-command in the flash memory array;
w, writing data into the micro-command in the data register in the flash memory through a physical bus;
lc, a micro command for loading data from the flash memory array into a cache register inside the flash memory;
l1d, micro-command to load data from flash array to data register immediately after Lc completes;
l2d, micro-command that loads data into the data register not immediately after Lc;
p, a micro-command for reading data from the flash memory cache register through a physical bus;
M, micro-command for moving data from data register of flash memory to buffer register;
suspend, perform a Suspend micro-command;
resume, micro command to Resume;
e, carrying out a micro-command of block erasing;
reset, a micro command to Reset.
Preferably, splitting the read or write command into a plurality of micro commands so that the Nandflash flash is stored on a multi-logical unit number LUN to realize parallel processing of each micro command includes:
and splitting the read or write command into a plurality of micro commands according to a preset splitting rule so that the Nandflash flash is stored on a multi-logic unit number LUN to realize parallel processing of each micro command.
Preferably, splitting the read or write command into a plurality of micro commands according to a preset splitting rule, including:
according to the flash memory type of the Nandflash flash memory, the write operation is divided into C, W + C or W + W + C micro commands, and the read operation is divided into a plurality of pairs of L and P micro commands.
Preferably, splitting the read or write command into a plurality of micro commands according to a preset splitting rule, including:
according to different physical addresses to be accessed, L1d and M are inserted between L and P for execution, and the micro command Suspend and Resume are inserted before C or E.
Preferably, splitting the read or write command into a plurality of micro commands according to a preset splitting rule, including:
The "W/C" or "E" micro-command is placed at the tail of the queue.
For the micro-command pair L (n) + P (n), the initial position of the queue insertion is found according to the W/R/E operation and the physical address, if the initial position of the queue insertion cannot be found, P with the same physical page address is further found, L is removed, P is kept, and if the P with the same physical page address cannot be found, the micro-command pair L (n) + P (n) is inserted according to a preset queue insertion rule.
Preferably, the l (n) + p (n) micro command pair is inserted according to a preset queue insertion rule, and comprises:
the state before queue insertion is Null or E or W + W + C, when inserting L (n) + P (n) micro-command pairs, the queue after insertion is lc (n), P (n), NULL or E or W + W + C;
the pre-queue-insertion states are M, P (x1), P (x2),. P (xn), and when inserting L (n) + P (n) micro command pairs, the inserted queues are L2d (n), P (x1), P (x2) … P (xn), M, P (n);
the state before queue insertion is P (x), W + C, C or Resume, when inserting L (n) + P (n) micro-command pair, the queue after insertion is P (x), lc (n), P (n), W + C or Resume;
the state before queue insertion is lc (x), P (x), Null or E or W + W + C, when the L (n) + P (n) micro-command pair is inserted, the queue after insertion is lc (x), L1d (n), P (x), M, P (n), Null or E or W + W + C;
Inserting the micro command M processed before in queue, wherein the position of the micro command M is at the beginning P (x) of the queue, and when inserting L (n) + P (n) micro command pairs, the inserted queue is P (x), c (n), P (n);
inserting the previously processed micro command Lc at the beginning of the queue P (x), Null or E or W + W + C, and when inserting L (n) + P (n) micro command pairs, inserting the queue L1d (n), P (x), M, P (n), Null or E or W + W + C;
the queue before queue insertion starts W + C or Resume, and when L (n) + P (n) micro-command pairs are inserted, the queue after insertion is lc (n), P (n), WC or C or Resume;
when a micro command pair L (n) + P (n) is inserted into the queue, the queue after insertion is S, lc (n), P (n), Resume, NULL or E or WWC.
In a second aspect, the present invention provides a Nandflash command processing apparatus, including: the receiving unit is used for receiving a read or write command of the Nandflash flash memory; the processing unit is used for splitting the read or write command into a plurality of micro commands so that the Nandflash flash is stored on a multi-logic unit number LUN to realize parallel processing of each micro command; the micro command is a basic command processed by the Nandflash flash memory operation.
In a third aspect, the present invention provides a terminal, where the terminal includes a processor and a storage device, where the storage device stores a plurality of instructions to implement a configuration method of a reference signal, and the processor executes the plurality of instructions to implement: receiving a read or write command to the Nandflash flash memory; splitting the read or write command into a plurality of micro commands so that the Nandflash flashes on a multi-logic unit number LUN to realize parallel processing of each micro command; the micro command is a basic command processed by the Nandflash flash memory operation.
In a fourth aspect, the present invention provides a computer-readable storage medium storing a signal-mapped computer program, which when executed by at least one processor, implements any one of the Nandflash command processing methods described above.
The invention has the following beneficial effects:
the invention splits the read-write command of the Nandflash flash memory into a plurality of micro commands, so that the plurality of micro commands can be executed in parallel, thereby improving the read-write performance of the flash memory, improving the utilization rate of the flash memory, reducing the idle time of the flash memory and further solving the problem of lower transmission rate of the existing flash memory.
Drawings
Fig. 1 is a schematic flowchart of a Nandflash command processing method according to a first embodiment of the present invention;
fig. 2 is a schematic structural diagram of a Nandflash command processing apparatus according to a first embodiment of the present invention.
Detailed Description
The invention provides a Nandflash command processing method for solving the problem of low transmission rate of the existing flash memory. The present invention will be described in further detail below with reference to the drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.
A first embodiment of the present invention provides a Nandflash command processing method, and with reference to fig. 1, the method includes:
s101, receiving a read or write command of a Nandflash flash memory;
s102, splitting the read or write command into a plurality of micro commands to enable the Nandflash flash to exist on a multi-logic unit number LUN to realize parallel processing of all the micro commands;
the micro-command is a basic command for operating and processing the Nandflash flash memory.
That is to say, the embodiment of the invention splits the read-write command of the Nandflash flash memory into a plurality of micro commands, so that a plurality of micro commands can be executed in parallel, thereby improving the read-write performance of the flash memory, improving the utilization rate of the flash memory and reducing the idle time of the flash memory.
The core idea of the invention is to split the read-write command of the Nandflash flash memory into a plurality of micro commands, i.e. split the read-write command of the flash memory into a plurality of smaller operation processing commands, so that the system can realize parallel processing of each micro command on a multi-logic unit number LUN.
The micro-command in the embodiment of the invention refers to a smaller operation processing state command which can be processed in flash software compared with a read-write command.
In specific implementation, the micro command according to the embodiment of the present invention includes one or more of the following:
C, finally writing the data into the micro-command in the flash memory array;
w, writing data into the micro-command in the data register in the flash memory through a physical bus;
lc, a micro command for loading data from the flash memory array into a cache register inside the flash memory;
l1d, micro commands to load data from the flash array into the data register immediately after Lc completes;
l2d, micro-command that loads data into the data register not immediately after Lc;
p, a micro-command for reading data from the flash memory cache register through a physical bus;
m, micro-command for moving data from data register of flash memory to buffer register;
suspend, perform Suspend micro-command;
resume, micro command to Resume;
e, carrying out a micro command of block erasing;
reset, a micro command to Reset.
It should be noted that the above-mentioned just micro commands are only some micro commands listed for explaining the method of the present invention, and in the implementation, a person skilled in the art can split the read/write command into other arbitrary micro commands according to actual needs, and the present invention is not limited to this.
The invention splits the read-write command into a plurality of micro commands, so that the system can realize better parallel processing performance on the multi-LUN flash memory.
Further, in this embodiment of the present invention, splitting the read or write command into a plurality of micro commands, so that the Nandflash flash has multiple logical unit numbers LUN to implement parallel processing of each micro command, includes:
and splitting the read or write command into a plurality of micro commands according to a preset splitting rule, so that the Nandflash flash is stored on a multi-logic unit number LUN to realize parallel processing of each micro command.
In specific implementation, the splitting the read or write command into a plurality of micro commands according to a preset splitting rule in the embodiment of the present invention includes: according to the flash memory type of the Nandflash flash memory, the write operation is divided into C, W + C or W + W + C micro commands, and the read operation is divided into a plurality of pairs of L and P micro commands.
In specific implementation, according to the embodiment of the present invention, the read or write command is split into a plurality of micro commands according to a preset splitting rule, or L1d and M may be inserted between L and P to be executed according to different physical addresses to be accessed, and Suspend and Resume micro commands are inserted before C or E.
Specifically, the embodiment of the invention divides the write operation into C, W + C or W + W + C micro-commands according to different flash memory types, divides the read operation into several pairs of L and P micro-commands, and inserts L1d and M between L and P according to different physical addresses to be accessed, and allows the micro-commands Suspend and Resume to be inserted before C or E, thereby improving the performance of reading.
For example, a nandflash of tlc (triple level process) type is split according to W + C, the first W corresponds to Lowerpage, the second W corresponds to Middle page, and C corresponds to HigherPage, and the end of the write operation is marked only after the last micro-command C is processed. And for the nandflash of MLC type, splitting is carried out according to the mode of W + C.
In addition, the embodiment of the present invention splits the read or write command into a plurality of micro commands according to a preset splitting rule, including: the method comprises the steps of placing a 'W/C' or 'E' micro-command at the tail of a queue, finding a starting position of queue insertion for an L (n) + P (n) micro-command pair according to a W/R/E operation and a physical address, further finding P with the same physical page address if the starting position of the queue insertion cannot be found, removing the L, keeping the P, and inserting the L (n) + P (n) micro-command pair according to a preset queue insertion rule if the P with the same physical page address cannot be found.
In specific implementation, the inserting of the l (n) + p (n) micro-command pair according to the preset queue insertion rule in the embodiment of the present invention includes:
the state before queue insertion is Null or E or W + W + C, when inserting L (n) + P (n) micro-command pairs, the queue after insertion is lc (n), P (n), NULL or E or W + W + C;
The state before queue insertion is M, P (x1), P (x2),. P (xn), when inserting L (n) + P (n) micro command pair, the queue after insertion is L2d (n), P (x1), P (x2) … P (xn), M, P (n);
the state before queue insertion is P (x), W + C, C or Resume, when inserting L (n) + P (n) micro-command pair, the queue after insertion is P (x), lc (n), P (n), W + C or Resume;
the state before queue insertion is lc (x), P (x), Null or E or W + W + C, when the L (n) + P (n) micro-command pair is inserted, the queue after insertion is lc (x), L1d (n), P (x), M, P (n), Null or E or W + W + C;
inserting the micro command M processed before in queue, wherein the position of the micro command M is at the beginning P (x) of the queue, and when inserting L (n) + P (n) micro command pairs, the inserted queue is P (x), c (n), P (n);
inserting the previously processed micro command Lc at the beginning of the queue P (x), Null or E or W + W + C, and when inserting L (n) + P (n) micro command pairs, inserting the queue L1d (n), P (x), M, P (n), Null or E or W + W + C;
the queue before queue insertion starts W + C or Resume, and when L (n) + P (n) micro-command pairs are inserted, the queue after insertion is lc (n), P (n), WC or C or Resume;
when a micro command pair L (n) + P (n) is inserted into the queue, the queue after insertion is S, lc (n), P (n), Resume, NULL or E or WWC.
The following will explain the embodiment of the present invention by using table 1 to insert l (n) + p (n) micro-command pairs according to the preset queue insertion rule:
generally, the embodiment of the invention fully exerts the hardware capability of the flash memory on the multi-LUN flash memory device through the micro-command queue and the management algorithm for the micro-command queue, realizes better parallel processing operation and improves the read-write performance of the whole system.
A second embodiment of the present invention provides a Nandflash command processing apparatus, referring to fig. 2, including:
the receiving unit is used for receiving a read or write command of the Nandflash flash memory;
the processing unit is used for splitting the read or write command into a plurality of micro commands so that the Nandflash flash is stored on a multi-logic unit number LUN to realize parallel processing of each micro command;
the micro command is a basic command processed by the Nandflash flash memory operation.
That is to say, in the embodiment of the present invention, the processing unit splits the read-write command of the Nandflash flash memory into a plurality of micro commands, so that the plurality of micro commands can be executed in parallel, thereby improving the read-write performance of the flash memory, improving the utilization rate of the flash memory, and reducing the idle time of the flash memory.
The core idea of the invention is to split the read-write command of the Nandflash flash memory into a plurality of micro commands, i.e. split the read-write command of the flash memory into a plurality of smaller operation processing commands, so that the system can realize parallel processing of each micro command on a multi-logic unit number LUN.
The micro-command in the embodiment of the invention refers to a smaller operation processing state command which can be processed in flash memory software compared with a read-write command.
In specific implementation, the micro command according to the embodiment of the present invention includes one or more of the following:
c, finally writing the data into the micro-command in the flash memory array;
w, writing data into the micro-command in the data register in the flash memory through a physical bus;
lc, a micro command for loading data from the flash memory array into a cache register inside the flash memory;
l1d, micro-command to load data from flash array to data register immediately after Lc completes;
l2d, micro-command that loads data into the data register not immediately after Lc;
p, a micro-command for reading data from the flash memory cache register through a physical bus;
m, micro-command for moving data from data register of flash memory to buffer register;
suspend, perform a Suspend micro-command;
resume, micro command to Resume;
e, carrying out a micro-command of block erasing;
reset, a micro command to Reset.
It should be noted that the above-mentioned just micro commands are only some micro commands listed for explaining the method of the present invention, and in the implementation, a person skilled in the art can split the read/write command into other arbitrary micro commands according to actual needs, and the present invention is not limited to this.
The invention splits the read-write command into a plurality of micro commands, so that the system can realize better parallel processing performance on the multi-LUN flash memory.
Further, in this embodiment of the present invention, the processing unit is further configured to split the read or write command into a plurality of micro commands according to a preset splitting rule, so that the Nandflash flash is stored on the multiple logic unit number LUN to implement parallel processing of each micro command.
In specific implementation, the processing unit according to the embodiment of the present invention splits a write operation into C, W + C or W + C micro commands and splits a read operation into a plurality of pairs of L and P micro commands according to the flash memory type of the Nandflash flash memory. And according to different physical addresses to be accessed, inserting L1d and M between L and P to execute, and inserting the micro command Suspend and Resume before C or E.
Specifically, the processing unit of the embodiment of the present invention splits a write operation into C, W + C or W + C micro-commands according to different flash memory types, splits a read operation into several pairs of L and P micro-commands, and inserts L1d and M between L and P to execute according to different physical addresses to be accessed, and allows the micro-commands Suspend and Resume to be inserted before C or E, thereby improving the performance of the read.
For example, a nandflash of tlc (triple level process) type is split according to W + C, the first W corresponds to Lowerpage, the second W corresponds to Middle page, and C corresponds to HigherPage, and only after the last micro-command C is processed, the end of the writing operation is marked. And for the nandflash of the MLC type, splitting is carried out according to a W + C mode.
In addition, the processing unit in the embodiment of the present invention is further configured to place a "W/C" or "E" micro command at the tail of the queue, and for an L (n) + P (n) micro command pair, first find a starting position of a queue insertion according to a W/R/E operation and a physical address, if the starting position of the queue insertion cannot be found, further find P having the same physical page address, remove L, keep P, and if the P having the same physical page address cannot be found, insert the L (n) + P (n) micro command pair according to a preset queue insertion rule.
In specific implementation, the inserting l (n) + p (n) micro command pairs according to the preset queue insertion rule in the embodiment of the present invention includes:
the state before queue insertion is Null or E or W + W + C, and when L (n) + P (n) micro command pairs are inserted, the queue after insertion is lc (n), P (n), NULL or E or W + W + C;
the state before queue insertion is M, P (x1), P (x2),. P (xn), when inserting L (n) + P (n) micro command pair, the queue after insertion is L2d (n), P (x1), P (x2) … P (xn), M, P (n);
The state before queue insertion is P (x), W + C, C or Resume, when the micro-command pairs L (n) + P (n) are inserted, the inserted queues are P (x), lc (n), P (n), W + C or Resume;
the status before queue insertion is lc (x), P (x), Null or E or W + W + C, and when the micro command pairs L (n) + P (n) are inserted, the queue after insertion is lc (x), L1d (n), P (x), M, P (n), Null or E or W + W + C;
inserting the micro command M processed before in queue, wherein the position of the micro command M is at the beginning P (x) of the queue, and when inserting L (n) + P (n) micro command pairs, the inserted queue is P (x), c (n), P (n);
inserting the previously processed micro command Lc at the beginning of the queue P (x), Null or E or W + W + C, and when inserting L (n) + P (n) micro command pairs, inserting the queue L1d (n), P (x), M, P (n), Null or E or W + W + C;
the queue before queue insertion starts to be W + C or Resume, and when the micro command pairs L (n) + P (n) are inserted, the queue after insertion is lc (n), P (n), WC or C or Resume;
when a micro command pair L (n) + P (n) is inserted into the queue, the queue after insertion is S, lc (n), P (n), Resume, NULL or E or WWC.
Generally, the embodiment of the invention fully exerts the hardware capability of the flash memory on the multi-LUN flash memory device through the micro-command queue and the management algorithm for the micro-command queue, realizes better parallel processing operation and improves the read-write performance of the whole system.
The relevant content of the embodiments of the present invention can be understood by referring to the method embodiments, which are not described in detail herein.
A third embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores a signal-mapped computer program, which when executed by at least one processor, implements the method of:
receiving a read or write command to the Nandflash flash memory;
splitting the read or write command into a plurality of micro commands so that the Nandflash flashes on a multi-logic unit number LUN to realize parallel processing of each micro command;
the micro command is a basic command processed by the Nandflash flash memory operation.
The relevant content of the embodiments of the present invention can be understood by referring to the method embodiments, which are not described in detail herein.
A fourth embodiment of the present invention provides a terminal, where the terminal includes any one of the Nandflash command processing apparatuses in the second embodiment of the present invention, which can be understood with reference to the second embodiment of the present invention specifically, and details are not described herein.
Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, and the scope of the invention should not be limited to the embodiments described above.
Claims (5)
1. A Nandflash command processing method is characterized by comprising the following steps:
receiving a read or write command to the Nandflash flash memory;
splitting the read or write command into a plurality of micro commands so that the Nandflash flash has multiple Logic Unit Numbers (LUNs) to realize parallel processing of each micro command;
the micro command is a basic command processed by the Nandflash flash memory operation;
the micro-commands include one or more of:
c, finally writing the data into the micro-command in the flash memory array;
w, writing data into the micro-command in the data register in the flash memory through a physical bus;
lc, a micro command for loading data from the flash memory array into a cache register inside the flash memory;
l1d, micro-command to load data from flash array to data register immediately after Lc completes;
l2d, micro commands that load data into the data register not immediately after Lc;
p, a micro-command for reading data from the flash memory cache register through a physical bus;
m, micro-command for moving data from data register of flash memory to buffer register;
suspend, perform a Suspend micro-command;
resume, micro command to Resume;
e, carrying out a micro-command of block erasing;
Reset, a micro command to Reset;
splitting the read or write command into a plurality of micro commands so that the Nandflash flash has multiple Logic Unit Numbers (LUNs) to realize parallel processing of each micro command, wherein the method comprises the following steps:
splitting the read or write command into a plurality of micro commands according to a preset splitting rule so as to enable the Nandflash to exist on a multi-logic unit number LUN to realize parallel processing of each micro command;
splitting the read or write command into a plurality of micro commands according to a preset splitting rule, including:
according to the flash memory type of the Nandflash flash memory, splitting write operation into C, W + C or W + W + C micro commands, and splitting read operation into a plurality of pairs of L and P micro commands;
splitting the read or write command into a plurality of micro commands according to a preset splitting rule, including:
according to different physical addresses to be accessed, inserting L1d and M between L and P for execution, and inserting Suspend micro command and Resume micro command before C or E;
splitting the read or write command into a plurality of micro commands according to a preset splitting rule, including:
placing the "W/C" or "E" micro-commands at the tail of the queue;
for the micro-command pair L (n) + P (n), the initial position of the queue insertion is found according to the W/R/E operation and the physical address, if the initial position of the queue insertion cannot be found, P with the same physical page address is further found, L is removed, P is kept, and if the P with the same physical page address cannot be found, the micro-command pair L (n) + P (n) is inserted according to a preset queue insertion rule.
2. The method of claim 1, wherein inserting the l (n) + p (n) micro command pair according to a preset queue insertion rule comprises:
the state before queue insertion is Null or E or W + W + C, when inserting L (n) + P (n) micro-command pairs, the queue after insertion is lc (n), P (n), NULL or E or W + W + C;
the pre-queue-insertion states are M, P (x1), P (x2),. P (xn), and when inserting L (n) + P (n) micro command pairs, the inserted queues are L2d (n), P (x1), P (x2) … P (xn), M, P (n);
the state before queue insertion is P (x), W + C, C or Resume, when inserting L (n) + P (n) micro-command pair, the queue after insertion is P (x), lc (n), P (n), W + C or Resume;
the state before queue insertion is lc (x), P (x), Null or E or W + W + C, when the L (n) + P (n) micro-command pair is inserted, the queue after insertion is lc (x), L1d (n), P (x), M, P (n), Null or E or W + W + C;
inserting the micro command M processed before in queue at the beginning P (x) of the queue, and when inserting L (n) + P (n) micro command pairs, inserting the queue after being inserted as P (x), lc (n), P (n);
inserting the previously processed micro command Lc at the beginning of the queue P (x), Null or E or W + W + C, and when inserting L (n) + P (n) micro command pairs, inserting the queue L1d (n), P (x), M, P (n), Null or E or W + W + C;
The queue before queue insertion starts to be W + C or Resume, and when the micro command pairs L (n) + P (n) are inserted, the queue after insertion is lc (n), P (n), WC or C or Resume;
when inserting L (n) + P (n) micro-command pairs, the inserted queues are S, lc (n), P (n), Resume, NULL or E or W + W + C.
3. A Nandflash command processing device is characterized by comprising:
the receiving unit is used for receiving a read or write command of the Nandflash flash memory;
the processing unit is used for splitting the read or write command into a plurality of micro commands so as to enable the Nandflash to exist on a multi-logic unit number LUN to realize parallel processing of each micro command;
the processing unit is further configured to split the read or write command into a plurality of micro commands, so that the Nandflash flash has multiple logical unit numbers LUN to implement parallel processing of each micro command, including: splitting the read or write command into a plurality of micro commands according to a preset splitting rule so as to enable the Nandflash to exist on a multi-logic unit number LUN to realize parallel processing of each micro command; splitting the read or write command into a plurality of micro commands according to a preset splitting rule, including: according to the flash memory type of the Nandflash flash memory, splitting write operation into C, W + C or W + W + C micro commands, and splitting read operation into a plurality of pairs of L and P micro commands; splitting the read or write command into a plurality of micro commands according to a preset splitting rule, including: according to different physical addresses to be accessed, inserting L1d and M between L and P for execution, and inserting Suspend micro command and Resume micro command before C or E; splitting the read or write command into a plurality of micro commands according to a preset splitting rule, including: placing the "W/C" or "E" micro-commands at the tail of the queue; for the micro-command pair L (n) + P (n), firstly, finding the initial position of the queue insertion according to the W/R/E operation and the physical address, if the initial position of the queue insertion cannot be found, further finding P with the same physical page address, removing L, keeping P, and if the P with the same physical page address cannot be found, inserting the micro-command pair L (n) + P (n) according to a preset queue insertion rule;
The micro-command is a basic command processed by the Nandflash flash memory operation, and the micro-command comprises one or more of the following: c, finally writing the data into the micro-command in the flash memory array; w, writing data into a micro command in a data register in the flash memory through a physical bus; lc, a micro command for loading data from the flash memory array into a cache register inside the flash memory; l1d, micro-command to load data from flash array to data register immediately after Lc completes; l2d, micro-command that loads data into the data register not immediately after Lc; p, a micro-command for reading data from the flash memory cache register through a physical bus; m, micro-command for moving data from data register of flash memory to buffer register; suspend, perform a Suspend micro-command; resume, micro command to Resume; e, carrying out a micro-command of block erasing; reset, a micro command to Reset.
4. A terminal, comprising a processor and a storage device, wherein the storage device stores a plurality of instructions for implementing a reference signal configuration method, and the processor executes the plurality of instructions for implementing:
Receiving a read or write command to the Nandflash flash memory;
splitting the read or write command into a plurality of micro commands so that the Nandflash flash has multiple Logic Unit Numbers (LUNs) to realize parallel processing of each micro command;
splitting the read or write command into a plurality of micro commands so that the Nandflash flash has multiple Logic Unit Numbers (LUNs) to realize parallel processing of each micro command, wherein the method comprises the following steps: splitting the read or write command into a plurality of micro commands according to a preset splitting rule so as to enable the Nandflash to exist on a multi-logic unit number LUN to realize parallel processing of each micro command;
splitting the read or write command into a plurality of micro commands according to a preset splitting rule, including: according to the flash memory type of the Nandflash flash memory, splitting write operation into C, W + C or W + W + C micro commands, and splitting read operation into a plurality of pairs of L and P micro commands;
splitting the read or write command into a plurality of micro commands according to a preset splitting rule, including: according to different physical addresses to be accessed, inserting L1d and M between L and P for execution, and inserting Suspend micro command and Resume micro command before C or E;
splitting the read or write command into a plurality of micro commands according to a preset splitting rule, including: placing the "W/C" or "E" micro-commands at the tail of the queue; for the micro-command pair L (n) + P (n), firstly, finding the initial position of the queue insertion according to the W/R/E operation and the physical address, if the initial position of the queue insertion cannot be found, further finding P with the same physical page address, removing L, keeping P, and if the P with the same physical page address cannot be found, inserting the micro-command pair L (n) + P (n) according to a preset queue insertion rule;
The micro-command is a basic command processed by the Nandflash flash memory operation, and the micro-command comprises one or more of the following: c, finally writing the data into the micro-command in the flash memory array; w, writing data into a micro command in a data register in the flash memory through a physical bus; lc, a micro command for loading data from the flash memory array into a cache register inside the flash memory; l1d, micro-command to load data from flash array to data register immediately after Lc completes; l2d, micro-command that loads data into the data register not immediately after Lc; p, a micro-command for reading data from the flash memory cache register through a physical bus; m, micro-command for moving data from data register of flash memory to buffer register; suspend, perform a Suspend micro-command; resume, micro command to Resume; e, carrying out a micro-command of block erasing; reset, a micro command to Reset.
5. A computer-readable storage medium, characterized in that it stores a signal-mapped computer program which, when executed by at least one processor, implements the Nandflash command processing method of any one of claims 1-2.
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