CN109995379B

CN109995379B - Method and device for processing information

Info

Publication number: CN109995379B
Application number: CN201711486605.6A
Authority: CN
Inventors: 张朝龙; 王坚; 乔云飞; 张公正
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2017-12-29
Filing date: 2017-12-29
Publication date: 2021-07-16
Anticipated expiration: 2037-12-29
Also published as: CN109995379A; WO2019128809A1

Abstract

The application provides an information processing method, and the QC-LDPC constructed by the method is beneficial to reducing error floor in the decoding process, so that the decoding performance can be improved. The method comprises the following steps: determining a first spreading factor and a correction value for the first spreading factor; determining a check matrix according to the first expansion factor and the correction value of the first expansion factor; and encoding the information sequence with the length of K by using the check matrix.

Description

Method and device for processing information

Technical Field

The present application relates to the field of information processing, and in particular, to a method and an apparatus for processing information.

Background

Low Density Parity Check code (LDPC) is a linear block code with a sparse Check matrix proposed by Robert g. The LDPC code not only has good performance approaching to the Shannon limit, but also has the advantages of low decoding complexity, flexible structure and the like, so that the LDPC code is widely applied to various fields in recent years. Among them, Quasi-Cyclic Low Density Parity Check (QC-LDPC) codes are LDPC codes with a Quasi-Cyclic structure, which are a subclass of LDPC codes, and have been a research hotspot in the field of channel coding in recent years due to their advantages of simple description, easy construction, storage space saving, and the like.

The construction process of the QC-LDPC code is a construction process of a parity check matrix (parity check matrix) of the QC-LDPC code. And the check matrix of the QC-LDPC is obtained by expanding the base matrix through an expansion factor on the basis of the base matrix. However, the error floor inevitably exists in the existing methods for constructing the check matrix of the QC-LDPC. The error floor is a key factor of low decoding performance of QC-LDPC in the practical application process.

Disclosure of Invention

The application provides a method and a device for processing information, and the QC-LDPC constructed by the method is beneficial to reducing error floor in the decoding process, thereby improving the decoding performance.

In a first aspect, the present application provides a method of processing information, the method comprising: determining a first spreading factor and a correction value for the first spreading factor; determining a check matrix according to the first expansion factor and the correction value; and encoding the information sequence with the length of K by using the check matrix, wherein K is a positive integer.

The information processing method of the embodiment of the application can correct the expansion factor corresponding to the length K of the information sequence with the error flat layer when determining the expansion factor Z of the QC-LDPC check matrix so as to skip the position with the error flat layer, thereby improving the decoding performance of the QC-LDPC.

With reference to the first aspect, in certain implementations of the first aspect, the correction value for the first spreading factor is related to a length K of the information sequence. For example, the length K of the information sequence and the correction value of the first spreading factor satisfy at least one of the following tables:

length of information sequence K	Correction value of first expansion factor
		96	1
152	1
		176	1
272	2
		304	2
368	2
		400	3

With reference to the first aspect, in certain implementations of the first aspect, the length K of the information sequence and the correction value of the first spreading factor satisfy at least one of the following tables:

length of information sequence K	Correction value of first expansion factor
		96	1
152	1
		176	1
272	2
		368	2
400	6

With reference to the first aspect, in certain implementations of the first aspect, determining the correction value for the first expansion factor includes: and determining the correction value of the first spreading factor according to the length K and the code rate R of the information sequence. That is, the correction value of the first spreading factor may be related to the length K of the information sequence and the code rate R. Determining the correction value for the first spreading factor in combination with K and the code rate R allows for a more refined correction than determining the correction value for the first spreading factor only on the basis of the length K of the information sequence.

With reference to the first aspect, in certain implementations of the first aspect, the length K of the information sequence, the correction value of the first spreading factor, and the code rate R satisfy at least one of the following tables:

with reference to the first aspect, in certain implementations of the first aspect, the information sequence K, the correction value for the first spreading factor, and the code rate R satisfy at least one of the following tables:

in this embodiment, the range (0,1) of the code rate R may be divided into 6 intervals. For the length K of an information sequence, the correction value of the first spreading factor can be determined from the above table, regardless of the actually used code rate. Therefore, according to the interval in which the actually adopted code rate falls, the correction value corresponding to the interval is adopted to correct the first expansion factor, so that more refined correction of the expansion factor of the check matrix can be realized, and the decoding performance of the LDPC is further improved.

In a second aspect, the present application provides an apparatus for processing information, which has the function of implementing the method in the first aspect and any one of the possible implementations of the first aspect. The functions can be realized by hardware, and the functions can also be realized by executing corresponding software by hardware. The hardware or software includes one or more units corresponding to the above functions. For example, the apparatus comprises a processing unit for: determining a first spreading factor and a correction value for the first spreading factor; determining a check matrix according to the first expansion factor and the correction value of the first expansion factor; and encoding the information sequence with the length of K by using the check matrix, wherein K is a positive integer. Further, the apparatus may further include a receiving unit, configured to receive the information sequence with length K to be encoded.

In one possible implementation, the apparatus for processing information in the second aspect may be a terminal or a base station.

The QC-LDPC constructed by the device for processing information provided by the embodiment of the application is beneficial to reducing error floor in the decoding process, thereby improving the decoding performance.

In a third aspect, the present application provides a computer-readable storage medium having stored thereon computer instructions, which, when executed on a computer, cause the computer to perform the method of the first aspect or any possible implementation manner of the first aspect.

In a fourth aspect, the present application provides a chip (or a chip system) including a memory and a processor, where the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that a communication device in which the chip is installed executes the method in the first aspect and any one of the possible implementations of the first aspect.

In a fifth aspect, the present application provides a computer program product comprising: computer program code for causing a computer to perform the method of the first aspect and any one of its possible implementations described above, when the computer program code runs on a computer.

In a sixth aspect, the present application provides a method of processing information, the method comprising: determining a first spreading factor and a correction value for the first spreading factor; determining a check matrix according to the first expansion factor and the correction value of the first expansion factor; and decoding the sequence to be decoded by using the check matrix.

It should be noted that, in the decoding process, the process of determining the check matrix at the decoding end (or at the receiving end of the information and/or data) is the same as that at the transmitting end. Therefore, the relationship that is satisfied between the correction value of the first spreading factor and the length K of the information sequence, or the relationship that is satisfied between the correction value of the first spreading factor, the length K of the information sequence, and the code rate R, which is described in any one of the possible implementations of the first aspect, is also applicable to the method for processing information according to the sixth aspect. For brevity, no further description is provided herein.

The QC-LDPC constructed by the information processing method provided by the application is beneficial to reducing error floor in the decoding process, thereby improving the decoding performance.

In a seventh aspect, the present application provides an apparatus for processing information, which has the function of implementing the method in any one of the possible implementations of the sixth aspect and the sixth aspect. The functions can be realized by hardware, and the functions can also be realized by executing corresponding software by hardware. The hardware or software includes one or more units corresponding to the above functions. For example, the apparatus comprises a processing unit for: determining a first spreading factor and a correction value for the first spreading factor; determining a check matrix according to the first expansion factor and the correction value of the first expansion factor; and decoding the sequence to be decoded by using the check matrix.

In a possible implementation manner, the apparatus for processing information in the seventh aspect may be a terminal or a base station.

In an eighth aspect, the present application provides a computer-readable storage medium having stored thereon computer instructions which, when run on a computer, cause the computer to perform the method of the sixth aspect or any possible implementation manner of the sixth aspect.

In a ninth aspect, the present application provides a chip (or a chip system) including a memory and a processor, the memory is used for storing a computer program, and the processor is used for calling and running the computer program from the memory, so that a communication device installed with the chip executes the method in the sixth aspect and any one of the possible implementation manners thereof.

In a tenth aspect, the present application provides a computer program product comprising: computer program code which, when run on a computer, causes the computer to perform the method of the sixth aspect and any one of its possible implementations.

In the method for processing information according to the embodiment of the present application, the spreading factor (i.e., the first spreading factor) for determining the check matrix is modified, so that the check matrix used for encoding skips over the position of the error floor, and thus the decoding performance can be improved.

Drawings

Fig. 1 is a wireless communication system 100 suitable for use in embodiments of the present application.

FIG. 2 is a schematic diagram of a check matrix for LDPC based on a matrix.

Fig. 3 is a graph comparing the performance of the LDPC code with the polarization code when K is 94 and N is 420.

Fig. 4 is a schematic flow chart of a method 200 of encoding of an embodiment of the present application.

Fig. 5 is a schematic diagram of BLER from BG2 matrix in NR and LOMS algorithm.

Fig. 6-11 are examples of determining whether an error floor exists based on a performance curve.

Fig. 12 is a schematic block diagram of an apparatus 600 for processing information according to an embodiment of the present application.

Fig. 13 is a schematic configuration diagram of an apparatus 700 for processing information according to an embodiment of the present application.

Fig. 14 is a schematic block diagram of an apparatus 800 for processing information according to an embodiment of the present application.

Fig. 15 is a schematic configuration diagram of an apparatus 900 for processing information according to an embodiment of the present application.

Detailed Description

The technical solution in the present application will be described below with reference to the accompanying drawings.

Fig. 1 is a wireless communication system 100 suitable for use in embodiments of the present application. At least one network device 101 may be included in the wireless communication system that communicates with one or more terminal devices (e.g., terminal device 102 and terminal device 103 shown in fig. 1). The network device may be a base station, or a device formed by integrating the base station and a base station controller, or other devices having similar communication functions.

A terminal is a device with communication function, and may include a handheld device with wireless communication function, a vehicle-mounted device, a wearable device, a computing device or other processing device connected to a wireless modem, and the like. The terminal can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; can also be deployed on the water surface (such as a ship and the like); and may also be deployed in the air (e.g., airplanes, balloons, satellites, etc.). The terminal may be a mobile phone (mobile phone), a tablet computer (Pad), a computer with a wireless transceiving function, a Virtual Reality (VR) terminal device, an Augmented Reality (AR) terminal device, a wireless terminal in industrial control (industrial control), a wireless terminal in unmanned driving (self driving), a wireless terminal in remote medical treatment (remote medical), a wireless terminal in smart grid (smart grid), a wireless terminal in transportation safety (transportation safety), a wireless terminal in smart city (smart city), a wireless terminal in smart home (smart home), and the like. Terminals can be called different names in different networks, for example: subscriber equipment, mobile stations, subscriber units, stations, cellular telephones, personal digital assistants, wireless modems, wireless communication devices, handheld devices, laptops, cordless telephones, wireless local loop stations, and the like. For convenience of description, the terminal is simply referred to in this application.

A Base Station (BS), also called a base station device, is a device deployed in a radio access network to provide a wireless communication function. The nomenclature of the base station may be different in different wireless access systems, for example, the base station in a Universal Mobile Telecommunications System (UMTS) network is called node B (NodeB), the base station in an LTE network is called evolved node B (eNB or eNodeB), the base station in a New Radio (NR) network is called a transmission point (TRP) or a next generation node B (gNB), or in other networks with multiple technologies integrated, or the base station in other evolved networks may also adopt other nomenclature. The invention is not limited thereto.

The wireless communication system mentioned in the embodiments of the present application includes but is not limited to: narrow Band-Internet of Things (NB-IoT), Global System for Mobile Communications (GSM), Enhanced Data rates for GSM Evolution (EDGE), Wideband Code Division Multiple Access (WCDMA), Code Division Multiple Access 2000 (Code Division Multiple Access, CDMA2000), Time Division-synchronous Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), and the next generation of 5G Mobile communication systems, namely enhanced Mobile bandwidth (eMBB), high reliability Low Latency Communication (URLLC), and enhanced mass Machine Type Communication (eMTC), or new Communication systems emerging in the future.

The network device and the terminal device in fig. 1 communicate by using wireless technology. When the network device sends a signal, it is an encoding end, and when the network device receives a signal, it is a decoding end. The same applies to the terminal device, which is the encoding side when the terminal device transmits a signal and the decoding side when the terminal device receives a signal.

In addition, the encoding end is an information and/or data transmitting end, and the decoding end is an information and/or data receiving end.

For ease of understanding, the relevant concepts related to the present application will first be briefly described.

Low Density Parity Check code (LDPC) is a kind of linear block code with sparse Check matrix, that is, zero elements in the Check matrix of the LDPC code are far more than non-zero elements, and the distribution of the non-zero elements has no regularity. Wherein, a code length is equal to N, and the linear block code with the information sequence length equal to K can be uniquely determined by the check matrix. The LDPC code not only has good performance approaching to the Shannon limit, but also has low decoding complexity and flexible structure, is a hotspot of research in the field of channel coding in recent years, and is widely applied to the fields of deep space communication, optical fiber communication, satellite digital video, audio broadcasting and the like at present.

Quasi-Cyclic Low Density Parity Check codes (QC-LDPC) are a subclass of LDPC codes. The parity check matrix (QC-LDPC) is obtained by extending a base matrix, which is hereinafter referred to as H_bThe check matrix is denoted as H. The position of the non-zero element in the base matrix, for example, the row and column where the non-zero element is located, can be described by a base map (BG).

If the base matrix H_bIs m in size_b×n_bThen the check matrix H is of size (m)_b·Z)×(n_bZ), where Z is referred to as the spreading factor of the check matrix.

An expression of the check matrix H of QC-LDPC is given below:

in the formula (1), each element of the check matrix H

Is a zero matrix or a cyclic shift matrix, wherein the cyclic shift matrix is a cyclic shift a to an identity matrix I of Z × Z size_ijThe bits are obtained. Therefore, a will also_ijA shifting factor referred to as a cyclic shift matrix, in some examples, a_ijCan also be represented as P_i,j。a_ijThe value range of (A) is more than or equal to-1_ij<Z。

If the check matrix H is a full rank matrix, it may be (n) of the base matrix_b-m_b) Column Placement (n)_b-m_b) Z information bits, we will base (n) of the matrix_b-m_b) The column is called an information column, and let k_b＝n_b-m_b。

When QC-LDPC encoding is used, if the length K of the information sequence is K_bInteger division, then each information bit position after spreading is used to place an information bit. If K is not K_bInteger division resulting in Z.k_b>K, then there will be (Z.k) in the check matrix H of the LDPC after expansion_b-K) redundant information bit positions, which may be referred to as padding bits.

FIG. 2 is a schematic diagram of a check matrix for LDPC based on a matrix. Referring to fig. 2, wherein a denotes the number of bits shifted and I is an identity matrix. As known to those skilled in the art, a linear block code with a code length of N and a number of information bits of K may be formed from a generator matrix G_K×NTo be defined. Information sequence S to be coded_L×KBy generating a matrix G_K×NIs mapped to a codeword. The linear block code can also pass through a check matrix H_(N-K)×KTo be described in an equivalent manner.

The following describes a procedure for determining a check matrix of QC-LDPC specified in the New Radio (NR).

(1) Determining K according to the length K of the information sequence_b。

In particular, K is determined according to the length K of the information sequence_bThe process is as follows:

(2) according to k_bThe spreading factor Z is determined.

Specifically, the determined spreading factor Z should satisfy the expression (2), and the value of Z should fall into table 1.

k_b×Z>K (2)

TABLE 1

It should be noted that, in step (2), if the value of Z satisfying expression (2) is a non-integer, then the value of Z is rounded up, so that the value of Z falls into table 1.

For example, if Z satisfying expression (2) is 65.5, then 65.5 is rounded up, and Z should be the smallest integer greater than 65.5 in table 1, that is, 72.

Then, according to the table 1, the index corresponding to the value of Z (corresponding to set index i in the table 1) is determined_LSValue of (d).

As can be seen in table 1, 72 corresponds to an index of 5.

(3) And determining a check matrix according to the expansion factor Z.

Specifically, according to the value of the spreading factor Z, an index corresponding to the value of Z is obtained, and taking table 1 as an example, while determining the spreading factor Z, a set index i corresponding to the spreading factor Z is obtained_LSThe value of (a). And determining a check matrix according to the value. Taking table 2 as an example, and table 2 is an example of a check matrix, the check matrix can be determined by querying table 2 below.

In Table 2, column 1 and column 2 are the row index and column index, respectively, of the non-zero element, which can be used as the information of the base graph, hereIs represented by H_BG. Wherein for each set indexi_LSEach non-zero element has a corresponding value V_i,j. Shift the factor P accordingly_i,j＝mod(V_i,j,Z)。

TABLE 2

Here, the check matrix is determined by referring to table 2 according to the index corresponding to Z.

Continuing with the example of Z being 72, 72 corresponds to an index of 5.

To obtain the check matrix corresponding to Z72, the index in table 2 needs to be 5 (i.e., Set index i in table 2)_LS5) each element of the corresponding matrix is modulo 72. That is, the shift factor P in the check matrix corresponding to Z72_i,jIs mod (V)_i,j72) in which V_i,jIs the value of the non-zero element in the ith row and the jth column in the matrix with the index of 5. V_i,jThe remainder obtained by complementation with 72 is Z-72 pairsThe shift factor of the corresponding cyclic shift matrix of the non-zero elements. In one possible implementation, each non-zero element may be replaced by a cyclic shift matrix of Z × Z size to obtain a check matrix, where each cyclic shift matrix is obtained by cyclic shifting the identity matrix I according to the shift factor of the non-zero element at the position.

(4) And coding according to the check matrix.

The above describes the prior art process for determining the check matrix of QC-LDPC. When the spreading factor Z of the check matrix is determined, it is mainly considered that a Block Error Rate (BLER) is equal to 10^-2The performance of the BLER at other values is not considered, and therefore, an error floor occurs at some positions, which affects the decoding performance.

Fig. 3 is a graph comparing the performance of the LDPC code with the polarization code when K is 94 and N is 420. Referring to FIG. 3, LDPC has a BLER of less than 10 in comparison to a Polar code (i.e., Polar code)^-4A more pronounced error floor occurs. Where N is the encoded length.

Fig. 3 is a graph of BLER obtained by iterating 20 times according to the BG2 matrix and the (Layered Offset Min-Sum, LOMS) decoding algorithm.

The BG2 matrix is the matrix H defined in Table 2 above_BG。

The LOMS decoding algorithm is one of decoding algorithms of LDPC. Currently, the decoding Algorithm of the LDPC code is evolved based on a Message Passing Algorithm (Message Passing Algorithm), which is also called a Belief Propagation Algorithm (Belief Propagation Algorithm). The LOMS decoding algorithm is a variant of the message passing algorithm and is characterized by iterative computations between check nodes and bit nodes (also called variable nodes). For the details of the LOMS algorithm and the check node and bit node, reference is made to the prior art and no further details are given here.

It is known to those skilled in the art that when studying the frame error rate and/or bit error rate of LDPC, one can analyze the performance at different signal-to-noise ratios. The decoding performance curve is typically divided into two regions: a low/medium signal-to-noise ratio region and a high signal-to-noise ratio region. In the low/medium signal-to-noise ratio region, the decisive factor for causing the error code is that the signal-to-noise ratio is too low, and the error rate is high because the signal strength is not enough and a large number of error bits occur. In the high snr region, the signal strength is high enough, and decoding failure still occurs mainly due to trapping. The concept of trapping can be referred to in the art and will not be described in detail herein.

Error floor refers to the sudden drop in the error performance curve from the low/medium channel ratio waterfall region to the high signal-to-noise ratio region.

In some systems where the bit error rate is required to be extremely low, such as data storage and optical communication systems, the bit error rate is required to be 10^-12～10^-15The following. Therefore, how to reduce the error floor of the LDPC code is one of the key issues of LDPC in practical applications.

Therefore, the application provides an information processing method, and the LDPC constructed by the method is beneficial to reducing error layers in the decoding process so as to improve the decoding performance of the LDPC.

Referring to fig. 4, fig. 4 is a schematic flow chart of a method 200 of processing information according to an embodiment of the present application. Method 200 may be performed by a sender of information and/or data. The sender of information and/or data may also be considered the encoder. For example, by the terminal device 102 in the uplink transmission scenario shown in fig. 1. Also for example, it may be performed by the network device 101 in the downstream transmission scenario shown in fig. 1.

The

main steps

210 and 230 of the method 200 of the embodiment of the present application are described in detail below.

210. A first spreading factor and a correction value for the first spreading factor are determined.

The first spreading factor herein refers to the spreading factor of the check matrix of LDPC, i.e., the spreading factor Z described above.

In the embodiment of the present application, whether the first spreading factor needs to be modified may be determined according to the length K of the information sequence.

For ease of understanding and distinction, the spreading factor before modification will be referred to as a first spreading factor and the spreading factor after modification will be referred to as a second spreading factor hereinafter.

Through performance simulation, it can be found that at some given error rate BLER, the length K of the information sequence has an error floor at some values, and the spreading factor corresponding to the length K of the information sequence can be corrected.

There are several ways to determine whether an error floor exists for the length K of the information sequence at a given BLER. Only two examples are given herein.

Referring to fig. 5, fig. 5 is a schematic diagram of BLER, which is obtained by using BG2 matrix in NR and LOMS algorithm as an example. In fig. 5, a method for determining whether or not an error floor exists at BLER-1 e-5 and BLER-1 e-6 is given by taking K-96 and N-420 as an example, as described in manner 1 below.

Mode 1

And judging whether an error floor exists according to the slope of the curve and a preset judgment threshold value.

In mode 1, first, three-stage curve slopes K1, K2, and K3 are defined. Where K1 is the slope of BLER-1 e-2 to BLER-1 e-3. K2 is the slope of BLER-1 e-4 to BLER-1 e-5. K3 is the slope of BLER-1 e-5 to BLER-1 e-6.

And comparing the change of the slopes with a preset judgment threshold value to judge whether an error floor exists or not.

Specifically, these changes in slope are compared with a preset decision threshold value. And if the change of the slope is greater than or equal to a preset judgment threshold value, determining that an error floor exists. And if the change of the slope is smaller than a preset judgment threshold value, determining that no error floor exists.

Further, the decision threshold value is an integer greater than 1, e.g., 1.1, 1.2, 1.3, 1.4, 1.5, etc. Wherein, the judgment threshold value is set according to the severity of the judgment. If the judgment on the wrong leveling layer is relatively strict, the judgment threshold value can be set to be a higher point, and if the judgment on the wrong leveling layer is relatively loose, the judgment threshold value can be set to be a lower point.

It should be noted that whether an error floor exists in the length K of the information sequence is for a certain BLER. In other words, it is determined whether there is an error floor for the length K of the information sequence, i.e. whether there is an error floor for the length K of the information sequence at a certain BLER.

For example, if it is to be determined whether K96 has an error floor at BLER 1e-5, then it is determined whether K1/K2 ≧ decision threshold value 1 holds. If K1/K2 is larger than or equal to the decision threshold value 1, then K96 is considered to have an error floor at BLER 1 e-5.

For another example, if it is to be determined whether K96 has an error floor at BLER 1e-6, then it is determined whether K1/K3 ≧ decision threshold 2 holds. If K1/K3 is larger than or equal to the decision threshold value 2, it is considered that K96 has an error floor at BLER 1 e-6.

The length K of the information sequence counted according to the method in mode 1 is given below as [40,48, 5664, 72,80,88,96,104,112,120,128,136,144,152,160,168,176,184,192,200,208,224,240,256,272,288,304,320,336,352,368,384,400,424,448,472,496,520,544,568,592,624,656,688,720,752,784, 864,904,944,1000,1048,1080,1144,1176,1208,1240,1272,1304,1336,1368, 2611432, 1496, 1490, 1624,1688,1752,1816,1880,1944,2040,2104,2168,2232,2296,2424,2488,2552,2616,2680, 278, 2872, 2924, 2872, 2942, 363882, 2/3, 363, 364, 362, 2/3, 3627, 362, 3676, 3638, 3676, and 3638, 2/3.

Table 3 is the statistical result of the error floor at decision threshold value 1.5 and BLER equal to 1 e-5. Table 4 is the statistical result of the error floor at decision threshold value 1.1 and BLER equal to 1 e-6.

Where 0 in the table indicates no error floor and 1 in the table indicates the presence of an error floor.

TABLE 3

TABLE 4

The statistical results of the error floor at 1e-5 with the decision threshold value 1.1 and BLER are given in table 5 below. The statistical results of the error floor at 1e-5 with the decision threshold value 1.1 and BLER are given in table 6 below.

TABLE 5

TABLE 6

Mode 2

And judging whether an error flat layer exists according to the performance curve.

Referring to fig. 6, fig. 6 is an example of determining whether a false floor exists based on a performance curve. Fig. 6 shows a graph of the required Signal-to-Noise Ratio (SNR) when K is 96, BLER is 1e-1, and the code rates R are 0.67, 0.5, 0.33, 0.17, 0.13, and 0.08, respectively. The spike in fig. 5 means that an error floor has occurred. These error floors can be skipped by correcting the spreading factor corresponding to the peak position. Specifically, the performance curve corresponding to each code rate may be fitted. The raw data is then compared with the fitted data for differences. And if the difference value exceeds a preset judgment threshold value, determining that a wrong leveling layer exists.

Fig. 7 to 11 show graphs of Signal to Noise ratios (SNR) required when K is 96, BLER is 1e-2, 1e-3, 1e-4, 1e-5, 1e-6, and code rate R is 0.67, 0.5, 0.33, 0.17, 0.13, and 0.08, respectively. The method for determining whether there is an error floor is similar to that in fig. 5, and is not described in detail here.

It should be noted that the performance curves in fig. 5-11 are simulated in an Additive White Gaussian Noise channel (AWGN) environment.

In addition, the length K of the information sequence in fig. 6 to 11 includes check bits. As shown in fig. 6-11, the check bits are 24 bits. Such as the 24-CRC shown in fig. 6. Here, CRC denotes a Cyclic Redundancy Check (Cyclic Redundancy Check).

It should be understood that the above manner 1 and manner 2 are only examples for determining whether an error floor exists, and those skilled in the art can also determine whether an error floor exists at a given BLER according to other methods for determining an error floor, and the present application is not limited thereto.

It is understood that it is not absolute whether the length K of the information sequence has an error floor at a given BLER. For example, the dependency of the decision threshold values on the severity of the decision error floor has been described above. Therefore, whether an error floor exists at a certain BLER for the length K of the information sequence is related to the magnitude of the set decision threshold. Alternatively, other methods of determining whether a false floor exists may be used depending on other factors. Therefore, the present application is not limited to the method of determining the error floor. In other words, any method for determining the error floor can be adopted, and in the case of the error floor, the spreading factor of the check matrix can be corrected by using the method of the present application, so as to reduce the error floor as much as possible.

As an alternative embodiment, the transmitting end may determine the first spreading factor through the procedure of determining the spreading factor of the check matrix in the NR described above. I.e. the first spreading factor is determined on the basis of the length K of the information sequence.

The correction value for the first spreading factor may be related to the length of the information sequence. Alternatively, the length K of the information sequence and the code rate R may be related to each other. In one possible implementation, the correction value for the first spreading factor may be determined by means of a table look-up.

Alternatively, at least one of the following table 7 may be satisfied between K and the correction value of the first spreading factor. Correcting the first spreading factor according to the correction value of the first spreading factor given in table 7 can eliminate the error floor that occurs at BLER-1 e-5 when the information sequence K <400 (e.g., K96, 152, 176, etc.) in table 5.

TABLE 7

Alternatively, at least one of the following table 8 may be satisfied between K and the correction value of the first spreading factor. By correcting the first spreading factor according to the correction value of the first spreading factor given in table 8, it is possible to eliminate the error floor that occurs at BLER 1e-6 when the information sequence K <400 (e.g., K96, 152, 176, etc.) in table 6.

TABLE 8

It can be seen that tables 7 and 8 are mainly modified for the length K of the information sequence. Further, to achieve a finer adjustment, the first spreading factor may be corrected in conjunction with the code rate R with reference to tables 7 and 8, instead of correcting for only the K pair.

TABLE 9

Those skilled in the art will appreciate that 6 values of the code rate R are given in table 9, but this is only an example. In the encoding process, if the actually used code rate is not equal to any of the 6 values given in table 9, other methods may be used to determine the correction value of the first spreading factor.

As is well known, the code rate R has a value of 0< R <1, and thus, the 6 code rates shown in table 9 can divide the interval (0,1) into 6 intervals, and each interval corresponds to one correction value. In this way, the first spreading factor is corrected by using the correction value corresponding to the interval according to which interval the actually used code rate falls in. See table 10.

Watch 10

220. And determining a check matrix according to the first expansion factor and the corrected value of the first expansion factor.

After the first spreading factor and the correction value of the first spreading factor are respectively determined in the combining step 210, the first spreading factor is corrected by using the correction value of the first spreading factor, so as to obtain a corrected spreading factor. For example, the first spreading factor may be added to the correction value to obtain a corrected spreading factor. Alternatively, other correction methods are also possible.

Next, a check matrix is determined using the second spreading factor.

The process of determining the check matrix according to the second spreading factor is the same as the process of step (3) in the procedure of determining the check matrix according to the spreading factor Z in NR described above by referring to table 2. For the avoidance of redundancy, this is not described in detail here.

It should be noted that, if the second spreading factor obtained after correcting the first spreading factor does not belong to table 1, the remainder operation may be directly performed on the value of the second spreading factor to determine the check matrix.

230. The information sequence is encoded using a check matrix.

Step 240 can be found in the prior art and will not be described in detail herein.

Subsequently, the sending end may send the encoded codeword to the receiving end.

And the receiving end receives the sequence to be decoded and determines a check matrix H by using the same method as the transmitting end. And finally, the receiving end decodes the sequence to be decoded by using the check matrix to obtain a decoded sequence.

The encoding method of the embodiment of the application can skip the position of the error flat layer when determining the expansion factor Z of the check matrix, thereby improving the decoding performance.

It should be noted that skipping the position with the error floor merely increases the number of punctured bits (puncturing bits) in the check matrix without other influence, so that there is no other performance loss.

The encoding method according to the embodiment of the present application is explained in detail above, and the encoding apparatus according to the embodiment of the present application is explained below with reference to fig. 12 and 13.

Fig. 12 is a schematic block diagram of an apparatus 600 for processing information according to an embodiment of the present application. The apparatus 600 mainly comprises a processing unit 610 and a transmitting unit 620. Wherein the processing unit 610 is configured to:

determining a first spreading factor and a correction value for the first spreading factor;

determining a check matrix according to the first expansion factor and the correction value of the first expansion factor;

and encoding the information sequence with the length of K by using the check matrix, wherein K is a positive integer.

Further, the sending unit 620 is configured to send the encoded codeword.

It should be understood that the processing unit 610, when used for encoding, may also be referred to as an encoding unit.

Each unit and the other operations or functions described above in the apparatus 600 of the embodiment of the present application are respectively for realizing the method of processing information of the embodiment of the present application. For brevity, no further description is provided herein.

In one possible design, when part or all of the functions of the apparatus 600 are implemented by hardware, the apparatus 600 includes: an input interface circuit for obtaining an information sequence; the logic circuit is used for determining a first spreading factor and a correction value of the first spreading factor, determining a check matrix according to the first spreading factor and the correction value, and encoding an information sequence with the length of K according to the check matrix, wherein K is a positive integer; and the output interface circuit is used for outputting the coded code words.

In one possible design, when the above functions of apparatus 600 are all implemented by hardware, apparatus 600 includes: a memory for storing a program; a processor for executing the program stored in the memory, and when the program is executed, the apparatus 600 may implement the method for processing information as described in any of the above possible designs.

Alternatively, the apparatus 600 may be a chip or an integrated circuit.

In one possible design, when some or all of the above-described functionality of apparatus 600 is implemented in software, apparatus 600 includes a processor and memory. The processor implements the above-described functions of the apparatus 800 by reading stored software code in the memory. The memory and the storage may be physically separate units, or the memory and the processor may be integrated together.

Fig. 13 is a schematic structural diagram of an apparatus 700 for processing information according to an embodiment of the present application. As shown in fig. 13, the apparatus 700 includes: one or more processors 701, and one or more memories 702. Optionally, the device 700 may also include one or more transceivers 703. The processor 701 is configured to control the transceiver 703 to send and receive signals, the memory 702 is configured to store a computer program, and the processor 701 is configured to call and execute the computer program from the memory 702, so that the apparatus 700 performs the corresponding procedures and/or operations of processing information according to the embodiments of the present application. And will not be described in detail herein.

It should be noted that the apparatus 600 shown in fig. 12 can be implemented by the device 700 shown in fig. 13. For example, the processing unit 610 may be implemented by the processor 701, the transmitting unit 620 may be implemented by the transceiver 703, and the like.

Furthermore, the present application provides a computer-readable storage medium having stored therein computer instructions which, when run on a computer, cause the computer to perform the method of processing information described in any one of the embodiments of the present application.

The present application also provides a computer program product comprising computer program code which, when run on a computer, causes the computer to perform a method of processing information as described in any of the embodiments of the present application.

The present application also provides a chip (or a chip system) including a memory and a processor, where the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that a communication device installed with the chip executes the method for processing information in the embodiments of the present application.

The communication device described herein may be the sender or the encoder of information. For example, in uplink transmission, a terminal device is equipped with the chip to encode an information sequence, such as the terminal device 102 shown in fig. 1. In the downstream transmission, the network device 101 is equipped with the chip to encode the information sequence.

In addition, the application also provides a device 800 for processing information. Referring to fig. 14, fig. 14 is a schematic block diagram of an apparatus 800 for processing information according to an embodiment of the present application. The apparatus 800 mainly comprises a receiving unit 810 and a processing unit 820. The receiving unit 810 is configured to receive a sequence to be decoded. The processing unit 820 is configured to determine a first spreading factor and a correction value for the first spreading factor; determining a check matrix according to the first expansion factor and the correction value of the first expansion factor; and decoding the sequence to be decoded by using the check matrix.

When the processing unit 820 is used for decoding, it may also be referred to as a decoding unit (or a decoding unit).

The apparatus 800 may be a receiving end or a decoding end of information. Taking fig. 1 as an example, during uplink transmission, the apparatus 800 may be a network device 101, and decode information (or a sequence to be decoded) received from a terminal device 102. In downlink transmission, the apparatus 800 may be a terminal device 103, and decode information received from the network device 101.

In one possible design, when part or all of the described functions of the apparatus 800 are implemented by hardware, the apparatus 800 may be a logic circuit, an integrated circuit, or the like. For example, the apparatus 800 includes: the input interface circuit is used for acquiring a sequence to be decoded; the logic circuit is used for determining a first spreading factor and a correction value of the first spreading factor, determining a check matrix according to the first spreading factor and the correction value, and decoding the sequence to be decoded according to the check matrix; and the output interface circuit is used for outputting the decoded sequence.

In one possible design, when the above functions of the apparatus 800 are all implemented by hardware, the apparatus 800 includes: a memory for storing a program; a processor configured to execute the program stored in the memory, and when the program is executed, the apparatus 800 may implement a procedure for decoding a sequence to be decoded.

Alternatively, the apparatus 800 may be a chip or an integrated circuit.

In one possible design, when some or all of the above-described functionality of the apparatus 800 is implemented in software, the apparatus 800 includes a processor and a memory. The processor implements the above-described functions of the apparatus 800 by reading stored software code in the memory. The memory may be integrated within the processor or may be external to the processor.

Fig. 15 is a schematic configuration diagram of an apparatus 900 for processing information according to an embodiment of the present application. As shown in fig. 15, the apparatus 900 includes: one or more processors 901, and one or more memories 902. Optionally, the device 900 may also include one or more transceivers 903. The processor 901 is configured to control the transceiver 903 to transmit and receive signals, the memory 902 is configured to store a computer program, and the processor 901 is configured to call and run the computer program from the memory 902, so that the apparatus 900 executes corresponding procedures and/or operations for decoding a sequence to be decoded. And will not be described in detail herein.

It should be noted that the apparatus 800 shown in fig. 14 can be implemented by the device 900 shown in fig. 15. For example, the receiving unit 810 may be implemented by the transceiver 903, the processing unit 820 may be implemented by the processor 901, and the like.

In addition, the present application provides a computer-readable storage medium, in which computer instructions are stored, and when the computer instructions are executed on a computer, the computer is caused to execute corresponding procedures and/or operations for decoding a sequence to be decoded in the embodiments of the present application.

The present application further provides a computer program product, which includes computer program code, when the computer program code runs on a computer, the computer is caused to execute the corresponding procedures and/or operations for decoding the sequence to be decoded in the embodiments of the present application.

The present application further provides a chip (or, a chip system) including a memory and a processor, where the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that a communication device in which the chip is installed executes a corresponding process and/or operation for decoding a sequence to be decoded in the embodiment of the present application.

The communication device described herein may be the receiving end or the decoding end of the information. For example, in the upstream transmission, the network device 101 is mounted with the chip. In the downlink transmission, the terminal device 103 is equipped with the chip.

In the above embodiments, the processor may be a Central Processing Unit (CPU), a microprocessor, an Application-Specific Integrated Circuit (ASIC), or one or more Integrated circuits for controlling the execution of the program in the present Application. For example, a processor may be comprised of a digital signal processor device, a microprocessor device, an analog to digital converter, a digital to analog converter, and so forth. The processor may distribute the control and signal processing functions of the mobile device between these devices according to their respective functions. Further, the processor may include functionality to operate one or more software programs, which may be stored in the memory. The functions of the processor can be realized by hardware, and can also be realized by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above functions.

The Memory may be a Read-Only Memory (ROM) or other type of static storage device that may store static information and instructions, a Random Access Memory (RAM) or other type of dynamic storage device that may store information and instructions. But is not limited to, Electrically Erasable Programmable Read-Only Memory (EEPROM), Compact Disc Read-Only Memory (CD-ROM) or other optical disk storage, optical disk storage (including Compact Disc, laser disk, optical disk, digital versatile disk, blu-ray disk, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a U disk, a removable hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method of processing information, comprising:

determining a check matrix according to the first expansion factor and the correction value;

encoding an information sequence with the length of K by using the check matrix, wherein the K is a positive integer;

wherein the correction values for K and the first spreading factor satisfy at least one of the following tables:

；

Or, the K and the correction value of the first spreading factor satisfy at least one of the following tables:

。

2. The method of claim 1, wherein determining the correction value for the first expansion factor comprises:

and determining the correction value of the first expansion factor according to the K and the code rate R.

3. The method according to claim 2, wherein the K, the correction value for the first spreading factor and the code rate R satisfy at least one of the following tables:

4. an apparatus for processing information, comprising:

a processing unit for determining a first spreading factor and a correction value for the first spreading factor;

the processing unit is further used for determining a check matrix according to the first expansion factor and the correction value;

the processing unit is further configured to encode an information sequence with a length of K using the check matrix, where K is a positive integer;

；

。

5. The apparatus according to claim 4, wherein the processing unit is specifically configured to determine the correction value for the first spreading factor based on the K and a code rate R.

6. The apparatus of claim 5, wherein the K, the correction value for the first spreading factor, and the code rate R satisfy at least one of the following tables:

7. a terminal, characterized in that it comprises the apparatus according to any one of claims 4 to 6.

8. A base station, characterized in that it comprises the apparatus according to any of claims 4 to 6.

9. A communication system comprising a terminal according to claim 7 and a base station according to claim 8.

10. A computer-readable storage medium comprising instructions that, when executed on a computer, cause the computer to perform the method of any of claims 1 to 3.