CN109994476B

CN109994476B - Method for preparing magnetic random access memory array unit

Info

Publication number: CN109994476B
Application number: CN201711474396.3A
Authority: CN
Inventors: 张云森
Original assignee: Shanghai Ciyu Information Technologies Co Ltd
Current assignee: Shanghai Ciyu Information Technologies Co Ltd
Priority date: 2017-12-29
Filing date: 2017-12-29
Publication date: 2021-03-16
Anticipated expiration: 2037-12-29
Also published as: CN109994476A

Abstract

The invention provides a method for preparing a magnetic random access memory array unit, which is characterized in that a bit line through hole etching barrier layer is inserted between magnetic tunnel junction dielectrics, so that the bit line through hole etching barrier layer can block main etching in a subsequent bit line through hole etching process and provides a main etching endpoint optical emission spectrum judgment signal; and then selecting an over-etching process with lower etching rate and higher selection ratio to etch the residual dielectric and the covering layer. The invention effectively avoids the over-etching of the dielectric protective layer around the hard mask and the magnetic tunnel junction in the final phase of the bit line through hole etching, thereby avoiding the short circuit of the whole magnetic random access memory array unit circuit.

Description

Method for preparing magnetic random access memory array unit

Technical Field

The invention relates to a method for preparing a Magnetic Random Access Memory (MRAM) array unit, belonging to the technical field of manufacturing of MRAM.

Background

In recent years, MRAM using Magnetic Tunnel Junction (MTJ) is considered as a future solid-state nonvolatile memory, which has features of high speed read and write, large capacity, and low power consumption. Ferromagnetic MTJs are typically sandwich structures with a magnetic memory layer that can change the magnetization direction to record different data; an insulating tunnel barrier layer in between; and the magnetic reference layer is positioned on the other side of the tunnel barrier layer, and the magnetization direction of the magnetic reference layer is unchanged.

In order to be able to record information in such a magnetoresistive element, a writing method based on Spin momentum Transfer (STT) switching technology has been proposed, and such an MRAM is called STT-MRAM. STT-MRAM is further classified into in-plane STT-MRAM and perpendicular STT-MRAM (i.e., pSTT-MRAM), which have better performance depending on the direction of magnetic polarization. In this way, the magnetization direction of the magnetic memory layer can be reversed by supplying a spin-polarized current to the magnetoresistive element. In addition, as the volume of the magnetic memory layer is reduced, the smaller the spin-polarized current to be injected for writing or switching operation. Therefore, this writing method can achieve both device miniaturization and current reduction.

Meanwhile, the pSTT-MRAM can be well matched with the most advanced technology node in terms of scale, because the required switching current is reduced when the size of the MTJ element is reduced. It is therefore desirable to make the pSTT-MRAM device extremely small in size, with very good uniformity, and with minimal impact on the MTJ magnetic properties, by a fabrication method that also achieves high yield, high accuracy, high reliability, low power consumption, and maintains a temperature coefficient suitable for good data storage. Meanwhile, the write operation in the nonvolatile memory is based on the resistance state change, so that it is necessary to control the damage and shortening of the life of the MTJ memory device caused thereby. However, the fabrication of a small MTJ device may increase the fluctuation of MTJ resistance, so that the write voltage or current of pSTT-MRAM may fluctuate greatly, which may impair the performance of MRAM.

In the current MRAM manufacturing process, the connection between the Magnetic Tunnel Junction (MTJ) and the Bit Line (Bit Line) is usually implemented by directly connecting a Bit Line Via (BLV, Bit Line Via) and a Top Electrode (TE, Top Electrode) formed at one time with the magnetic tunnel junction; however, when the BLV is fabricated by etching, an etching barrier layer of the BLV is generally used as a capping layer deposited immediately after the Magnetic Tunnel Junction (MTJ) etching; in such a structure, the capping layer is often insufficient to block ion bombardment in the main etch step of the BLV, which will cause direct communication between the Bottom (BE) and Top (TE) electrodes of the magnetic tunnel junction, as shown in fig. 1, thereby rendering the entire device useless. This phenomenon is more pronounced if the alignment of the BLV and the magnetic tunnel junction pattern is not very precise.

Disclosure of Invention

In order to solve the above technical problems, the present invention provides a method for fabricating a magnetic random access memory array cell. A bit line through hole (BLV) etching barrier layer is inserted in the magnetic tunnel junction dielectric medium to prevent the main etching in the subsequent bit line through hole etching process and provide an Optical Emission Spectroscopy (OES) judgment signal of a main etching endpoint; and then selecting an over-etching process with lower etching rate and higher selection ratio to etch the residual dielectric and the covering layer. The specific technical scheme is as follows:

the first scheme comprises the following steps:

providing a surface-polished CMOS substrate with a metal through hole, and depositing a bottom electrode metal layer, a magnetic tunnel junction multilayer film and a top electrode film layer on the substrate;

patterning the magnetic tunnel junction pattern, etching the multilayer film of the magnetic tunnel junction to form a magnetic tunnel junction, etching the metal layer of the bottom electrode to form a bottom electrode, and covering the magnetic tunnel junction and the bottom electrode with a first covering layer;

depositing a first dielectric layer, a bit line through hole etching barrier layer and a second dielectric layer on the first covering layer in sequence, then flattening the second dielectric layer, and then depositing a second covering layer on the second dielectric layer;

and step four, etching to form a bit line through hole, and filling metal copper in the bit line through hole.

Further, the first covering layer is made of SiC, SiN or SiCN, and is formed by chemical vapor deposition, atomic layer deposition or ion beam deposition.

Furthermore, the total thickness of the four layers of the first dielectric layer, the bit line through hole etching barrier layer, the second dielectric layer and the second covering layer is 120 nm-400 nm.

Further, the first dielectric layer and the second dielectric layer are SiO₂SiON or a low dielectric constant dielectric.

Further, the bit line through hole etching barrier layer is made of SiC, SiN or SiCN, is covered on the first dielectric layer in a shape-preserving mode through chemical vapor deposition or atomic layer deposition, and is 10 nm-50 nm thick.

Further, the second covering layer is SiO₂And forming a second covering layer by using chemical vapor deposition.

Further, in the main etching step of etching to form the bit line through hole, C is adopted₄F₈Or C₄F₆As the main etch gas. And (3) taking an optical emission spectrum signal of CN or CO as an etching end point signal for judging the main etching step. And after the main etching step is finished, selecting main etching gas with low C/F content, sequentially etching the bit line through hole etching barrier layer, the first dielectric layer and the first covering layer, and stopping on the top electrode film layer.

The second scheme comprises the following steps:

depositing a first dielectric layer on the first covering layer, flattening the first dielectric layer, and then sequentially depositing a bit line through hole etching barrier layer, a second dielectric layer and a second covering layer on the first dielectric layer;

The invention has the beneficial effects that: the invention effectively avoids the over-etching of the dielectric protective layer around the hard mask and the magnetic tunnel junction in the final phase of the bit line through hole etching, thereby avoiding the short circuit of the whole magnetic random access memory array unit circuit.

Drawings

A more complete understanding of the present invention, and the attendant advantages and features thereof, will be more readily understood by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein:

FIG. 1 is a schematic diagram of a magnetic tunnel junction bottom electrode in direct communication with a top electrode under prior art conditions;

FIG. 2(a) is a schematic view of a substrate in accordance with a preferred embodiment of the present invention;

FIG. 2(b) is a schematic diagram of a bottom electrode metal layer deposited on a substrate according to a preferred embodiment of the present invention;

FIG. 3 is a schematic diagram of a magnetic tunnel junction and a first cladding layer in a preferred embodiment of the invention;

FIGS. 4(a) to 4(c) are schematic diagrams illustrating the formation of bit line vias by etching according to a preferred embodiment of the present invention;

FIGS. 5(a) to 5(c) are schematic diagrams illustrating the formation of bit line vias by etching according to another preferred embodiment of the present invention;

description of reference numerals: 100-surface polished metal through-hole (V)_x(x>1), 101-CMOS dielectric, 102-CMOS dielectric, 1)03-CMOS via metal diffusion barrier, 104-CMOS via metal, 201-bottom electrode metal, 202-magnetic tunnel junction multilayer film, 203-top electrode film (hard mask layer), 204-first capping layer, 205-first dielectric layer, 206-Bit Line Via (BLV) etch barrier, 207-second dielectric layer, 208-second capping layer, 301-Bit Line Via (BLV), 302-Bit Line Via (BLV) metal diffusion barrier, 303-Bit Line Via (BLV) metal.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. It is to be noted that the drawings are in simplified form and are not to precise scale, which is provided for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

The present invention includes, but is not limited to, the fabrication of Magnetic Random Access Memories (MRAMs), and is not limited to any process sequence or flow, as long as the resulting product or device is prepared by the same or similar method as that prepared by the following preferred process sequence or flow, with the following specific steps:

example 1:

the method comprises the following steps: through-metal vias (V) providing surface polishing_x(x>1) as shown in fig. 2 (a); and depositing a bottom electrode metal layer 201, a magnetic tunnel junction multilayer film 202, and a top electrode film layer 203 thereon, as shown in fig. 2 (b); the material of the CMOS via is typically Cu or W. The bottom electrode metal layer 201 includes Ta, TaN, Ti, TiN, W, WN, or the like, has a thickness in a range of 20nm to 80nm, and is generally implemented by Physical Vapor Deposition (PVD) or the like. Further, it may be subjected to a surface planarization process in order to improve its surface flatness.

The total thickness of the Magnetic Tunnel Junction (MTJ) multilayer film 202 is 15nm to 40nm, and may be a Bottom Pinned structure formed by sequentially stacking a reference layer, a barrier layer, and a memory layer upward, or a Top Pinned structure formed by sequentially stacking a memory layer, a barrier layer, and a reference layer upward.

Further, the reference layer has a magnetic polarizationDenaturation, which differs depending on whether it is an in-plane (iST-MRAM) or perpendicular (pSTT-MRAM) structure. The reference layer of in-plane (iSTT-MRAM) typically has a (IrMn or PtMn)/CoFe/Ru/CoFe/CoFeB structure with a preferred total thickness of 10-30 nm; the reference layer of the vertical type (pSTT-MRAM) typically has TbCoFe or [ Co/Pt ]]/Co/Ru/[CoPt]/CoFeB_mThe superlattice multilayer film structure usually needs a seed layer, such as Ta/Pt, on the lower surface, and the total thickness of the reference layer is preferably 8-20 nm.

Further, the barrier layer is a non-magnetic metal oxide, preferably MgO or Al₂O₃The thickness is 0.5 nm-3 nm. Further, the barrier layer may adopt a double-layered MgO structure.

Further, the memory layer has a variable magnetic polarization, which differs depending on whether it is an in-plane (iST-MRAM) or perpendicular (pSTT-MRAM) structure. The memory layer of the in-plane iSTT-MRAM is generally CoFe/CoFeB or CoFe/NiFe, and the thickness is preferably 2nm to 6nm, and the memory layer of the vertical pSTT-MRAM is generally CoFeB, CoFe/CoFeB, Fe/CoFeB, CoFeB (Ta, W, Mo)/CoFeB, and the thickness is preferably 0.8nm to 2 nm.

Generally, an ultra-thin seed layer is typically deposited before the deposition of the magnetic tunnel junction multilayer film 202 to obtain better growth of the magnetic tunnel junction multilayer film 202.

The top electrode layer (hard mask layer) 203 has a thickness of 20nm to 100nm, and Ta, TaN, W, WN, etc. are selected to obtain a better profile in the halogen plasma.

Step two: the magnetic tunnel junction pattern is patterned and etched and the etched magnetic tunnel junction is immediately covered with a first capping layer 204, as shown in fig. 3.

The step is to define the pattern of the magnetic tunnel junction graphically, etch the top electrode film layer (hard mask layer) 203, the multilayer film 202 of the magnetic tunnel junction and the bottom electrode metal layer 201, and keep a certain over-etching to effectively separate the magnetic tunnel junction, and then deposit the first cover layer 204.

In this process, the magnetic tunnel junction is defined and the top electrode film layer 203 is subjected to Reactive Ion Etching (RIE) by using a single lithography and single etching (LE) or two lithography and single etching (LELE), and the residual polymer is removed by using a reactive ion etching or wet process, so that the magnetic tunnel junction pattern is transferred to the top of the magnetic tunnel junction.

The Etching of the Magnetic Tunnel Junction (MTJ) multilayer film 202 and the bottom electrode metal layer 201 is completed by adopting a Reactive Ion Etching (RIE) method and/or an Ion Beam Etching (IBE) method, and a certain over-Etching is maintained; finally, a Magnetic Tunnel Junction (MTJ) array cell is formed in the storage region.

Wherein, IBE mainly adopts Ar, Kr or Xe and the like as an ion source; RIE mainly uses CH₃OH、CH₄/Ar、 C₂H₅OH、CH₃OH/Ar or CO/NH₃Etc. as the main etching gas; fluorine-containing gas can be selected as the main gas in the over-etching step, so that the bottom electrodes of different magnetic tunnel junctions are effectively isolated.

The first capping Layer 204 is made of SiC, SiN, or SiCN, and the forming method thereof can be implemented by Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or Ion Beam Deposition (IBD).

Step three: a first dielectric layer 205, a Bit Line Via (BLV) etch stop layer 206, and a second dielectric layer 207 are deposited in sequence, and the top of the second dielectric layer 207 is planarized, followed by the deposition of a second capping layer 208, as shown in fig. 4 (a). The total thickness of the four layers is controlled to be 120 nm-400 nm. Wherein the first dielectric layer 205 and the second dielectric layer 207 are SiO₂Materials such as SiON or low dielectric constant (low-k) dielectrics.

The low dielectric constant (low-k) dielectric refers to a material having a dielectric constant (k) lower than that of silicon dioxide (k is 3.9), and in practice, the low-k material may be a hydrosilicate (HSQ, k is 2.8-3.0) containing Si — CH₃Functional group-containing methylsilicates (MSQ, k ═ 2.5-2.7), synthetic hydrosilicates HSQ and methyl-containing methylHybrid organosiloxane Polymer (HOSP) films (k 2.5) and porous SiOCH films (k 2.3-2.7) synthesized from the silicates MSQ, and even ultra-low dielectric constants (k) can be used<2.0) Porous Silicate, and a Porous SiOCH film having a dielectric constant (k) of 1.9.

The Bit Line Via (BLV) etch stop Layer 206 is typically SiC, SiN, or SiCN, and is conformally deposited on the first dielectric Layer 205 by Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD), wherein the thickness of the Bit Line Via (BLV) etch stop Layer 206 is 10nm to 50 nm. The second cap layer 208 is typically a high density SiO₂And depositing by using a CVD (chemical vapor deposition) process. The Planarization method generally employs Chemical Mechanical Planarization (CMP).

Step four: etching the magnetic tunnel junction Bit Line Via (BLV) and performing metallic copper filling, as shown in fig. 4(b) and 4 (c); the method comprises the following steps:

step 4.1: the Bit Line Via (BLV)301 is defined graphically and formed by an etching process, typically using a high C/F content gas (e.g., C/F) in the main etching step₄F₈Or C₄F₆Etc.) as the main etching gas; OES signals of CN (387nm) or CO (520nm) and the like are used as etching end point signals for judging the main etching step, then, main etching gas with low C/F content is selected to etch the bit line through hole etching barrier layer 206, the first dielectric layer 205 and the first covering layer 204 in sequence, technological parameters and gas components are accurately controlled, the etching rate is reduced to a reasonable range, and high SiO is formed₂the/SiN etch selectivity, as shown in FIG. 4 (b); after the etching is completed, a cleaning process is used to remove the remaining polymer and the like.

Step 4.2: fill the bit line via metal 303 and polish it down using Chemical Mechanical Polishing (CMP), as shown in fig. 4 (c); wherein a bit line via metal diffusion barrier layer 302(Ti/TiN or Ta/TaN) and a copper seed layer are typically deposited in advance before Electroplating (ECP) copper.

Example 2:

step one, step two: respectively carrying out the same steps as the first step and the second step in the embodiment 1;

step three: a first dielectric layer 205 is deposited in sequence and aligned planarized, followed by deposition of a Bit Line Via (BLV) etch stop layer 206, a second dielectric layer 207 and a second capping layer 208, as shown in fig. 5 (a). Wherein the total thickness of the four layers is controlled to be 120 nm-400 nm; the first dielectric layer 205 and the second dielectric layer 207 are SiO₂Materials such as SiON or low-k, the Bit Line Via (BLV) etch stop Layer 206 is typically SiC, SiN, or SiCN, and is covered on the first dielectric Layer 205 by using a Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD), and the thickness thereof is 10nm to 50 nm; the second cap layer 208 is typically a high density SiO₂And depositing by using a CVD (chemical vapor deposition) process. The Planarization method generally employs Chemical Mechanical Planarization (CMP).

Step four: the fourth step is the same as the first step, as shown in FIG. 5(b) and FIG. 5 (c).

The foregoing detailed description of the preferred embodiments of the invention has been presented. It should be understood that numerous modifications and variations could be devised by those skilled in the art in light of the present teachings without departing from the inventive concepts. Therefore, the technical solutions available to those skilled in the art through logic analysis, reasoning and limited experiments based on the prior art according to the concept of the present invention should be within the scope of protection defined by the claims.

Claims

1. A method of fabricating a magnetic random access memory array cell, comprising the steps of:

step two, patterning a magnetic tunnel junction pattern, etching the multilayer film of the magnetic tunnel junction to form a magnetic tunnel junction, etching the metal layer of the bottom electrode to form a bottom electrode, and covering the magnetic tunnel junction and the bottom electrode with a first covering layer;

etching to form a bit line through hole, and filling metal copper in the bit line through hole, wherein in the main etching step, gas with high C/F content ratio is adopted as main etching gas; and taking the OES signal as an etching end point signal for judging the main etching step, and then selecting the main etching gas with low C/F content to etch the bit line through hole etching barrier layer, the first dielectric layer and the first covering layer in sequence.

2. A method of fabricating a magnetic random access memory array cell, comprising the steps of:

3. The method of claim 1 or 2, wherein the first capping layer is made of SiC, SiN or SiCN, and is formed by chemical vapor deposition, atomic layer deposition or ion beam deposition.

4. The method of claim 1 or 2, wherein in step three, the total thickness of the four layers of the first dielectric layer, the bit line via etch stop layer, the second dielectric layer, and the second capping layer is 120nm to 400 nm.

5. The method of claim 1 or 2, wherein the first dielectric layer and the second dielectric layer are SiO₂SiON or a low dielectric constant dielectric.

6. The method of claim 1 or 2, wherein the bit line via etch stop layer is made of SiC, SiN or SiCN and conformally covers the first dielectric layer by chemical vapor deposition or atomic layer deposition, and has a thickness of 10nm to 50 nm.

7. The method of claim 1 or 2, wherein the second capping layer is SiO₂And forming the second covering layer by adopting chemical vapor deposition.

8. The method of claim 1 or 2, wherein the main etching step for forming the bit line via hole is performed by using C₄F₈Or C₄F₆As the main etch gas.

9. The method of claim 8, wherein an optical emission spectrum signal of CN or CO is used as an etching end point signal for determining the main etching step.

10. The method of claim 8, wherein after the main etching step is completed, the bit line via etch stop layer, the first dielectric layer, and the first capping layer are sequentially etched using a low C/F content main etch gas, stopping on the top electrode film layer.